[llvm-mca] PR39261: Rename FetchStage to EntryStage.

[andreadb]

Summary

This fixes PR39261.

FetchStage is a misnomer. It causes confusion with the frontend fetch stage, which we don't currently simulate.
I decided to rename it into EntryStage mainly because this is meant to be a "source" stage for all pipelines.

Let me know if okay to commit.

Thanks,
Andrea

[mattd]

LGTM.

tools/llvm-mca/lib/CMakeLists.txt

18 ↗

(On Diff #173182)

nit: EntryStage should come before ExecuteStage.

tools/llvm-mca/lib/Context.cpp

24 ↗

(On Diff #173182)

nit: EntryStage should come before ExecuteStage.

[andreadb]

Thanks Matt, I will apply the suggested changes and then commit.

Cheers

llvm/trunk/tools/llvm-mca/include/Stages/EntryStage.h

+//===---------------------- EntryStage.h ------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file defines the Entry stage of an instruction pipeline.  Its sole
+/// purpose in life is to pick instructions in sequence and move them to the
+/// next pipeline stage.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TOOLS_LLVM_MCA_ENTRY_STAGE_H
+#define LLVM_TOOLS_LLVM_MCA_ENTRY_STAGE_H
+
+#include "SourceMgr.h"
+#include "Stages/Stage.h"
+#include <map>
+
+namespace llvm {
+namespace mca {
+
+class EntryStage final : public Stage {
+  InstRef CurrentInstruction;
+  using InstMap = std::map<unsigned, std::unique_ptr<Instruction>>;
+  InstMap Instructions;
+  SourceMgr &SM;
+
+  // Updates the program counter, and sets 'CurrentInstruction'.
+  void getNextInstruction();
+
+  EntryStage(const EntryStage &Other) = delete;
+  EntryStage &operator=(const EntryStage &Other) = delete;
+
+public:
+  EntryStage(SourceMgr &SM) : CurrentInstruction(), SM(SM) {}
+
+  bool isAvailable(const InstRef &IR) const override;
+  bool hasWorkToComplete() const override;
+  Error execute(InstRef &IR) override;
+  Error cycleStart() override;
+  Error cycleEnd() override;
+};
+
+} // namespace mca
+} // namespace llvm
+
+#endif // LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H

llvm/trunk/tools/llvm-mca/include/Stages/FetchStage.h

-//===---------------------- FetchStage.h ------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-/// \file
-///
-/// This file defines the Fetch stage of an instruction pipeline.  Its sole
-/// purpose in life is to produce instructions for the rest of the pipeline.
-///
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
-#define LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
-
-#include "SourceMgr.h"
-#include "Stages/Stage.h"
-#include <map>
-
-namespace llvm {
-namespace mca {
-
-class FetchStage final : public Stage {
-  InstRef CurrentInstruction;
-  using InstMap = std::map<unsigned, std::unique_ptr<Instruction>>;
-  InstMap Instructions;
-  SourceMgr &SM;
-
-  // Updates the program counter, and sets 'CurrentInstruction'.
-  void getNextInstruction();
-
-  FetchStage(const FetchStage &Other) = delete;
-  FetchStage &operator=(const FetchStage &Other) = delete;
-
-public:
-  FetchStage(SourceMgr &SM) : CurrentInstruction(), SM(SM) {}
-
-  bool isAvailable(const InstRef &IR) const override;
-  bool hasWorkToComplete() const override;
-  Error execute(InstRef &IR) override;
-  Error cycleStart() override;
-  Error cycleEnd() override;
-};
-
-} // namespace mca
-} // namespace llvm
-
-#endif // LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H

llvm/trunk/tools/llvm-mca/lib/CMakeLists.txt

 include_directories(${LLVM_MCA_SOURCE_DIR}/include)
 
 add_library(LLVMMCA
   STATIC
   Context.cpp
   HWEventListener.cpp
   HardwareUnits/HardwareUnit.cpp
   HardwareUnits/LSUnit.cpp
   HardwareUnits/RegisterFile.cpp
   HardwareUnits/ResourceManager.cpp
   HardwareUnits/RetireControlUnit.cpp
   HardwareUnits/Scheduler.cpp
   InstrBuilder.cpp
   Instruction.cpp
   Pipeline.cpp
   Stages/DispatchStage.cpp
+  Stages/EntryStage.cpp
   Stages/ExecuteStage.cpp
-  Stages/FetchStage.cpp
   Stages/InstructionTables.cpp
   Stages/RetireStage.cpp
   Stages/Stage.cpp
   Support.cpp
   )
 
 llvm_update_compile_flags(LLVMMCA)
 llvm_map_components_to_libnames(libs
   MC
   Support
   )
 
 target_link_libraries(LLVMMCA ${libs})
 set_target_properties(LLVMMCA PROPERTIES FOLDER "Libraries")

llvm/trunk/tools/llvm-mca/lib/Context.cpp

 ///
 //===----------------------------------------------------------------------===//
 
 #include "Context.h"
 #include "HardwareUnits/RegisterFile.h"
 #include "HardwareUnits/RetireControlUnit.h"
 #include "HardwareUnits/Scheduler.h"
 #include "Stages/DispatchStage.h"
+#include "Stages/EntryStage.h"
 #include "Stages/ExecuteStage.h"
-#include "Stages/FetchStage.h"
 #include "Stages/RetireStage.h"
 
 namespace llvm {
 namespace mca {
 
 std::unique_ptr<Pipeline>
 Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
                                SourceMgr &SrcMgr) {
   const MCSchedModel &SM = STI.getSchedModel();
 
   // Create the hardware units defining the backend.
   auto RCU = llvm::make_unique<RetireControlUnit>(SM);
   auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
   auto LSU = llvm::make_unique<LSUnit>(Opts.LoadQueueSize, Opts.StoreQueueSize,
                                        Opts.AssumeNoAlias);
   auto HWS = llvm::make_unique<Scheduler>(SM, LSU.get());
 
   // Create the pipeline stages.
-  auto Fetch = llvm::make_unique<FetchStage>(SrcMgr);
+  auto Fetch = llvm::make_unique<EntryStage>(SrcMgr);
   auto Dispatch = llvm::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
                                                    *RCU, *PRF);
   auto Execute = llvm::make_unique<ExecuteStage>(*HWS);
   auto Retire = llvm::make_unique<RetireStage>(*RCU, *PRF);
 
   // Pass the ownership of all the hardware units to this Context.
   addHardwareUnit(std::move(RCU));
   addHardwareUnit(std::move(PRF));

llvm/trunk/tools/llvm-mca/lib/Stages/EntryStage.cpp

+//===---------------------- EntryStage.cpp ----------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file defines the Fetch stage of an instruction pipeline.  Its sole
+/// purpose in life is to produce instructions for the rest of the pipeline.
+///
+//===----------------------------------------------------------------------===//
+
+#include "Stages/EntryStage.h"
+#include "Instruction.h"
+
+namespace llvm {
+namespace mca {
+
+bool EntryStage::hasWorkToComplete() const { return CurrentInstruction; }
+
+bool EntryStage::isAvailable(const InstRef & /* unused */) const {
+  if (CurrentInstruction)
+    return checkNextStage(CurrentInstruction);
+  return false;
+}
+
+void EntryStage::getNextInstruction() {
+  assert(!CurrentInstruction && "There is already an instruction to process!");
+  if (!SM.hasNext())
+    return;
+  SourceRef SR = SM.peekNext();
+  std::unique_ptr<Instruction> Inst = llvm::make_unique<Instruction>(SR.second);
+  CurrentInstruction = InstRef(SR.first, Inst.get());
+  Instructions[SR.first] = std::move(Inst);
+  SM.updateNext();
+}
+
+llvm::Error EntryStage::execute(InstRef & /*unused */) {
+  assert(CurrentInstruction && "There is no instruction to process!");
+  if (llvm::Error Val = moveToTheNextStage(CurrentInstruction))
+    return Val;
+
+  // Move the program counter.
+  CurrentInstruction.invalidate();
+  getNextInstruction();
+  return llvm::ErrorSuccess();
+}
+
+llvm::Error EntryStage::cycleStart() {
+  if (!CurrentInstruction)
+    getNextInstruction();
+  return llvm::ErrorSuccess();
+}
+
+llvm::Error EntryStage::cycleEnd() {
+  // Find the first instruction which hasn't been retired.
+  const InstMap::iterator It =
+      llvm::find_if(Instructions, [](const InstMap::value_type &KeyValuePair) {
+        return !KeyValuePair.second->isRetired();
+      });
+
+  // Erase instructions up to the first that hasn't been retired.
+  if (It != Instructions.begin())
+    Instructions.erase(Instructions.begin(), It);
+
+  return llvm::ErrorSuccess();
+}
+
+} // namespace mca
+} // namespace llvm

llvm/trunk/tools/llvm-mca/lib/Stages/FetchStage.cpp

-//===---------------------- FetchStage.cpp ----------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-/// \file
-///
-/// This file defines the Fetch stage of an instruction pipeline.  Its sole
-/// purpose in life is to produce instructions for the rest of the pipeline.
-///
-//===----------------------------------------------------------------------===//
-
-#include "Stages/FetchStage.h"
-#include "Instruction.h"
-
-namespace llvm {
-namespace mca {
-
-bool FetchStage::hasWorkToComplete() const { return CurrentInstruction; }
-
-bool FetchStage::isAvailable(const InstRef & /* unused */) const {
-  if (CurrentInstruction)
-    return checkNextStage(CurrentInstruction);
-  return false;
-}
-
-void FetchStage::getNextInstruction() {
-  assert(!CurrentInstruction && "There is already an instruction to process!");
-  if (!SM.hasNext())
-    return;
-  SourceRef SR = SM.peekNext();
-  std::unique_ptr<Instruction> Inst = llvm::make_unique<Instruction>(SR.second);
-  CurrentInstruction = InstRef(SR.first, Inst.get());
-  Instructions[SR.first] = std::move(Inst);
-  SM.updateNext();
-}
-
-llvm::Error FetchStage::execute(InstRef & /*unused */) {
-  assert(CurrentInstruction && "There is no instruction to process!");
-  if (llvm::Error Val = moveToTheNextStage(CurrentInstruction))
-    return Val;
-
-  // Move the program counter.
-  CurrentInstruction.invalidate();
-  getNextInstruction();
-  return llvm::ErrorSuccess();
-}
-
-llvm::Error FetchStage::cycleStart() {
-  if (!CurrentInstruction)
-    getNextInstruction();
-  return llvm::ErrorSuccess();
-}
-
-llvm::Error FetchStage::cycleEnd() {
-  // Find the first instruction which hasn't been retired.
-  const InstMap::iterator It =
-      llvm::find_if(Instructions, [](const InstMap::value_type &KeyValuePair) {
-        return !KeyValuePair.second->isRetired();
-      });
-
-  // Erase instructions up to the first that hasn't been retired.
-  if (It != Instructions.begin())
-    Instructions.erase(Instructions.begin(), It);
-
-  return llvm::ErrorSuccess();
-}
-
-} // namespace mca
-} // namespace llvm

llvm/trunk/tools/llvm-mca/llvm-mca.cpp

 // The cpu defaults to the 'native' host cpu.
 // The output defaults to standard output.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeRegion.h"
 #include "CodeRegionGenerator.h"
 #include "PipelinePrinter.h"
-#include "Stages/FetchStage.h"
+#include "Stages/EntryStage.h"
 #include "Stages/InstructionTables.h"
 #include "Views/DispatchStatistics.h"
 #include "Views/InstructionInfoView.h"
 #include "Views/RegisterFileStatistics.h"
 #include "Views/ResourcePressureView.h"
 #include "Views/RetireControlUnitStatistics.h"
 #include "Views/SchedulerStatistics.h"
 #include "Views/SummaryView.h"
for (const MCInst &MCI : Insts) {
       LoweredSequence.emplace_back(std::move(Inst.get()));
     }
 
     mca::SourceMgr S(LoweredSequence, PrintInstructionTables ? 1 : Iterations);
 
     if (PrintInstructionTables) {
       //  Create a pipeline, stages, and a printer.
       auto P = make_unique<mca::Pipeline>();
-      P->appendStage(make_unique<mca::FetchStage>(S));
+      P->appendStage(make_unique<mca::EntryStage>(S));
       P->appendStage(make_unique<mca::InstructionTables>(SM));
       mca::PipelinePrinter Printer(*P);
 
       // Create the views for this pipeline, execute, and emit a report.
       if (PrintInstructionInfoView) {
         Printer.addView(
             make_unique<mca::InstructionInfoView>(*STI, *MCII, Insts, *IP));
       }