[COFF, ARM64] Implement llvm.addressofreturnaddress intrinsic

[mgrang]

This comment was removed by mgrang.

[efriedma]

lib/Target/AArch64/AArch64ISelLowering.cpp

5238

This won't work for a varags function; in that case, this would point to the spill of r7, not lr. Maybe it would be more straightforward to just compute it as FP+8?

I think you need to call MFI.setFrameAddressIsTaken(true); or something like that to ensure lr is spilled.

[mgrang]

lib/Target/AArch64/AArch64ISelLowering.cpp

5238

MSVC always seem to generate: ldr lr,[sp],#0x10

[efriedma]

LGTM

[mgrang]

The previous version failed to apply cleanly. So had to rebase.

docs/LangRef.rst

 
 Semantics:
 """"""""""
 
 Note that calling this intrinsic does not prevent function inlining or
 other aggressive transformations, so the value returned may not be that
 of the obvious source-language caller.
 
-This intrinsic is only implemented for x86.
+This intrinsic is only implemented for x86 and aarch64.
 
 '``llvm.frameaddress``' Intrinsic
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Syntax:
 """""""
 
 ::

lib/Target/AArch64/AArch64ISelLowering.cpp

SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
   case ISD::FP_ROUND:
     return LowerFP_ROUND(Op, DAG);
   case ISD::FP_EXTEND:
     return LowerFP_EXTEND(Op, DAG);
   case ISD::FRAMEADDR:
     return LowerFRAMEADDR(Op, DAG);
   case ISD::RETURNADDR:
     return LowerRETURNADDR(Op, DAG);
+  case ISD::ADDROFRETURNADDR:
+    return LowerADDROFRETURNADDR(Op, DAG);
   case ISD::INSERT_VECTOR_ELT:
     return LowerINSERT_VECTOR_ELT(Op, DAG);
   case ISD::EXTRACT_VECTOR_ELT:
     return LowerEXTRACT_VECTOR_ELT(Op, DAG);
   case ISD::BUILD_VECTOR:
     return LowerBUILD_VECTOR(Op, DAG);
   case ISD::VECTOR_SHUFFLE:
     return LowerVECTOR_SHUFFLE(Op, DAG);
if (((Reg == AArch64::X1 || Reg == AArch64::W1) &&
       !Subtarget->isXRegisterReserved(20)))
     Reg = 0;
   if (Reg)
     return Reg;
   report_fatal_error(Twine("Invalid register name \""
                               + StringRef(RegName)  + "\"."));
 }
 
+SDValue AArch64TargetLowering::LowerADDROFRETURNADDR(SDValue Op,
+                                                     SelectionDAG &DAG) const {
+  DAG.getMachineFunction().getFrameInfo().setFrameAddressIsTaken(true);
+
+  EVT VT = Op.getValueType();
+  SDLoc DL(Op);
+
+  SDValue FrameAddr =
+      DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
+  SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
+
+  return DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset);
+}
+
 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
                                                SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   MFI.setReturnAddressIsTaken(true);
 
   EVT VT = Op.getValueType();
   SDLoc DL(Op);

test/CodeGen/AArch64/addr-of-ret-addr.ll

+; RUN: llc < %s -disable-fp-elim -mtriple=arm64-windows | FileCheck %s
+
+; Test generated from C code:
+; #include <stdarg.h>
+; void *foo() {
+;   return _AddressOfReturnAddress();
+; }
+; int bar(int x(va_list, void*), ...) {
+;   va_list y;
+;   va_start(y, x);
+;   return x(y, _AddressOfReturnAddress()) + 1;
+; }
+
+declare void @llvm.va_start(i8*)
+declare i8* @llvm.addressofreturnaddress()
+
+define dso_local i8* @"foo"() {
+entry:
+  %0 = call i8* @llvm.addressofreturnaddress()
+  ret i8* %0
+
+; CHECK-LABEL: foo
+; CHECK: stp x29, x30, [sp, #-16]!
+; CHECK: mov x29, sp
+; CHECK: add x0, x29, #8
+; CHECK: ldp x29, x30, [sp], #16
+}
+
+define dso_local i32 @"bar"(i32 (i8*, i8*)* %x, ...) {
+entry:
+  %x.addr = alloca i32 (i8*, i8*)*, align 8
+  %y = alloca i8*, align 8
+  store i32 (i8*, i8*)* %x, i32 (i8*, i8*)** %x.addr, align 8
+  %y1 = bitcast i8** %y to i8*
+  call void @llvm.va_start(i8* %y1)
+  %0 = load i32 (i8*, i8*)*, i32 (i8*, i8*)** %x.addr, align 8
+  %1 = call i8* @llvm.addressofreturnaddress()
+  %2 = load i8*, i8** %y, align 8
+  %call = call i32 %0(i8* %2, i8* %1)
+  %add = add nsw i32 %call, 1
+  ret i32 %add
+
+; CHECK-LABEL: bar
+; CHECK: sub sp, sp, #96
+; CHECK: stp x29, x30, [sp, #16]
+; CHECK: add x29, sp, #16
+; CHECK: str x1, [x29, #24]
+; CHECK: add x1, x29, #8
+; CHECK: ldp x29, x30, [sp, #16]
+; CHECK: add sp, sp, #96
+}