This is an archive of the discontinued LLVM Phabricator instance.

[COFF, ARM64] Implement llvm.addressofreturnaddress intrinsic
ClosedPublic

Authored by mgrang on Oct 31 2018, 5:41 PM.

Diff Detail

Repository
rL LLVM

Event Timeline

mgrang created this revision.Oct 31 2018, 5:41 PM
This comment was removed by mgrang.
mgrang updated this revision to Diff 172070.Oct 31 2018, 5:47 PM
efriedma added inline comments.Oct 31 2018, 5:55 PM
lib/Target/AArch64/AArch64ISelLowering.cpp
5238 ↗(On Diff #172068)

This won't work for a varags function; in that case, this would point to the spill of r7, not lr. Maybe it would be more straightforward to just compute it as FP+8?

I think you need to call MFI.setFrameAddressIsTaken(true); or something like that to ensure lr is spilled.

mgrang added inline comments.Oct 31 2018, 5:59 PM
lib/Target/AArch64/AArch64ISelLowering.cpp
5238 ↗(On Diff #172068)

MSVC always seem to generate: ldr lr,[sp],#0x10

mgrang updated this revision to Diff 172225.Nov 1 2018, 1:48 PM
efriedma accepted this revision.Nov 1 2018, 1:51 PM

LGTM

This revision is now accepted and ready to land.Nov 1 2018, 1:51 PM
mgrang updated this revision to Diff 172233.Nov 1 2018, 2:22 PM
mgrang set the repository for this revision to rL LLVM.

The previous version failed to apply cleanly. So had to rebase.

This revision was automatically updated to reflect the committed changes.