[AArch64] [Windows] SEH opcodes should be scheduling boundaries.

[efriedma]

Summary

Prevents the post-RA scheduler from modifying the prologue sequences emitting by frame lowering. This is roughly similar to what we do for other targets: TargetInstrInfo::isSchedulingBoundary checks isPosition(), which checks for CFI_INSTRUCTION.

isSEHInstruction is taken from D50288; it'll land with whatever patch lands first.

[rnk]

From reading the docs for isSchedulingBoundary, yes, definitely:

/// isSchedulingBoundary - Test if the given instruction should be
/// considered a scheduling boundary. This primarily includes labels
/// and terminators.

Fundamentally, SEH instructions are labels for unwind info.

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h

public:
   bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
                        unsigned, unsigned, int &, int &, int &) const override;
   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                     const DebugLoc &DL, unsigned DstReg,
                     ArrayRef<MachineOperand> Cond, unsigned TrueReg,
                     unsigned FalseReg) const override;
   void getNoop(MCInst &NopInst) const override;
 
+  bool isSchedulingBoundary(const MachineInstr &MI,
+                            const MachineBasicBlock *MBB,
+                            const MachineFunction &MF) const override;
+
   /// analyzeCompare - For a comparison instruction, return the source registers
   /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
   /// Return true if the comparison instruction can be analyzed.
   bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
                       unsigned &SrcReg2, int &CmpMask,
                       int &CmpValue) const override;
   /// optimizeCompareInstr - Convert the instruction supplying the argument to
   /// the comparison into one that sets the zero bit in the flags register.
public:
   /// more efficiently.
   bool isExynosLdStExtFast(const MachineInstr &MI) const;
   /// Returns true if the instruction has a constant shift left or extension
   /// that can be executed more efficiently.
   bool isExynosShiftExtFast(const MachineInstr &MI) const;
   /// Returns true if the instruction has a shift by immediate that can be
   /// executed in one cycle less.
   bool isFalkorShiftExtFast(const MachineInstr &MI) const;
+  /// Return true if the instructions is a SEH instruciton used for unwinding
+  /// on Windows.
+  static bool isSEHInstruction(const MachineInstr &MI);
 
 private:
   /// Sets the offsets on outlined instructions in \p MBB which use SP
   /// so that they will be valid post-outlining.
   ///
   /// \param MBB A \p MachineBasicBlock in an outlined function.
   void fixupPostOutline(MachineBasicBlock &MBB) const;
 

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

bool AArch64InstrInfo::isFalkorShiftExtFast(const MachineInstr &MI) const {
   case AArch64::STRXroW:
   case AArch64::STRXroX: {
     unsigned IsSigned = MI.getOperand(3).getImm();
     return !IsSigned;
   }
   }
 }
 
+bool AArch64InstrInfo::isSEHInstruction(const MachineInstr &MI) {
+  unsigned Opc = MI.getOpcode();
+  switch (Opc) {
+    default:
+      return false;
+    case AArch64::SEH_StackAlloc:
+    case AArch64::SEH_SaveFPLR:
+    case AArch64::SEH_SaveFPLR_X:
+    case AArch64::SEH_SaveReg:
+    case AArch64::SEH_SaveReg_X:
+    case AArch64::SEH_SaveRegP:
+    case AArch64::SEH_SaveRegP_X:
+    case AArch64::SEH_SaveFReg:
+    case AArch64::SEH_SaveFReg_X:
+    case AArch64::SEH_SaveFRegP:
+    case AArch64::SEH_SaveFRegP_X:
+    case AArch64::SEH_SetFP:
+    case AArch64::SEH_AddFP:
+    case AArch64::SEH_Nop:
+    case AArch64::SEH_PrologEnd:
+    case AArch64::SEH_EpilogStart:
+    case AArch64::SEH_EpilogEnd:
+      return true;
+  }
+}
+
 bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
                                              unsigned &SrcReg, unsigned &DstReg,
                                              unsigned &SubIdx) const {
   switch (MI.getOpcode()) {
   default:
     return false;
   case AArch64::SBFMXri: // aka sxtw
   case AArch64::UBFMXri: // aka uxtw
if (BaseRegA == BaseRegB) {
       int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
       if (LowOffset + LowWidth <= HighOffset)
         return true;
     }
   }
   return false;
 }
 
+bool AArch64InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
+                                            const MachineBasicBlock *MBB,
+                                            const MachineFunction &MF) const {
+  if (TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF))
+    return true;
+  return isSEHInstruction(MI);
+}
+
 /// analyzeCompare - For a comparison instruction, return the source registers
 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
 /// Return true if the comparison instruction can be analyzed.
 bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
                                       unsigned &SrcReg2, int &CmpMask,
                                       int &CmpValue) const {
   // The first operand can be a frame index where we'd normally expect a
   // register.

llvm/trunk/test/CodeGen/AArch64/wineh1.mir

-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj -disable-post-ra \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj  \
 # RUN:   | llvm-readobj -unwind | FileCheck %s
 # This test case checks the basic validity of the .xdata section.  It's
 # documented at:
 # https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
 
 # We expect to see the following in the .xdata section:
 
 # CHECK:   ExceptionData {

llvm/trunk/test/CodeGen/AArch64/wineh2.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN:   -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
+# RUN:    -filetype=obj | llvm-readobj -unwind | FileCheck %s
 # Test that the pre/post increment save of a flating point register is correct.
 
 # CHECK:        ExceptionData {
 # CHECK-NEXT:      FunctionLength: 136
 # CHECK-NEXT:      Version: 0
 # CHECK-NEXT:      ExceptionData: No
 # CHECK-NEXT:      EpiloguePacked: No
 # CHECK-NEXT:      EpilogueScopes: 1

llvm/trunk/test/CodeGen/AArch64/wineh3.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN:   -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
+# RUN:    -filetype=obj | llvm-readobj -unwind | FileCheck %s
 # Test that the register pairing of both general purpose and floating point
 # registers is correctly saved in the .xdata section, as well as the pre/post
 # increment of floating point register pairs.
 
 # CHECK:        ExceptionData {
 # CHECK-NEXT:      FunctionLength: 124
 # CHECK-NEXT:      Version: 0
 # CHECK-NEXT:      ExceptionData: No

llvm/trunk/test/CodeGen/AArch64/wineh4.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN:   -disable-branch-fold -disable-post-ra -filetype=obj \
+# RUN:   -disable-branch-fold  -filetype=obj \
 # RUN: | llvm-readobj -unwind | FileCheck %s
 # Check that multiple epilgoues are correctly placed in .xdata.
 
 # CHECK:        ExceptionData {
 # CHECK-NEXT:      FunctionLength: 164
 # CHECK-NEXT:      Version: 0
 # CHECK-NEXT:      ExceptionData: No
 # CHECK-NEXT:      EpiloguePacked: No

llvm/trunk/test/CodeGen/AArch64/wineh5.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN:   -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
+# RUN:    -filetype=obj | llvm-readobj -unwind | FileCheck %s
 
 # Check that that the large stack allocation is correctly represented in .xdata.
 
 # CHECK:        ExceptionData {
 # CHECK-NEXT:     FunctionLength: 156
 # CHECK-NEXT:     Version: 0
 # CHECK-NEXT:     ExceptionData: No
 # CHECK-NEXT:     EpiloguePacked: No

llvm/trunk/test/CodeGen/AArch64/wineh6.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN:   -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
+# RUN:    -filetype=obj | llvm-readobj -unwind | FileCheck %s
 # Check save_fplr_x, set_fp, alloc_s
 
 # CHECK:  ExceptionData {
 # CHECK-NEXT:      FunctionLength: 92
 # CHECK-NEXT:      Version: 0
 # CHECK-NEXT:      ExceptionData: No
 # CHECK-NEXT:      EpiloguePacked: No
 # CHECK-NEXT:      EpilogueScopes: 1

llvm/trunk/test/CodeGen/AArch64/wineh7.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
-# RUN:   -filetype=obj -disable-post-ra | llvm-readobj -unwind | FileCheck %s
+# RUN:   -filetype=obj  | llvm-readobj -unwind | FileCheck %s
 # Check AddFP
 
 # CHECK:   ExceptionData {
 # CHECK-NEXT:      FunctionLength: 72
 # CHECK-NEXT:      Version: 0
 # CHECK-NEXT:      ExceptionData: No
 # CHECK-NEXT:      EpiloguePacked: No
 # CHECK-NEXT:      EpilogueScopes: 1