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Differential D53848

[ARM] Add missing pseudo-instruction for Thumb1 RSBS.
ClosedPublic

Authored by efriedma on Oct 29 2018, 4:22 PM.

Details

Reviewers
dmgreen
t.p.northover
rogfer01
Commits
rG063fd98bcc06: [ARM] Add missing pseudo-instruction for Thumb1 RSBS.
rL345782: [ARM] Add missing pseudo-instruction for Thumb1 RSBS.
Summary

Shows up rarely for 64-bit arithmetic, more frequently for the compare patterns added in r325323.

Diff Detail

Repository
rL LLVM

Event Timeline

efriedma created this revision.Oct 29 2018, 4:22 PM
Herald added subscribers: chrib, kristof.beyls, javed.absar. · View Herald TranscriptOct 29 2018, 4:22 PM
rogfer01 accepted this revision.Oct 30 2018, 12:19 AM

Hi @efriedma thanks a lot for this improvement.

LGTM.

This revision is now accepted and ready to land.Oct 30 2018, 12:19 AM
Closed by commit rL345782: [ARM] Add missing pseudo-instruction for Thumb1 RSBS. (authored by efriedma). · Explain WhyOct 31 2018, 2:48 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
ARM/
1 line
6 lines
test/
CodeGen/
ARM/
42 lines
6 lines
12 lines
2 lines
Thumb/
9 lines
3 lines

Diff 171606

lib/Target/ARM/ARMBaseInstrInfo.cpp

Show First 20 Lines • Show All 2,193 Lines • ▼ Show 20 Linesstatic const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
{ARM::tADDSi8, ARM::tADDi8}, {ARM::tADDSi8, ARM::tADDi8},
{ARM::tADDSrr, ARM::tADDrr}, {ARM::tADDSrr, ARM::tADDrr},
{ARM::tADCS, ARM::tADC}, {ARM::tADCS, ARM::tADC},
{ARM::tSUBSi3, ARM::tSUBi3}, {ARM::tSUBSi3, ARM::tSUBi3},
{ARM::tSUBSi8, ARM::tSUBi8}, {ARM::tSUBSi8, ARM::tSUBi8},
{ARM::tSUBSrr, ARM::tSUBrr}, {ARM::tSUBSrr, ARM::tSUBrr},
{ARM::tSBCS, ARM::tSBC}, {ARM::tSBCS, ARM::tSBC},
{ARM::tRSBS, ARM::tRSB},
{ARM::t2ADDSri, ARM::t2ADDri}, {ARM::t2ADDSri, ARM::t2ADDri},
{ARM::t2ADDSrr, ARM::t2ADDrr}, {ARM::t2ADDSrr, ARM::t2ADDrr},
{ARM::t2ADDSrs, ARM::t2ADDrs}, {ARM::t2ADDSrs, ARM::t2ADDrs},
{ARM::t2SUBSri, ARM::t2SUBri}, {ARM::t2SUBSri, ARM::t2SUBri},
{ARM::t2SUBSrr, ARM::t2SUBrr}, {ARM::t2SUBSrr, ARM::t2SUBrr},
{ARM::t2SUBSrs, ARM::t2SUBrs}, {ARM::t2SUBSrs, ARM::t2SUBrs},
▲ Show 20 Lines • Show All 2,899 Lines • Show Last 20 Lines

lib/Target/ARM/ARMInstrThumb.td

Show First 20 Lines • Show All 1,337 Lines • ▼ Show 20 Lines def tSUBSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
Sched<[WriteALU]>; Sched<[WriteALU]>;
def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
2, IIC_iALUr, 2, IIC_iALUr,
[(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn, [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn,
tGPR:$Rm))]>, tGPR:$Rm))]>,
Requires<[IsThumb1Only]>, Requires<[IsThumb1Only]>,
Sched<[WriteALU]>; Sched<[WriteALU]>;
def tRSBS : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn),
2, IIC_iALUr,
[(set tGPR:$Rd, CPSR, (ARMsubc 0, tGPR:$Rn))]>,
Requires<[IsThumb1Only]>,
Sched<[WriteALU]>;
} }
// Sign-extend byte // Sign-extend byte
def tSXTB : // A8.6.222 def tSXTB : // A8.6.222
T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
IIC_iUNAr, IIC_iUNAr,
"sxtb", "\t$Rd, $Rm", "sxtb", "\t$Rd, $Rm",
[(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
▲ Show 20 Lines • Show All 357 Lines • Show Last 20 Lines

test/CodeGen/ARM/and-load-combine.ll

Show All 22 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_xor8_short_short: ; THUMB1-LABEL: cmp_xor8_short_short:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0] ; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1] ; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: eors r1, r0 ; THUMB1-NEXT: eors r1, r0
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_xor8_short_short: ; THUMB2-LABEL: cmp_xor8_short_short:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ldrb r1, [r1] ; THUMB2-NEXT: ldrb r1, [r1]
; THUMB2-NEXT: eors r0, r1 ; THUMB2-NEXT: eors r0, r1
Show All 28 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_xor8_short_int: ; THUMB1-LABEL: cmp_xor8_short_int:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0] ; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1] ; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: eors r1, r0 ; THUMB1-NEXT: eors r1, r0
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_xor8_short_int: ; THUMB2-LABEL: cmp_xor8_short_int:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ldrb r1, [r1] ; THUMB2-NEXT: ldrb r1, [r1]
; THUMB2-NEXT: eors r0, r1 ; THUMB2-NEXT: eors r0, r1
Show All 29 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_xor8_int_int: ; THUMB1-LABEL: cmp_xor8_int_int:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0] ; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1] ; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: eors r1, r0 ; THUMB1-NEXT: eors r1, r0
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_xor8_int_int: ; THUMB2-LABEL: cmp_xor8_int_int:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ldrb r1, [r1] ; THUMB2-NEXT: ldrb r1, [r1]
; THUMB2-NEXT: eors r0, r1 ; THUMB2-NEXT: eors r0, r1
Show All 28 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_xor16: ; THUMB1-LABEL: cmp_xor16:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrh r0, [r0] ; THUMB1-NEXT: ldrh r0, [r0]
; THUMB1-NEXT: ldrh r1, [r1] ; THUMB1-NEXT: ldrh r1, [r1]
; THUMB1-NEXT: eors r1, r0 ; THUMB1-NEXT: eors r1, r0
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_xor16: ; THUMB2-LABEL: cmp_xor16:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrh r0, [r0] ; THUMB2-NEXT: ldrh r0, [r0]
; THUMB2-NEXT: ldrh r1, [r1] ; THUMB2-NEXT: ldrh r1, [r1]
; THUMB2-NEXT: eors r0, r1 ; THUMB2-NEXT: eors r0, r1
Show All 28 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_or8_short_short: ; THUMB1-LABEL: cmp_or8_short_short:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0] ; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1] ; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: orrs r1, r0 ; THUMB1-NEXT: orrs r1, r0
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_or8_short_short: ; THUMB2-LABEL: cmp_or8_short_short:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ldrb r1, [r1] ; THUMB2-NEXT: ldrb r1, [r1]
; THUMB2-NEXT: orrs r0, r1 ; THUMB2-NEXT: orrs r0, r1
Show All 28 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_or8_short_int: ; THUMB1-LABEL: cmp_or8_short_int:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0] ; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1] ; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: orrs r1, r0 ; THUMB1-NEXT: orrs r1, r0
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_or8_short_int: ; THUMB2-LABEL: cmp_or8_short_int:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ldrb r1, [r1] ; THUMB2-NEXT: ldrb r1, [r1]
; THUMB2-NEXT: orrs r0, r1 ; THUMB2-NEXT: orrs r0, r1
Show All 29 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_or8_int_int: ; THUMB1-LABEL: cmp_or8_int_int:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0] ; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1] ; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: orrs r1, r0 ; THUMB1-NEXT: orrs r1, r0
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_or8_int_int: ; THUMB2-LABEL: cmp_or8_int_int:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ldrb r1, [r1] ; THUMB2-NEXT: ldrb r1, [r1]
; THUMB2-NEXT: orrs r0, r1 ; THUMB2-NEXT: orrs r0, r1
Show All 28 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_or16: ; THUMB1-LABEL: cmp_or16:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrh r0, [r0] ; THUMB1-NEXT: ldrh r0, [r0]
; THUMB1-NEXT: ldrh r1, [r1] ; THUMB1-NEXT: ldrh r1, [r1]
; THUMB1-NEXT: orrs r1, r0 ; THUMB1-NEXT: orrs r1, r0
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_or16: ; THUMB2-LABEL: cmp_or16:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrh r0, [r0] ; THUMB2-NEXT: ldrh r0, [r0]
; THUMB2-NEXT: ldrh r1, [r1] ; THUMB2-NEXT: ldrh r1, [r1]
; THUMB2-NEXT: orrs r0, r1 ; THUMB2-NEXT: orrs r0, r1
Show All 28 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_and8_short_short: ; THUMB1-LABEL: cmp_and8_short_short:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r1, [r1] ; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: ldrb r2, [r0] ; THUMB1-NEXT: ldrb r2, [r0]
; THUMB1-NEXT: ands r2, r1 ; THUMB1-NEXT: ands r2, r1
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r2, #0
; THUMB1-NEXT: subs r0, r0, r2
; THUMB1-NEXT: adcs r0, r2 ; THUMB1-NEXT: adcs r0, r2
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_and8_short_short: ; THUMB2-LABEL: cmp_and8_short_short:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r1, [r1] ; THUMB2-NEXT: ldrb r1, [r1]
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ands r0, r1 ; THUMB2-NEXT: ands r0, r1
Show All 28 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_and8_short_int: ; THUMB1-LABEL: cmp_and8_short_int:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0] ; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1] ; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: ands r1, r0 ; THUMB1-NEXT: ands r1, r0
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_and8_short_int: ; THUMB2-LABEL: cmp_and8_short_int:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ldrb r1, [r1] ; THUMB2-NEXT: ldrb r1, [r1]
; THUMB2-NEXT: ands r0, r1 ; THUMB2-NEXT: ands r0, r1
Show All 29 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_and8_int_int: ; THUMB1-LABEL: cmp_and8_int_int:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r1, [r1] ; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: ldrb r2, [r0] ; THUMB1-NEXT: ldrb r2, [r0]
; THUMB1-NEXT: ands r2, r1 ; THUMB1-NEXT: ands r2, r1
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r2, #0
; THUMB1-NEXT: subs r0, r0, r2
; THUMB1-NEXT: adcs r0, r2 ; THUMB1-NEXT: adcs r0, r2
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_and8_int_int: ; THUMB2-LABEL: cmp_and8_int_int:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r1, [r1] ; THUMB2-NEXT: ldrb r1, [r1]
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ands r0, r1 ; THUMB2-NEXT: ands r0, r1
Show All 28 Lines
; ARMEB-NEXT: lsr r0, r0, #5 ; ARMEB-NEXT: lsr r0, r0, #5
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: cmp_and16: ; THUMB1-LABEL: cmp_and16:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrh r1, [r1] ; THUMB1-NEXT: ldrh r1, [r1]
; THUMB1-NEXT: ldrh r2, [r0] ; THUMB1-NEXT: ldrh r2, [r0]
; THUMB1-NEXT: ands r2, r1 ; THUMB1-NEXT: ands r2, r1
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r2, #0
; THUMB1-NEXT: subs r0, r0, r2
; THUMB1-NEXT: adcs r0, r2 ; THUMB1-NEXT: adcs r0, r2
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: cmp_and16: ; THUMB2-LABEL: cmp_and16:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrh r1, [r1] ; THUMB2-NEXT: ldrh r1, [r1]
; THUMB2-NEXT: ldrh r0, [r0] ; THUMB2-NEXT: ldrh r0, [r0]
; THUMB2-NEXT: ands r0, r1 ; THUMB2-NEXT: ands r0, r1
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: test6: ; THUMB1-LABEL: test6:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0] ; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ands r0, r1 ; THUMB1-NEXT: ands r0, r1
; THUMB1-NEXT: uxtb r1, r2 ; THUMB1-NEXT: uxtb r1, r2
; THUMB1-NEXT: subs r1, r0, r1 ; THUMB1-NEXT: subs r1, r0, r1
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: test6: ; THUMB2-LABEL: test6:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ands r0, r1 ; THUMB2-NEXT: ands r0, r1
; THUMB2-NEXT: uxtb r1, r2 ; THUMB2-NEXT: uxtb r1, r2
Show All 30 Lines
; ARMEB-NEXT: bx lr ; ARMEB-NEXT: bx lr
; ;
; THUMB1-LABEL: test7: ; THUMB1-LABEL: test7:
; THUMB1: @ %bb.0: @ %entry ; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0] ; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ands r0, r1 ; THUMB1-NEXT: ands r0, r1
; THUMB1-NEXT: uxtb r1, r2 ; THUMB1-NEXT: uxtb r1, r2
; THUMB1-NEXT: subs r1, r0, r1 ; THUMB1-NEXT: subs r1, r0, r1
; THUMB1-NEXT: movs r0, #0 ; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: subs r0, r0, r1
; THUMB1-NEXT: adcs r0, r1 ; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr ; THUMB1-NEXT: bx lr
; ;
; THUMB2-LABEL: test7: ; THUMB2-LABEL: test7:
; THUMB2: @ %bb.0: @ %entry ; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0] ; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: ands r0, r1 ; THUMB2-NEXT: ands r0, r1
; THUMB2-NEXT: uxtb r1, r2 ; THUMB2-NEXT: uxtb r1, r2
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test/CodeGen/ARM/atomic-cmpxchg.ll

Show All 18 Lines
; CHECK-ARM: sub r0, r0, {{r[0-9]+}} ; CHECK-ARM: sub r0, r0, {{r[0-9]+}}
; CHECK-ARM: rsbs [[REG:r[0-9]+]], r0, #0 ; CHECK-ARM: rsbs [[REG:r[0-9]+]], r0, #0
; CHECK-ARM: adc r0, r0, [[REG]] ; CHECK-ARM: adc r0, r0, [[REG]]
; CHECK-THUMB-LABEL: test_cmpxchg_res_i8 ; CHECK-THUMB-LABEL: test_cmpxchg_res_i8
; CHECK-THUMB: bl __sync_val_compare_and_swap_1 ; CHECK-THUMB: bl __sync_val_compare_and_swap_1
; CHECK-THUMB-NOT: mov [[R1:r[0-7]]], r0 ; CHECK-THUMB-NOT: mov [[R1:r[0-7]]], r0
; CHECK-THUMB: subs [[R1:r[0-7]]], r0, {{r[0-9]+}} ; CHECK-THUMB: subs [[R1:r[0-7]]], r0, {{r[0-9]+}}
; CHECK-THUMB: movs r0, #0 ; CHECK-THUMB: rsbs r0, [[R1]], #0
; CHECK-THUMB: subs r0, r0, [[R1]]
; CHECK-THUMB: adcs r0, [[R1]] ; CHECK-THUMB: adcs r0, [[R1]]
; CHECK-ARMV6-LABEL: test_cmpxchg_res_i8: ; CHECK-ARMV6-LABEL: test_cmpxchg_res_i8:
; CHECK-ARMV6-NEXT: .fnstart ; CHECK-ARMV6-NEXT: .fnstart
; CHECK-ARMV6-NEXT: uxtb [[DESIRED:r[0-9]+]], r1 ; CHECK-ARMV6-NEXT: uxtb [[DESIRED:r[0-9]+]], r1
; CHECK-ARMV6-NEXT: [[TRY:.LBB[0-9_]+]]: ; CHECK-ARMV6-NEXT: [[TRY:.LBB[0-9_]+]]:
; CHECK-ARMV6-NEXT: ldrexb [[LD:r[0-9]+]], [r0] ; CHECK-ARMV6-NEXT: ldrexb [[LD:r[0-9]+]], [r0]
; CHECK-ARMV6-NEXT: cmp [[LD]], [[DESIRED]] ; CHECK-ARMV6-NEXT: cmp [[LD]], [[DESIRED]]
; CHECK-ARMV6-NEXT: movne [[RES:r[0-9]+]], #0 ; CHECK-ARMV6-NEXT: movne [[RES:r[0-9]+]], #0
; CHECK-ARMV6-NEXT: bxne lr ; CHECK-ARMV6-NEXT: bxne lr
; CHECK-ARMV6-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0] ; CHECK-ARMV6-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]
; CHECK-ARMV6-NEXT: cmp [[SUCCESS]], #0 ; CHECK-ARMV6-NEXT: cmp [[SUCCESS]], #0
; CHECK-ARMV6-NEXT: moveq [[RES]], #1 ; CHECK-ARMV6-NEXT: moveq [[RES]], #1
; CHECK-ARMV6-NEXT: bxeq lr ; CHECK-ARMV6-NEXT: bxeq lr
; CHECK-ARMV6-NEXT: b [[TRY]] ; CHECK-ARMV6-NEXT: b [[TRY]]
; CHECK-THUMBV6-LABEL: test_cmpxchg_res_i8: ; CHECK-THUMBV6-LABEL: test_cmpxchg_res_i8:
; CHECK-THUMBV6: mov [[EXPECTED:r[0-9]+]], r1 ; CHECK-THUMBV6: mov [[EXPECTED:r[0-9]+]], r1
; CHECK-THUMBV6-NEXT: bl __sync_val_compare_and_swap_1 ; CHECK-THUMBV6-NEXT: bl __sync_val_compare_and_swap_1
; CHECK-THUMBV6-NEXT: uxtb r1, r4 ; CHECK-THUMBV6-NEXT: uxtb r1, r4
; CHECK-THUMBV6-NEXT: subs [[R1:r[0-7]]], r0, {{r[0-9]+}} ; CHECK-THUMBV6-NEXT: subs [[R1:r[0-7]]], r0, {{r[0-9]+}}
; CHECK-THUMBV6-NEXT: movs r0, #0 ; CHECK-THUMBV6-NEXT: rsbs r0, [[R1]], #0
; CHECK-THUMBV6-NEXT: subs r0, r0, [[R1]]
; CHECK-THUMBV6-NEXT: adcs r0, [[R1]] ; CHECK-THUMBV6-NEXT: adcs r0, [[R1]]
; CHECK-ARMV7-LABEL: test_cmpxchg_res_i8: ; CHECK-ARMV7-LABEL: test_cmpxchg_res_i8:
; CHECK-ARMV7-NEXT: .fnstart ; CHECK-ARMV7-NEXT: .fnstart
; CHECK-ARMV7-NEXT: uxtb [[DESIRED:r[0-9]+]], r1 ; CHECK-ARMV7-NEXT: uxtb [[DESIRED:r[0-9]+]], r1
; CHECK-ARMV7-NEXT: b [[TRY:.LBB[0-9_]+]] ; CHECK-ARMV7-NEXT: b [[TRY:.LBB[0-9_]+]]
; CHECK-ARMV7-NEXT: [[HEAD:.LBB[0-9_]+]]: ; CHECK-ARMV7-NEXT: [[HEAD:.LBB[0-9_]+]]:
; CHECK-ARMV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0] ; CHECK-ARMV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]
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test/CodeGen/ARM/select-imm.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; ARM: rsbs r1, r0, #0 ; ARM: rsbs r1, r0, #0
; ARM: adc r0, r0, r1 ; ARM: adc r0, r0, r1
; ARMT2-LABEL: t3: ; ARMT2-LABEL: t3:
; ARMT2: clz r0, r0 ; ARMT2: clz r0, r0
; ARMT2: lsr r0, r0, #5 ; ARMT2: lsr r0, r0, #5
; THUMB1-LABEL: t3: ; THUMB1-LABEL: t3:
; THUMB1: movs r1, #0 ; THUMB1: rsbs r1, r0, #0
; THUMB1: subs r1, r1, r0
; THUMB1: adcs r0, r1 ; THUMB1: adcs r0, r1
; THUMB2-LABEL: t3: ; THUMB2-LABEL: t3:
; THUMB2: clz r0, r0 ; THUMB2: clz r0, r0
; THUMB2: lsrs r0, r0, #5 ; THUMB2: lsrs r0, r0, #5
%0 = icmp eq i32 %a, 160 %0 = icmp eq i32 %a, 160
%1 = zext i1 %0 to i32 %1 = zext i1 %0 to i32
ret i32 %1 ret i32 %1
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; ARM-NOT: mov ; ARM-NOT: mov
; ARM: sub r0, r0, #1 ; ARM: sub r0, r0, #1
; ARM-NOT: mov ; ARM-NOT: mov
; ARM: rsbs r1, r0, #0 ; ARM: rsbs r1, r0, #0
; ARM: adc r0, r0, r1 ; ARM: adc r0, r0, r1
; THUMB1-LABEL: t5: ; THUMB1-LABEL: t5:
; THUMB1-NOT: bne ; THUMB1-NOT: bne
; THUMB1: movs r0, #0 ; THUMB1: rsbs r0, r1, #0
; THUMB1: subs r0, r0, r1
; THUMB1: adcs r0, r1 ; THUMB1: adcs r0, r1
; THUMB2-LABEL: t5: ; THUMB2-LABEL: t5:
; THUMB2-NOT: mov ; THUMB2-NOT: mov
; THUMB2: subs r0, #1 ; THUMB2: subs r0, #1
; THUMB2: clz r0, r0 ; THUMB2: clz r0, r0
; THUMB2: lsrs r0, r0, #5 ; THUMB2: lsrs r0, r0, #5
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; ARMT2: sub r0, r4, #5 ; ARMT2: sub r0, r4, #5
; ARMT2: clz r0, r0 ; ARMT2: clz r0, r0
; ARMT2: lsr r0, r0, #5 ; ARMT2: lsr r0, r0, #5
; THUMB1-LABEL: t8: ; THUMB1-LABEL: t8:
; THUMB1: bl t7 ; THUMB1: bl t7
; THUMB1: mov r1, r0 ; THUMB1: mov r1, r0
; THUMB1: subs r2, r4, #5 ; THUMB1: subs r2, r4, #5
; THUMB1: movs r0, #0 ; THUMB1: rsbs r0, r2, #0
; THUMB1: subs r0, r0, r2
; THUMB1: adcs r0, r2 ; THUMB1: adcs r0, r2
; THUMB2-LABEL: t8: ; THUMB2-LABEL: t8:
; THUMB2: bl t7 ; THUMB2: bl t7
; THUMB2: mov r1, r0 ; THUMB2: mov r1, r0
; THUMB2: subs r0, r4, #5 ; THUMB2: subs r0, r4, #5
; THUMB2: clz r0, r0 ; THUMB2: clz r0, r0
; THUMB2: lsrs r0, r0, #5 ; THUMB2: lsrs r0, r0, #5
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; ARM: rsbs r1, r0, #0 ; ARM: rsbs r1, r0, #0
; ARM: adc r0, r0, r1 ; ARM: adc r0, r0, r1
; ARMT2-LABEL: t10: ; ARMT2-LABEL: t10:
; ARMT2: clz r0, r0 ; ARMT2: clz r0, r0
; ARMT2: lsr r0, r0, #5 ; ARMT2: lsr r0, r0, #5
; THUMB1-LABEL: t10: ; THUMB1-LABEL: t10:
; THUMB1: movs r0, #0 ; THUMB1: rsbs r0, r1, #0
; THUMB1: subs r0, r0, r1
; THUMB1: adcs r0, r1 ; THUMB1: adcs r0, r1
; THUMB2-LABEL: t10: ; THUMB2-LABEL: t10:
; THUMB2: clz r0, r0 ; THUMB2: clz r0, r0
; THUMB2: lsrs r0, r0, #5 ; THUMB2: lsrs r0, r0, #5
; V8MBASE-LABEL: t10: ; V8MBASE-LABEL: t10:
; V8MBASE-NOT: movs r0, #0 ; V8MBASE-NOT: movs r0, #0
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test/CodeGen/ARM/smml.ll

Show All 38 Linesentry:
%conv3 = trunc i64 %shr7 to i32 %conv3 = trunc i64 %shr7 to i32
ret i32 %conv3 ret i32 %conv3
} }
declare void @opaque(i32) declare void @opaque(i32)
define void @test_used_flags(i32 %in1, i32 %in2) { define void @test_used_flags(i32 %in1, i32 %in2) {
; CHECK-LABEL: test_used_flags: ; CHECK-LABEL: test_used_flags:
; CHECK-THUMB: movs r2, #0 ; CHECK-THUMB: movs r2, #0
; CHECK-THUMB: subs r0, r2, r0 ; CHECK-THUMB: rsbs r0, r0, #0
; CHECK-THUMB: sbcs r2, r1 ; CHECK-THUMB: sbcs r2, r1
; CHECK-THUMB: bge ; CHECK-THUMB: bge
; CHECK-V6: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1 ; CHECK-V6: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
; CHECK-V6: rsbs {{.*}}, [[PROD_LO]], #0 ; CHECK-V6: rsbs {{.*}}, [[PROD_LO]], #0
; CHECK-V6: rscs {{.*}}, [[PROD_HI]], #0 ; CHECK-V6: rscs {{.*}}, [[PROD_HI]], #0
; CHECK-THUMBV6T2: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1 ; CHECK-THUMBV6T2: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
; CHECK-THUMBV6T2: movs [[ZERO:r[0-9]+]], #0 ; CHECK-THUMBV6T2: movs [[ZERO:r[0-9]+]], #0
; CHECK-THUMBV6T2: rsbs {{.*}}, [[PROD_LO]], #0 ; CHECK-THUMBV6T2: rsbs {{.*}}, [[PROD_LO]], #0
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test/CodeGen/Thumb/branchless-cmp.ll

Show All 14 Lines
define i32 @test1b(i32 %a, i32 %b) { define i32 @test1b(i32 %a, i32 %b) {
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%cond = zext i1 %cmp to i32 %cond = zext i1 %cmp to i32
ret i32 %cond ret i32 %cond
; CHECK-LABEL: test1b: ; CHECK-LABEL: test1b:
; CHECK-NOT: b{{(ne)|(eq)}} ; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r1, r0, r1 ; CHECK: subs r1, r0, r1
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: rsbs r0, r1, #0
; CHECK-NEXT: subs r0, r0, r1
; CHECK-NEXT: adcs r0, r1 ; CHECK-NEXT: adcs r0, r1
} }
define i32 @test2a(i32 %a, i32 %b) { define i32 @test2a(i32 %a, i32 %b) {
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%cond = zext i1 %cmp to i32 %cond = zext i1 %cmp to i32
ret i32 %cond ret i32 %cond
; CHECK-LABEL: test2a: ; CHECK-LABEL: test2a:
; CHECK-NOT: b{{(ne)|(eq)}} ; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r1, r0, r1 ; CHECK: subs r1, r0, r1
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: rsbs r0, r1, #0
; CHECK-NEXT: subs r0, r0, r1
; CHECK-NEXT: adcs r0, r1 ; CHECK-NEXT: adcs r0, r1
} }
define i32 @test2b(i32 %a, i32 %b) { define i32 @test2b(i32 %a, i32 %b) {
entry: entry:
%cmp = icmp ne i32 %a, %b %cmp = icmp ne i32 %a, %b
%cond = zext i1 %cmp to i32 %cond = zext i1 %cmp to i32
ret i32 %cond ret i32 %cond
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define i32 @test3b(i32 %a, i32 %b) { define i32 @test3b(i32 %a, i32 %b) {
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%cond = select i1 %cmp, i32 4, i32 0 %cond = select i1 %cmp, i32 4, i32 0
ret i32 %cond ret i32 %cond
; CHECK-LABEL: test3b: ; CHECK-LABEL: test3b:
; CHECK-NOT: b{{(ne)|(eq)}} ; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r0, r0, r1 ; CHECK: subs r0, r0, r1
; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: subs r1, r1, r0
; CHECK-NEXT: adcs r1, r0 ; CHECK-NEXT: adcs r1, r0
; CHECK-NEXT: lsls r0, r1, #2 ; CHECK-NEXT: lsls r0, r1, #2
} }
; FIXME: This one hasn't changed actually ; FIXME: This one hasn't changed actually
; but could look like test3b ; but could look like test3b
define i32 @test4a(i32 %a, i32 %b) { define i32 @test4a(i32 %a, i32 %b) {
entry: entry:
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test/CodeGen/Thumb/long-setcc.ll

; RUN: llc -mtriple=thumb-eabi < %s | FileCheck %s ; RUN: llc -mtriple=thumb-eabi < %s | FileCheck %s
define i1 @t1(i64 %x) { define i1 @t1(i64 %x) {
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: lsrs r0, r1, #31 ; CHECK: lsrs r0, r1, #31
%B = icmp slt i64 %x, 0 %B = icmp slt i64 %x, 0
ret i1 %B ret i1 %B
} }
define i1 @t2(i64 %x) { define i1 @t2(i64 %x) {
; CHECK-LABEL: t2: ; CHECK-LABEL: t2:
; CHECK: movs r0, #0 ; CHECK: rsbs r0, r1, #0
; CHECK: subs r0, r0, r1
; CHECK: adcs r0, r1 ; CHECK: adcs r0, r1
%tmp = icmp ult i64 %x, 4294967296 %tmp = icmp ult i64 %x, 4294967296
ret i1 %tmp ret i1 %tmp
} }
define i1 @t3(i32 %x) { define i1 @t3(i32 %x) {
; CHECK-LABEL: t3: ; CHECK-LABEL: t3:
; CHECK: movs r0, #0 ; CHECK: movs r0, #0
%tmp = icmp ugt i32 %x, -1 %tmp = icmp ugt i32 %x, -1
ret i1 %tmp ret i1 %tmp
} }
; CHECK-NOT: cmp ; CHECK-NOT: cmp