[PATCH] FastISel fixes with FeatureVSX enabled

[seurer]

Summary

Test case and FastISel fixes with FeatureVSX enabled

There are a number of test cases that fail if FeatureVSX is turned on.

Many of them use options that aren't compatible with VSX (like -m32 or darwin
targets). I just disabled vsx (via -mattr=-vsx) for these.

The rest are looking for specific instructions that are not generated with
FeatureVSX enabled. I added -mattr=-vsx to the existing test checks for these
and then added new checks specific to VSX to look for the VSX instructions that
are generated instead.

The FastISel code cannot handle VSX registers and various assertion checks
will fail if one is encountered when it runs. I changed all the places in
FastISEL that allocate registers to check for VSX registers and return false
if one is found so that the regular code gen can handle it.

[mcrosier]

Added Daniel and Reed as reviews.

[echristo]

Wrong reviewers. :)

This is PPC you want one of these.

[echristo]

This should probably all be handled via the isTypeLegal machinery rather than this cut and paste.

Thanks!

-eric

[hfinkel]

Thanks for working on this!

Regarding approach, instead of disabling parts of FastISel when VSX is enabled, why don't we disable VSX when FastISel would be used? For example, what if in PPCSubtarget::initSubtargetFeatures we added something like this after the call to ParseSubtargetFeatures:

if (OptLevel == CodeGenOpt::None) or even better if possible (TM.Options.EnableFastISel)
  HasVSX = false;

(we already do something similar for little-Endian mode currently). Then we just need to add an assert in the FastISel implementation that VSX is not enabled.

As a general note, please upload full-context diffs in the future (see http://llvm.org/docs/Phabricator.html for instructions).

[seurer]

In D5362#12, @hfinkel wrote:

Thanks for working on this!

Regarding approach, instead of disabling parts of FastISel when VSX is enabled, why don't we disable VSX when FastISel would be used? For example, what if in PPCSubtarget::initSubtargetFeatures we added something like this after the call to ParseSubtargetFeatures:

if (OptLevel == CodeGenOpt::None) or even better if possible (TM.Options.EnableFastISel)
  HasVSX = false;

(we already do something similar for little-Endian mode currently). Then we just need to add an assert in the FastISel implementation that VSX is not enabled.

How about changing getRegForValue to return 0 if it ends up with a VSX register. All the uses of getRegForValue already check for a 0 return value. That moves the code to just one spot and there are already multiple checks there for things that FastISel can't handle.

As a general note, please upload full-context diffs in the future (see http://llvm.org/docs/Phabricator.html for instructions).

Will do.

[seurer]

New IsTypeLegal function added to FastISel
Overrides for IsTypeLegal added to PPCFastIsel
Some additional test case updates, mostly with option changes

[wschmidt]

Hi Bill,

This looks much better with the checking all in one place -- thanks for doing that! I don't see any problems with the patch from my end -- will defer to Hal and Eric whether their concerns are all handled.

I see we will have an opportunity to improve code gen for mcm-12.ll. Using the indexed-form VSX instruction allows use of more registers but means we need an extra addi in this sequence over just using lfd. But that's for the future...

[hfinkel]

/home/seurer/llvm/llvm-test/include/llvm/CodeGen/FastISel.h

486

Do other targets break if you make this call their two-argument isTypeLegal with a throw-away VT argument?

I'd rather do this in a way that targets don't need to provide two very-similar overrides and keep them in sync if possible.

/home/seurer/llvm/llvm-test/lib/Target/PowerPC/PPCFastISel.cpp

264

Not sure about f128 (it is not a legal type, and I assume the base class will take care of this), but if ppcf128 should be here, please add it.

[seurer]

Added const to isTypeLegal functions
Removed comment about f128 types

[seurer]

Removed default FeatureVSX in PPC.td
Two changes in FastISel.cpp to avoid svn code merge problems

After discussing this with Bill Schmidt we decided to not turn on FeatureVSX by default. There are some recent code updates elsewhere (unrelated to this) which cause register issues when FeatureVSX is turned on.

[echristo]

Out of curiosity, why not this patch?

dzur:~/sources/llvm> git diff
diff --git a/lib/Target/PowerPC/PPCFastISel.cpp
b/lib/Target/PowerPC/PPCFastISel.cpp
index 99aa4ea..b36c5c8 100644

• a/lib/Target/PowerPC/PPCFastISel.cpp

+++ b/lib/Target/PowerPC/PPCFastISel.cpp
@@ -2284,7 +2284,7 @@ namespace llvm {

// Only available on 64-bit ELF for now.
const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();

• if (Subtarget->isPPC64() && Subtarget->isSVR4ABI())

+ if (Subtarget->isPPC64() && Subtarget->isSVR4ABI() && !Subtarget->hasVSX())

  return new PPCFastISel(FuncInfo, LibInfo);

return nullptr;

[seurer]

Changes to fma.ll to fix merging

[echristo]

Not such a huge fan of the new EVT code. This is what the Type *, MVT
& code is for. What's giving you an EVT where you're not checking for
simple?

I.e. I see no reason this shouldn't work like:

bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {

EVT E = TLI.getValueType(Ty, true);

// Only handle simple types.
if (E == MVT::Other || !E.isSimple())
  return false;
VT = E.getSimpleVT();

if (VT == MVT::f64 || VT.isVector())
  return false;

return TLI.isTypeLegal(VT);

}

(though do we handle f64 or vectors if we don't have VSX? Do we need
both checks? etc)

-eric

[echristo]

OK, after some more looking I see where you're going with this. I
think the various bits can be unified under the isTypeLegal I brought
up before and making that virtual with the simple check it looks like
all of them check for MVT::isSimple() first.. You might need to pull
out the Other check though.

Few comments on the patch otherwise:

+++ /home/seurer/llvm/llvm-test/test/CodeGen/Generic/select-cc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s
+; RUN: llc -mattr=-vsx < %s

This is a generic codegen test. You can't change it this way.

+++ /home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/2007-09-08-unaligned.ll
@@ -1,7 +1,11 @@
-; RUN: llc < %s | grep stfd | count 3
-; RUN: llc < %s | grep stfs | count 1
-; RUN: llc < %s | grep lfd | count 2
-; RUN: llc < %s | grep lfs | count 2
+; RUN: llc -mattr=-vsx < %s | grep stfd | count 3
+; RUN: llc -mattr=-vsx < %s | grep stfs | count 1
+; RUN: llc -mattr=-vsx < %s | grep lfd | count 2
+; RUN: llc -mattr=-vsx < %s | grep lfs | count 2
+; RUN: llc -mattr=+vsx < %s | grep stxsdx | count 3
+; RUN: llc -mattr=+vsx < %s | grep stfs | count 1
+; RUN: llc -mattr=+vsx < %s | grep lxsdx | count 2
+; RUN: llc -mattr=+vsx < %s | grep lfs | count 2

This appears unrelated to fast-isel?

+++ /home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/2012-10-12-bitcast.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mattr=+altivec < %s | FileCheck %s
+; RUN: llc -mattr=-vsx -mattr=+altivec < %s | FileCheck %s
+; RUN: llc -mattr=+vsx -mattr=+altivec < %s | FileCheck -check-prefix=VSX %s

Ditto.

+++ /home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/buildvec_canonicalize.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math

FileCheck %s

+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+altivec
--enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -mattr=+altivec
--enable-unsafe-fp-math | FileCheck -check-prefix=VSX %s

Ditto.

+++ /home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/copysignl.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu
-mattr=-vsx < %s | FileCheck %s -check-prefix=NOVSX
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu
-mattr=+vsx < %s | FileCheck %s -check-prefix=VSX

Ditto.

+++ /home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fabs.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
+; RUN: llc < %s -mattr=-vsx -march=ppc32
-mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
+; RUN: llc < %s -mattr=+vsx -march=ppc32
-mtriple=powerpc-apple-darwin | grep "xsabsdp f1, f1"

Ditto.

+++ /home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fast-isel-call.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort
-mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
--check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx
-fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 |
FileCheck %s --check-prefix=ELF64

Do we really want to change almost every pwr7 fast isel test to remove
the vsx attribute just because bits of the tests don't work? I'm not
sure I've got a better solution, but this seems really heavy handed.

-; ELF64-LABEL: ret2
+; ELF64: ret2

Seems an orthogonal change?

+++ /home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fma.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32 -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -fp-contract=fast | FileCheck %s

This appears unrelated to fast-isel? (Along with everything that
doesn't use -O0 on the llc command line).

+++ /home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fsel.ll
@@ -1,5 +1,6 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
-enable-no-infs-fp-math -enable-no-nans-fp-math | FileCheck
-check-prefix=CHECK-FM %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
-mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
-enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx |
FileCheck -check-prefix=CHECK-FM %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
-enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx |
FileCheck -check-prefix=CHECK-FM-VSX %s
target datalayout =
"E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

@@ -16,6 +17,10 @@
; CHECK-FM: @zerocmp1
; CHECK-FM: fsel 1, 1, 2, 3
; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp1
+; CHECK-FM-VSX: fsel 1, 1, 2, 3
+; CHECK-FM-VSX: blr

Another orthogonal test change?

There's more seemingly of these as well, but calling out each one
separately seems to be a bit verbose.

Thoughts?

-eric

[seurer]

As per the discussion I have changed this to only contain the code fixes.

[wschmidt]

The current diff looks fine to me, and I'd be happy to commit it for you. Eric, I had difficulty parsing your last comment, but I believe this follows the direction you were pursuing. Any problem with moving forward on this one?

[wschmidt]

/me adds a light and airy *ping* to the discussion thread. ;)

[wschmidt]

I've been thinking about this a bit more, and I'm not very happy with a solution that changes the general FastISel machinery, given that it's intended to be temporary. I think seurer is making pretty good progress on the real solution for VSX in FastISel, so it might be best to suck it up and wait for that to be completed. Thoughts?

BTW, from a note he sent me this morning I have a feeling that FastISel may be ignoring AddedComplexity in the pattern selection code. The VSX pattern should be preferred over the other when available, but the non-VSX pattern code is being generated first, which doesn't give the VSX pattern a chance. Eric, is this possible?

[echristo]

In D5362#35, @wschmidt wrote:

I've been thinking about this a bit more, and I'm not very happy with a solution that changes the general FastISel machinery, given that it's intended to be temporary. I think seurer is making pretty good progress on the real solution for VSX in FastISel, so it might be best to suck it up and wait for that to be completed. Thoughts?

This is definitely my preference here. As a temporary solution I'm absolutely ok with checking if VSX is enabled and just disabling fastisel.

BTW, from a note he sent me this morning I have a feeling that FastISel may be ignoring AddedComplexity in the pattern selection code. The VSX pattern should be preferred over the other when available, but the non-VSX pattern code is being generated first, which doesn't give the VSX pattern a chance. Eric, is this possible?

I'm fairly certain we don't pay attention to AddedComplexity in fast isel. One solution would be to change the order of those patterns in the file I think. At least might be worth a try.

-eric

[seurer]

Superseded by [llvm] r223507

/home/seurer/llvm/llvm-test/include/llvm/CodeGen/FastISel.h

protected:
   virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; }
 
   /// \brief Emit the floating-point constant +0.0 in a register using target-
   /// specific logic.
   virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) {
     return 0;
   }
 
+  /// \brief Verify that a type is valid for FastISel.  Should be overriden
+  /// by targets with more restrictive type legality in FastIsel.
+  virtual bool isTypeLegal(EVT Evt) {
+    return TLI.isTypeLegal(Evt);
+  }
+
   /// \brief Check if \c Add is an add that can be safely folded into \c GEP.
   ///
   /// \c Add can be folded into \c GEP if:
   /// - \c Add is an add,
   /// - \c Add's size matches \c GEP's,
   /// - \c Add is in the same basic block as \c GEP, and
   /// - \c Add has a constant operand.
   bool canFoldAddIntoGEP(const User *GEP, const Value *Add);

/home/seurer/llvm/llvm-test/lib/CodeGen/SelectionDAG/FastISel.cpp

unsigned FastISel::getRegForValue(const Value *V) {
   // Don't handle non-simple values in FastISel.
   if (!RealVT.isSimple())
     return 0;
 
   // Ignore illegal types. We must do this before looking up the value
   // in ValueMap because Arguments are given virtual registers regardless
   // of whether FastISel can handle them.
   MVT VT = RealVT.getSimpleVT();
-  if (!TLI.isTypeLegal(VT)) {
+  if (!isTypeLegal(RealVT)) {
     // Handle integer promotions, though, because they're common and easy.
     if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
       VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
     else
       return 0;
   }
 
   // Look up the value to see if we already have a register for it.
bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
   if (VT == MVT::Other || !VT.isSimple())
     // Unhandled type. Halt "fast" selection and bail.
     return false;
 
   // We only handle legal types. For example, on x86-32 the instruction
   // selector contains all of the 64-bit instructions from x86-64,
   // under the assumption that i64 won't be used if the target doesn't
   // support it.
-  if (!TLI.isTypeLegal(VT)) {
+  if (!isTypeLegal(VT)) {
     // MVT::i1 is special. Allow AND, OR, or XOR because they
     // don't require additional zeroing, which makes them easy.
     if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
                           ISDOpcode == ISD::XOR))
       VT = TLI.getTypeToTransformTo(I->getContext(), VT);
     else
       return false;
   }
bool FastISel::selectCast(const User *I, unsigned Opcode) {
   EVT DstVT = TLI.getValueType(I->getType());
 
   if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
       !DstVT.isSimple())
     // Unhandled type. Halt "fast" selection and bail.
     return false;
 
   // Check if the destination type is legal.
-  if (!TLI.isTypeLegal(DstVT))
+  if (!isTypeLegal(DstVT))
     return false;
 
   // Check if the source operand is legal.
-  if (!TLI.isTypeLegal(SrcVT))
+  if (!isTypeLegal(SrcVT))
     return false;
 
   unsigned InputReg = getRegForValue(I->getOperand(0));
   if (!InputReg)
     // Unhandled operand.  Halt "fast" selection and bail.
     return false;
 
   bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
if (I->getType() == I->getOperand(0)->getType()) {
     updateValueMap(I, Reg);
     return true;
   }
 
   // Bitcasts of other values become reg-reg copies or BITCAST operators.
   EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType());
   EVT DstEVT = TLI.getValueType(I->getType());
   if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
-      !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
+      !isTypeLegal(SrcEVT) || !isTypeLegal(DstEVT))
     // Unhandled type. Halt "fast" selection and bail.
     return false;
 
   MVT SrcVT = SrcEVT.getSimpleVT();
   MVT DstVT = DstEVT.getSimpleVT();
   unsigned Op0 = getRegForValue(I->getOperand(0));
   if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
     return false;
if (ResultReg) {
     return true;
   }
 
   // Bitcast the value to integer, twiddle the sign bit with xor,
   // and then bitcast it back to floating-point.
   if (VT.getSizeInBits() > 64)
     return false;
   EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
-  if (!TLI.isTypeLegal(IntVT))
+  if (!isTypeLegal(IntVT))
     return false;
 
   unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
                                ISD::BITCAST, OpReg, OpRegIsKill);
   if (!IntReg)
     return false;
 
   unsigned IntResultReg = fastEmit_ri_(
if (!EVI)
     return false;
 
   // Make sure we only try to handle extracts with a legal result.  But also
   // allow i1 because it's easy.
   EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
   if (!RealVT.isSimple())
     return false;
   MVT VT = RealVT.getSimpleVT();
-  if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
+  if (!isTypeLegal(RealVT) && VT != MVT::i1)
     return false;
 
   const Value *Op0 = EVI->getOperand(0);
   Type *AggTy = Op0->getType();
 
   // Get the base result register.
   unsigned ResultReg;
   DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
for (BasicBlock::const_iterator I = SuccBB->begin();
 
       // Only handle legal types. Two interesting things to note here. First,
       // by bailing out early, we may leave behind some dead instructions,
       // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
       // own moves. Second, this check is necessary because FastISel doesn't
       // use CreateRegs to create registers, so it always creates
       // exactly one register for each non-void instruction.
       EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
-      if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
+      if (VT == MVT::Other || !isTypeLegal(VT)) {
         // Handle integer promotions, though, because they're common and easy.
         if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
           VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
         else {
           FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
           return false;
         }
       }
CmpInst::Predicate FastISel::optimizeCmpPredicate(const CmpInst *CI) const {
   case CmpInst::ICMP_SGT:   Predicate = CmpInst::FCMP_FALSE; break;
   case CmpInst::ICMP_SGE:   Predicate = CmpInst::FCMP_TRUE;  break;
   case CmpInst::ICMP_SLT:   Predicate = CmpInst::FCMP_FALSE; break;
   case CmpInst::ICMP_SLE:   Predicate = CmpInst::FCMP_TRUE;  break;
   }
 
   return Predicate;
 }
 No newline at end of file

/home/seurer/llvm/llvm-test/lib/Target/PowerPC/PPC.td

 def : ProcessorModel<"pwr6x", G5Model,
                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX,
                    FeatureFPRND, Feature64Bit,
                    DeprecatedMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr7", P7Model,
-                  [DirectivePwr7, FeatureAltivec,
+                  [DirectivePwr7, FeatureAltivec, FeatureVSX,
                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
                    FeaturePOPCNTD, FeatureLDBRX,
                    Feature64Bit /*, Feature64BitRegs */,
                    DeprecatedMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */,
-                  [DirectivePwr8, FeatureAltivec,
+                  [DirectivePwr8, FeatureAltivec, FeatureVSX,
                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
                    FeaturePOPCNTD, FeatureLDBRX,
                    Feature64Bit /*, Feature64BitRegs */,
                    DeprecatedMFTB, DeprecatedDST]>;
 def : Processor<"ppc", G3Itineraries, [Directive32]>;

/home/seurer/llvm/llvm-test/lib/Target/PowerPC/PPCFastISel.cpp

unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
                              uint64_t Imm);
     unsigned fastEmitInst_r(unsigned MachineInstOpcode,
                             const TargetRegisterClass *RC,
                             unsigned Op0, bool Op0IsKill);
     unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
                              const TargetRegisterClass *RC,
                              unsigned Op0, bool Op0IsKill,
                              unsigned Op1, bool Op1IsKill);
+    bool isTypeLegal(EVT VT) override;
 
   // Instruction selection routines.
   private:
     bool SelectLoad(const Instruction *I);
     bool SelectStore(const Instruction *I);
     bool SelectBranch(const Instruction *I);
     bool SelectIndirectBr(const Instruction *I);
     bool SelectFPExt(const Instruction *I);
     bool SelectFPTrunc(const Instruction *I);
     bool SelectIToFP(const Instruction *I, bool IsSigned);
     bool SelectFPToI(const Instruction *I, bool IsSigned);
     bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
     bool SelectCall(const Instruction *I);
     bool SelectRet(const Instruction *I);
     bool SelectTrunc(const Instruction *I);
     bool SelectIntExt(const Instruction *I);
 
   // Utility routines.
   private:
+    bool isTypeLegalCommon(EVT Evt, MVT &VT);
     bool isTypeLegal(Type *Ty, MVT &VT);
     bool isLoadTypeLegal(Type *Ty, MVT &VT);
     bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
                     bool isZExt, unsigned DestReg);
     bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
                      const TargetRegisterClass *RC, bool IsZExt = true,
                      unsigned FP64LoadOpc = PPC::LFD);
     bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
switch (Pred) {
     case CmpInst::FCMP_ORD:
       return PPC::PRED_NU;
 
     case CmpInst::FCMP_UNO:
       return PPC::PRED_UN;
   }
 }
 
-// Determine whether the type Ty is simple enough to be handled by
-// fast-isel, and return its equivalent machine type in VT.
-// FIXME: Copied directly from ARM -- factor into base class?
-bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
-  EVT Evt = TLI.getValueType(Ty, true);
-
+// Utility function for the following two functions that determines
+// whether the extended value type Evt is simple enough to be handled
+// by fast-isel.  The equivalent machine type is returned in VT.
+bool PPCFastISel::isTypeLegalCommon(EVT Evt, MVT &VT) {
   // Only handle simple types.
   if (Evt == MVT::Other || !Evt.isSimple()) return false;
+  // Note: overwrites VT's (second parameter's) value
   VT = Evt.getSimpleVT();
 
+  // FastISel can't handle VSX registers (yet).
+  // FIXME: remove when VSX support is added.
+  // note: f128 and ppcf128 are not included for now but should be added
+  if (PPCSubTarget->hasVSX() && (VT.isVector() || VT == MVT::f64)) {    
+   return false;
+  }
+
   // Handle all legal types, i.e. a register that will directly hold this
   // value.
   return TLI.isTypeLegal(VT);
 }
 
 // Determine whether the type Ty is simple enough to be handled by
+// fast-isel, and return its equivalent machine type in VT.
+bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
+  EVT Evt = TLI.getValueType(Ty, true);
+  return isTypeLegalCommon(Evt, VT);
+}
+
+// Determine whether the extended value type Evt is simple enough to be handled
+// by fast-isel.
+bool PPCFastISel::isTypeLegal(EVT Evt) {
+  MVT VT;
+  return isTypeLegalCommon(Evt, VT);
+}
+
+// Determine whether the type Ty is simple enough to be handled by
 // fast-isel as a load target, and return its equivalent machine type in VT.
 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
   if (isTypeLegal(Ty, VT)) return true;
 
   // If this is a type than can be sign or zero-extended to a basic operation
   // go ahead and accept it now.
   if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
     return true;
if (isa<ConstantInt>(*RV)) {
 
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
             TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
 
       RetRegs.push_back(RetReg);
 
     } else {
       unsigned Reg = getRegForValue(RV);
-
       if (Reg == 0)
         return false;
 
       // Copy the result values into the output registers.
       for (unsigned i = 0; i < ValLocs.size(); ++i) {
 
         CCValAssign &VA = ValLocs[i];
         assert(VA.isRegLoc() && "Can only return in registers!");

/home/seurer/llvm/llvm-test/test/CodeGen/Generic/select-cc.ll

-; RUN: llc < %s
+; RUN: llc -mattr=-vsx < %s
 ; PR2504
 ; XFAIL: hexagon
 define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind  {
   %x.lo = extractelement <2 x double> %x, i32 0    ; <double> [#uses=1]
   %x.lo.ge = fcmp oge double %x.lo, 0.000000e+00    ; <i1> [#uses=1]
   %a.d = select i1 %x.lo.ge, <2 x double> %y, <2 x double> %x    ; <<2 x double>> [#uses=1]
   ret <2 x double> %a.d
 }

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/2007-09-08-unaligned.ll

-; RUN: llc < %s | grep stfd | count 3
-; RUN: llc < %s | grep stfs | count 1
-; RUN: llc < %s | grep lfd | count 2
-; RUN: llc < %s | grep lfs | count 2
+; RUN: llc -mattr=-vsx < %s | grep stfd | count 3
+; RUN: llc -mattr=-vsx < %s | grep stfs | count 1
+; RUN: llc -mattr=-vsx < %s | grep lfd | count 2
+; RUN: llc -mattr=-vsx < %s | grep lfs | count 2
+; RUN: llc -mattr=+vsx < %s | grep stxsdx | count 3
+; RUN: llc -mattr=+vsx < %s | grep stfs | count 1
+; RUN: llc -mattr=+vsx < %s | grep lxsdx | count 2
+; RUN: llc -mattr=+vsx < %s | grep lfs | count 2
 ; ModuleID = 'foo.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
 target triple = "powerpc-apple-darwin8"
   %struct.anon = type <{ i8, float }>
 @s = global %struct.anon <{ i8 3, float 0x4014666660000000 }>    ; <%struct.anon*> [#uses=1]
 @u = global <{ i8, double }> <{ i8 3, double 5.100000e+00 }>    ; <<{ i8, double }>*> [#uses=1]
 @t = weak global %struct.anon zeroinitializer   ; <%struct.anon*> [#uses=2]
 @v = weak global <{ i8, double }> zeroinitializer    ; <<{ i8, double }>*> [#uses=2]

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/2012-10-12-bitcast.ll

-; RUN: llc -mattr=+altivec < %s | FileCheck %s
+; RUN: llc -mattr=-vsx -mattr=+altivec < %s | FileCheck %s
+; RUN: llc -mattr=+vsx -mattr=+altivec < %s | FileCheck -check-prefix=VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @test(<16 x i8> %v) nounwind {
 entry:
   %0 = bitcast <16 x i8> %v to i128
   %1 = lshr i128 %0, 96
   %2 = trunc i128 %1 to i32
   ret i32 %2
 }
 
 ; Verify that bitcast handles big-endian platforms correctly
 ; by checking we load the result from the correct offset
 
 ; CHECK: addi [[REGISTER:[0-9]+]], 1, -16
 ; CHECK: stvx 2, 0, [[REGISTER]]
 ; CHECK: lwz 3, -16(1)
 ; CHECK: blr
 
+; VSX: addi [[REGISTER:[0-9]+]], 1, -16
+; VSX: stxvd2x 34, 0, [[REGISTER]]
+; VSX: lwz 3, -16(1)
+; VSX: blr

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/buildvec_canonicalize.ll

-; RUN: llc < %s -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck -check-prefix=VSX %s
 
 define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
         %tmp = load <4 x float>* %P3            ; <<4 x float>> [#uses=1]
         %tmp3 = load <4 x float>* %P1           ; <<4 x float>> [#uses=1]
         %tmp4 = fmul <4 x float> %tmp, %tmp3             ; <<4 x float>> [#uses=1]
         store <4 x float> %tmp4, <4 x float>* %P3
         store <4 x float> zeroinitializer, <4 x float>* %P1
         store <4 x i32> zeroinitializer, <4 x i32>* %P2
         ret void
 }
 ; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
 ; to vmaddfp (so it would IEEE compliant with zero sign propagation).
 ; CHECK: @VXOR
 ; CHECK: vsplti
 ; CHECK: vxor
+; VSX: @VXOR
+; VSX: vxor
+; VSX: xvmulsp
 
 define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) {
         store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), <4 x i32>* %P2
         store <8 x i16> < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >, <8 x i16>* %P3
         ret void
 }
 ; CHECK: @VSPLTI
 ; CHECK: vsplti
+; VSX: @VSPLTI
+; VSX: vsplti

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/copysignl.ll

-; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=-vsx < %s | FileCheck %s -check-prefix=NOVSX
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s -check-prefix=VSX
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @foo_d_ll(ppc_fp128 %a, ppc_fp128 %b) #0 {
 entry:
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %a, ppc_fp128 %b) #0
   %conv = fptrunc ppc_fp128 %call to double
   ret double %conv
 
-; CHECK-LABEL: @foo_d_ll
-; CHECK: fcpsgn 1, 3, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_d_ll
+; NOVSX: fcpsgn 1, 3, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_d_ll
+; VSX: xscpsgndp 1, 3, 1
+; VSX: blr
 }
 
 declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) #0
 
 define double @foo_dl(double %a, ppc_fp128 %b) #0 {
 entry:
   %conv = fptrunc ppc_fp128 %b to double
   %call = tail call double @copysign(double %a, double %conv) #0
   ret double %call
 
-; CHECK-LABEL: @foo_dl
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_dl
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_dl
+; VSX: xscpsgndp 1, 2, 1
+; VSX: blr
 }
 
 declare double @copysign(double, double) #0
 
 define ppc_fp128 @foo_ll(double %a, ppc_fp128 %b) #0 {
 entry:
   %conv = fpext double %a to ppc_fp128
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %b) #0
   ret ppc_fp128 %call
 
-; CHECK-LABEL: @foo_ll
-; CHECK: bl copysignl
-; CHECK: blr
+; NOVSX-LABEL: @foo_ll
+; NOVSX: bl copysignl
+; NOVSX: blr
+; VSX-LABEL: @foo_ll
+; VSX: bl copysignl
+; VSX: blr
 }
 
 define ppc_fp128 @foo_ld(double %a, double %b) #0 {
 entry:
   %conv = fpext double %a to ppc_fp128
   %conv1 = fpext double %b to ppc_fp128
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %conv1) #0
   ret ppc_fp128 %call
 
-; CHECK-LABEL: @foo_ld
-; CHECK: bl copysignl
-; CHECK: blr
+; NOVSX-LABEL: @foo_ld
+; NOVSX: bl copysignl
+; NOVSX: blr
+; VSX-LABEL: @foo_ld
+; VSX: bl copysignl
+; VSX: blr
 }
 
 define ppc_fp128 @foo_lf(double %a, float %b) #0 {
 entry:
   %conv = fpext double %a to ppc_fp128
   %conv1 = fpext float %b to ppc_fp128
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %conv1) #0
   ret ppc_fp128 %call
 
-; CHECK-LABEL: @foo_lf
-; CHECK: bl copysignl
-; CHECK: blr
+; NOVSX-LABEL: @foo_lf
+; NOVSX: bl copysignl
+; NOVSX: blr
+; VSX-LABEL: @foo_lf
+; VSX: bl copysignl
+; VSX: blr
 }
 
 attributes #0 = { nounwind readnone }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fabs.ll

-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -mtriple=powerpc-apple-darwin | grep "xsabsdp f1, f1"
 
 define double @fabs(double %f) {
 entry:
   %tmp2 = tail call double @fabs( double %f ) readnone  ; <double> [#uses=1]
   ret double %tmp2
 }

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fast-isel-call.ll

-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
 
 define i32 @t1(i8 signext %a) nounwind {
   %1 = sext i8 %a to i32
   ret i32 %1
 }
 
 define i32 @t2(i8 zeroext %a) nounwind {
   %1 = zext i8 %a to i32

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
 
 define void @t1a(float %a) uwtable ssp {
 entry:
 ; ELF64: t1a
   %cmp = fcmp oeq float %a, 0.000000e+00
 ; ELF64: addis
 ; ELF64: lfs
 ; ELF64: fcmpu

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fast-isel-conversion.ll

-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
-; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 | FileCheck %s --check-prefix=PPC970
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
 
 ;; Tests for 970 don't use -fast-isel-abort because we intentionally punt
 ;; to SelectionDAG in some cases.
 
 ; Test sitofp
 
 define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp {
 entry:

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fast-isel-load-store.ll

-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort -mattr=-vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel -mattr=+vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64VSX
 
 ; This test verifies that load/store instructions are properly generated,
 ; and that they pass MI verification.
 
 @a = global i8 1, align 1
 @b = global i16 2, align 2
 @c = global i32 4, align 4
 @d = global i64 8, align 8
 @e = global float 1.25, align 4
 @f = global double 3.5, align 8
 
 %struct.s = type<{ i8, i32 }>
 %struct.t = type<{ i8, i64 }>
 
 @g = global %struct.s <{ i8 1, i32 2 }>, align 1
 @h = global %struct.t <{ i8 1, i64 2 }>, align 1
 
 @i = common global [8192 x i64] zeroinitializer, align 8
 
 ; load
 
 define i8 @t1() nounwind uwtable ssp {
 ; ELF64: t1
+; ELF64VSX: t1
   %1 = load i8* @a, align 1
 ; ELF64: lbz
+; ELF64VSX: lbz
   %2 = add nsw i8 %1, 1
 ; ELF64: addi
+; ELF64VSX: addi
   ret i8 %2
 }
 
 define i16 @t2() nounwind uwtable ssp {
 ; ELF64: t2
+; ELF64VSX: t2
   %1 = load i16* @b, align 2
 ; ELF64: lhz
+; ELF64VSX: lhz
   %2 = add nsw i16 %1, 1
 ; ELF64: addi
+; ELF64VSX: addi
   ret i16 %2
 }
 
 define i32 @t3() nounwind uwtable ssp {
 ; ELF64: t3
+; ELF64VSX: t3
   %1 = load i32* @c, align 4
 ; ELF64: lwz
+; ELF64VSX: lwz
   %2 = add nsw i32 %1, 1
 ; ELF64: addi
+; ELF64VSX: addi
   ret i32 %2
 }
 
 define i64 @t4() nounwind uwtable ssp {
 ; ELF64: t4
+; ELF64VSX: t4
   %1 = load i64* @d, align 4
 ; ELF64: ld
+; ELF64VSX: ld
   %2 = add nsw i64 %1, 1
 ; ELF64: addi
+; ELF64VSX: addi
   ret i64 %2
 }
 
 define float @t5() nounwind uwtable ssp {
 ; ELF64: t5
+; ELF64VSX: t5
   %1 = load float* @e, align 4
 ; ELF64: lfs
+; ELF64VSX: lfs
   %2 = fadd float %1, 1.0
 ; ELF64: fadds
+; ELF64VSX: fadds
   ret float %2
 }
 
 define double @t6() nounwind uwtable ssp {
 ; ELF64: t6
+; ELF64VSX: t6
   %1 = load double* @f, align 8
 ; ELF64: lfd
+; ELF64VSX: lxsdx
   %2 = fadd double %1, 1.0
 ; ELF64: fadd
+; ELF64VSX: xsadddp
   ret double %2
 }
 
 ; store
 
 define void @t7(i8 %v) nounwind uwtable ssp {
 ; ELF64: t7
+; ELF64VSX: t7
   %1 = add nsw i8 %v, 1
   store i8 %1, i8* @a, align 1
 ; ELF64: addis
 ; ELF64: addi
 ; ELF64: addi
 ; ELF64: stb
+; ELF64VSX: addis
+; ELF64VSX: addi
+; ELF64VSX: addi
+; ELF64VSX: stb
   ret void
 }
 
 define void @t8(i16 %v) nounwind uwtable ssp {
 ; ELF64: t8
+; ELF64VSX: t8
   %1 = add nsw i16 %v, 1
   store i16 %1, i16* @b, align 2
 ; ELF64: addis
 ; ELF64: addi
 ; ELF64: addi
 ; ELF64: sth
+; ELF64VSX: addis
+; ELF64VSX: addi
+; ELF64VSX: addi
+; ELF64VSX: sth
   ret void
 }
 
 define void @t9(i32 %v) nounwind uwtable ssp {
 ; ELF64: t9
+; ELF64VSX: t9
   %1 = add nsw i32 %v, 1
   store i32 %1, i32* @c, align 4
 ; ELF64: addis
 ; ELF64: addi
 ; ELF64: addi
 ; ELF64: stw
+; ELF64VSX: addis
+; ELF64VSX: addi
+; ELF64VSX: addi
+; ELF64VSX: stw
   ret void
 }
 
 define void @t10(i64 %v) nounwind uwtable ssp {
 ; ELF64: t10
+; ELF64VSX: t10
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* @d, align 4
 ; ELF64: addis
 ; ELF64: addi
 ; ELF64: addi
 ; ELF64: std
+; ELF64VSX: addis
+; ELF64VSX: addi
+; ELF64VSX: addi
+; ELF64VSX: std
   ret void
 }
 
 define void @t11(float %v) nounwind uwtable ssp {
 ; ELF64: t11
+; ELF64VSX: t11
   %1 = fadd float %v, 1.0
   store float %1, float* @e, align 4
 ; ELF64: fadds
 ; ELF64: stfs
+; ELF64VSX: fadds
+; ELF64VSX: stfs
   ret void
 }
 
 define void @t12(double %v) nounwind uwtable ssp {
 ; ELF64: t12
+; ELF64VSX: t12
   %1 = fadd double %v, 1.0
   store double %1, double* @f, align 8
 ; ELF64: fadd
 ; ELF64: stfd
+; ELF64VSX: xsadddp
+; ELF64VSX: stxsdx
   ret void
 }
 
 ;; lwa requires an offset divisible by 4, so we need lwax here.
 define i64 @t13() nounwind uwtable ssp {
 ; ELF64: t13
+; ELF64VSX: t13
   %1 = load i32* getelementptr inbounds (%struct.s* @g, i32 0, i32 1), align 1
   %2 = sext i32 %1 to i64
 ; ELF64: li
 ; ELF64: lwax
+; ELF64VSX: li
+; ELF64VSX: lwax
   %3 = add nsw i64 %2, 1
 ; ELF64: addi
+; ELF64VSX: addi
   ret i64 %3
 }
 
 ;; ld requires an offset divisible by 4, so we need ldx here.
 define i64 @t14() nounwind uwtable ssp {
 ; ELF64: t14
+; ELF64VSX: t14
   %1 = load i64* getelementptr inbounds (%struct.t* @h, i32 0, i32 1), align 1
 ; ELF64: li
 ; ELF64: ldx
+; ELF64VSX: li
+; ELF64VSX: ldx
   %2 = add nsw i64 %1, 1
 ; ELF64: addi
+; ELF64VSX: addi
   ret i64 %2
 }
 
 ;; std requires an offset divisible by 4, so we need stdx here.
 define void @t15(i64 %v) nounwind uwtable ssp {
 ; ELF64: t15
+; ELF64VSX: t15
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* getelementptr inbounds (%struct.t* @h, i32 0, i32 1), align 1
 ; ELF64: addis
 ; ELF64: addi
 ; ELF64: addi
 ; ELF64: li
 ; ELF64: stdx
+; ELF64VSX: addis
+; ELF64VSX: addi
+; ELF64VSX: addi
+; ELF64VSX: li
+; ELF64VSX: stdx
   ret void
 }
 
 ;; ld requires an offset that fits in 16 bits, so we need ldx here.
 define i64 @t16() nounwind uwtable ssp {
 ; ELF64: t16
+; ELF64VSX: t16
   %1 = load i64* getelementptr inbounds ([8192 x i64]* @i, i32 0, i64 5000), align 8
 ; ELF64: lis
 ; ELF64: ori
 ; ELF64: ldx
+; ELF64VSX: lis
+; ELF64VSX: ori
+; ELF64VSX: ldx
   %2 = add nsw i64 %1, 1
 ; ELF64: addi
+; ELF64VSX: addi
   ret i64 %2
 }
 
 ;; std requires an offset that fits in 16 bits, so we need stdx here.
 define void @t17(i64 %v) nounwind uwtable ssp {
 ; ELF64: t17
+; ELF64VSX: t17
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* getelementptr inbounds ([8192 x i64]* @i, i32 0, i64 5000), align 8
 ; ELF64: addis
 ; ELF64: ld
 ; ELF64: addi
 ; ELF64: lis
 ; ELF64: ori
 ; ELF64: stdx
+; ELF64VSX: addis
+; ELF64VSX: ld
+; ELF64VSX: addi
+; ELF64VSX: lis
+; ELF64VSX: ori
+; ELF64VSX: stdx
   ret void
 }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fast-isel-ret.ll

-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
 
 define zeroext i1 @rettrue() nounwind uwtable ssp {
 entry:
 ; ELF64-LABEL: rettrue
 ; ELF64: li 3, 1
 ; ELF64: blr
   ret i1 true
 }

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fcpsgn.ll

-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck -check-prefix=NOVSX %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @foo_dd(double %a, double %b) #0 {
 entry:
   %call = tail call double @copysign(double %a, double %b) #0
   ret double %call
 
-; CHECK-LABEL: @foo_dd
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_dd
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_dd
+; VSX: xscpsgndp 1, 2, 1
+; VSX: blr
 }
 
 declare double @copysign(double, double) #0
 
 define float @foo_ss(float %a, float %b) #0 {
 entry:
   %call = tail call float @copysignf(float %a, float %b) #0
   ret float %call
 
-; CHECK-LABEL: @foo_ss
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_ss
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_ss
+; VSX: fcpsgn 1, 2, 1
+; VSX: blr
 }
 
 declare float @copysignf(float, float) #0
 
 define float @foo_sd(float %a, double %b) #0 {
 entry:
   %conv = fptrunc double %b to float
   %call = tail call float @copysignf(float %a, float %conv) #0
   ret float %call
 
-; CHECK-LABEL: @foo_sd
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_sd
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_sd
+; VSX: fcpsgn 1, 2, 1
+; VSX: blr
 }
 
 define double @foo_ds(double %a, float %b) #0 {
 entry:
   %conv = fpext float %b to double
   %call = tail call double @copysign(double %a, double %conv) #0
   ret double %call
 
-; CHECK-LABEL: @foo_ds
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_ds
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_ds
+; VSX: fcpsgn 1, 2, 1
+; VSX: blr
 }
 
 attributes #0 = { nounwind readnone }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fma.ll

-; RUN: llc < %s -march=ppc32 -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -fp-contract=fast | FileCheck %s
 
 declare double @dummy1(double) #0
 declare double @dummy2(double, double) #0
 declare double @dummy3(double, double, double) #0
 
 define double @test_FMADD1(double %A, double %B, double %C) {
   %D = fmul double %A, %B   ; <double> [#uses=1]
   %E = fadd double %C, %D   ; <double> [#uses=1]

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fnabs.ll

-; RUN: llc < %s -march=ppc32 | grep fnabs
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fnabs
 
 declare double @fabs(double)
 
 define double @test(double %X) {
         %Y = call double @fabs( double %X ) readnone     ; <double> [#uses=1]
         %Z = fsub double -0.000000e+00, %Y               ; <double> [#uses=1]
         ret double %Z
 }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fp-branch.ll

-; RUN: llc < %s -march=ppc32 | grep fcmp | count 1
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fcmp | count 1
 
 declare i1 @llvm.isunordered.f64(double, double)
 
 define i1 @intcoord_cond_next55(double %tmp48.reload) {
 newFuncRoot:
         br label %cond_next55
 
 bb72.exitStub:          ; preds = %cond_next55

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fp_to_uint.ll

-; RUN: llc < %s -march=ppc32 | grep fctiwz | count 1
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fctiwz | count 1
 
 define i16 @foo(float %a) {
 entry:
         %tmp.1 = fptoui float %a to i16         ; <i16> [#uses=1]
         ret i16 %tmp.1
 }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fsel.ll

-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=CHECK-FM %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @zerocmp1(double %a, double %y, double %z) #0 {
 entry:
   %cmp = fcmp ult double %a, 0.000000e+00
   %z.y = select i1 %cmp, double %z, double %y
   ret double %z.y
 
 ; CHECK: @zerocmp1
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @zerocmp1
 ; CHECK-FM: fsel 1, 1, 2, 3
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp1
+; CHECK-FM-VSX: fsel 1, 1, 2, 3
+; CHECK-FM-VSX: blr
 }
 
 define double @zerocmp2(double %a, double %y, double %z) #0 {
 entry:
   %cmp = fcmp ogt double %a, 0.000000e+00
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 
 ; CHECK: @zerocmp2
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @zerocmp2
 ; CHECK-FM: fneg [[REG:[0-9]+]], 1
 ; CHECK-FM: fsel 1, [[REG]], 3, 2
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp2
+; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 1
+; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2
+; CHECK-FM-VSX: blr
 }
 
 define double @zerocmp3(double %a, double %y, double %z) #0 {
 entry:
   %cmp = fcmp oeq double %a, 0.000000e+00
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 
 ; CHECK: @zerocmp3
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @zerocmp3
 ; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 3
 ; CHECK-FM: fneg [[REG2:[0-9]+]], 1
 ; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp3
+; CHECK-FM-VSX: xsnegdp [[REG2:[0-9]+]], 1
+; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
+; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 3
+; CHECK-FM-VSX: blr
 }
 
 define double @min1(double %a, double %b) #0 {
 entry:
   %cmp = fcmp ole double %a, %b
   %cond = select i1 %cmp, double %a, double %b
   ret double %cond
 
 ; CHECK: @min1
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @min1
 ; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
 ; CHECK-FM: fsel 1, [[REG]], 1, 2
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @min1
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
+; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-FM-VSX: blr
 }
 
 define double @max1(double %a, double %b) #0 {
 entry:
   %cmp = fcmp oge double %a, %b
   %cond = select i1 %cmp, double %a, double %b
   ret double %cond
 
 ; CHECK: @max1
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @max1
 ; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
 ; CHECK-FM: fsel 1, [[REG]], 1, 2
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @max1
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-FM-VSX: blr
 }
 
 define double @cmp1(double %a, double %b, double %y, double %z) #0 {
 entry:
   %cmp = fcmp ult double %a, %b
   %z.y = select i1 %cmp, double %z, double %y
   ret double %z.y
 
 ; CHECK: @cmp1
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @cmp1
 ; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
 ; CHECK-FM: fsel 1, [[REG]], 3, 4
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @cmp1
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-FM-VSX: fsel 1, [[REG]], 3, 4
+; CHECK-FM-VSX: blr
 }
 
 define double @cmp2(double %a, double %b, double %y, double %z) #0 {
 entry:
   %cmp = fcmp ogt double %a, %b
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 
 ; CHECK: @cmp2
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @cmp2
 ; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
 ; CHECK-FM: fsel 1, [[REG]], 4, 3
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @cmp2
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
+; CHECK-FM-VSX: fsel 1, [[REG]], 4, 3
+; CHECK-FM-VSX: blr
 }
 
 define double @cmp3(double %a, double %b, double %y, double %z) #0 {
 entry:
   %cmp = fcmp oeq double %a, %b
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 
 ; CHECK: @cmp3
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @cmp3
 ; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
 ; CHECK-FM: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
 ; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]]
 ; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @cmp3
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-FM-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]
+; CHECK-FM-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
+; CHECK-FM-VSX: fsel 1, [[REG3]], [[REG2]], 4
+; CHECK-FM-VSX: blr
 }
 
 attributes #0 = { nounwind readnone }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/fsqrt.ll

 ; fsqrt should be generated when the fsqrt feature is enabled, but not 
 ; otherwise.
 
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
 ; RUN:   grep "fsqrt f1, f1"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
 ; RUN:   grep "fsqrt f1, f1"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
 ; RUN:   not grep "fsqrt f1, f1"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
 ; RUN:   not grep "fsqrt f1, f1"
 
 declare double @llvm.sqrt.f64(double)
 
 define double @X(double %Y) {
         %Z = call double @llvm.sqrt.f64( double %Y )            ; <double> [#uses=1]
         ret double %Z
 }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/i64_fp.ll

 ; fcfid and fctid should be generated when the 64bit feature is enabled, but not
 ; otherwise.
 
-; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+64bit | \
 ; RUN:   grep fcfid
-; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+64bit | \
 ; RUN:   grep fctidz
-; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g5 | \
 ; RUN:   grep fcfid
-; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g5 | \
 ; RUN:   grep fctidz
-; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=-64bit | \
 ; RUN:   not grep fcfid
-; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=-64bit | \
 ; RUN:   not grep fctidz
-; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g4 | \
 ; RUN:   not grep fcfid
-; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g4 | \
 ; RUN:   not grep fctidz
 
 define double @X(double %Y) {
         %A = fptosi double %Y to i64            ; <i64> [#uses=1]
         %B = sitofp i64 %A to double            ; <double> [#uses=1]
         ret double %B
 }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/mcm-12.ll

-; RUN: llc -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O1 -code-model=medium -mattr=-vsx < %s | FileCheck -check-prefix=NOVSX %s
+; RUN: llc -mcpu=pwr7 -O1 -code-model=medium -mattr=+vsx < %s | FileCheck -check-prefix=VSX %s
 
 ; Test peephole optimization for medium code model (32-bit TOC offsets)
 ; for loading a value from the constant pool (TOC-relative).
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
-; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
-; CHECK: .quad 4562098671269285104
-; CHECK-LABEL: test_double_const:
-; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
-; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
+; NOVSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; NOVSX: .quad 4562098671269285104
+; NOVSX-LABEL: test_double_const:
+; NOVSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
+; NOVSX: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
+
+; VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; VSX: .quad 4562098671269285104
+; VSX-LABEL: test_double_const:
+; VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
+; VSX: addi [[REG1]], {{[0-9]+}}, [[VAR]]@toc@l
+; VSX: lxsdx {{[0-9]+}}, 0, [[REG1]]

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/mcm-4.ll

-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false <%s | FileCheck -check-prefix=MEDIUM %s
-; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false <%s | FileCheck -check-prefix=LARGE %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s
 
 ; Test correct code generation for medium and large code model
 ; for loading a value from the constant pool (TOC-relative).
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
 ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
 ; MEDIUM: .quad 4562098671269285104
 ; MEDIUM-LABEL: test_double_const:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
 
+; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; MEDIUM-VSX: .quad 4562098671269285104
+; MEDIUM-VSX-LABEL: test_double_const:
+; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
+; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
+; MEDIUM-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
+
 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE: .quad 4562098671269285104
 ; LARGE-LABEL: test_double_const:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
+
+; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; LARGE-VSX: .quad 4562098671269285104
+; LARGE-VSX-LABEL: test_double_const:
+; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
+; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
+; LARGE-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/ppc64-align-long-double.ll

-; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=VSX %s
 
 ; Verify internal alignment of long double in a struct.  The double
 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
 ; the long double.  Check that these are stored to proper locations
 ; in the parameter save area and loaded from there for return in FPR1/2.
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"

 
 ; CHECK: std 6, 72(1)
 ; CHECK: std 5, 64(1)
 ; CHECK: std 4, 56(1)
 ; CHECK: std 3, 48(1)
 ; CHECK: lfd 1, 64(1)
 ; CHECK: lfd 2, 72(1)
 
+; VSX: std 6, 72(1)
+; VSX: std 5, 64(1)
+; VSX: std 4, 56(1)
+; VSX: std 3, 48(1)
+; VSX: li 3, 16
+; VSX: addi 4, 1, 48
+; VSX: lxsdx 1, 4, 3
+; VSX: li 3, 24
+; VSX: lxsdx 2, 4, 3

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/recipest.ll

-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck -check-prefix=CHECK-SAFE %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck -check-prefix=CHECK-SAFE %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-SAFE-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 declare double @llvm.sqrt.f64(double)
 declare float @llvm.sqrt.f32(float)
 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
 
 define double @foo(double %a, double %b) nounwind {
   %x = call double @llvm.sqrt.f64(double %b)
   %r = fdiv double %a, %x
   ret double %r
 
 ; CHECK: @foo
 ; CHECK-DAG: frsqrte
 ; CHECK-DAG: fnmsub
 ; CHECK: fmul
 ; CHECK: fmadd
 ; CHECK: fmul
 ; CHECK: fmul
 ; CHECK: fmadd
 ; CHECK: fmul
 ; CHECK: fmul
 ; CHECK: blr
 
+; CHECK-VSX: @foo
+; CHECK-DAG-VSX: xsrsqrtedp
+; CHECK-DAG-VSX: xsnmsubadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @foo
 ; CHECK-SAFE: fsqrt
 ; CHECK-SAFE: fdiv
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @foo
+; CHECK-SAFE-VSX: xssqrtdp
+; CHECK-SAFE-VSX: xsdivdp
+; CHECK-SAFE-VSX: blr
 }
 
 define double @foof(double %a, float %b) nounwind {
   %x = call float @llvm.sqrt.f32(float %b)
   %y = fpext float %x to double
   %r = fdiv double %a, %y
   ret double %r
 
 ; CHECK: @foof
 ; CHECK-DAG: frsqrtes
 ; CHECK-DAG: fnmsubs
 ; CHECK: fmuls
 ; CHECK-NEXT: fmadds
 ; CHECK-NEXT: fmuls
 ; CHECK-NEXT: fmul
 ; CHECK-NEXT: blr
 
+; CHECK-VSX: @foof
+; CHECK-DAG-VSX: frsqrtes
+; CHECK-DAG-VSX: fnmsubs
+; CHECK-VSX: fmuls
+; CHECK-VSX: fmadds
+; CHECK-VSX: fmuls
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @foof
 ; CHECK-SAFE: fsqrts
 ; CHECK-SAFE: fdiv
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @foof
+; CHECK-SAFE-VSX: fsqrts
+; CHECK-SAFE-VSX: xsdivdp
+; CHECK-SAFE-VSX: blr
 }
 
 define float @food(float %a, double %b) nounwind {
   %x = call double @llvm.sqrt.f64(double %b)
   %y = fptrunc double %x to float
   %r = fdiv float %a, %y
   ret float %r
 
-; CHECK: @foo
+; CHECK: @food
 ; CHECK-DAG: frsqrte
 ; CHECK-DAG: fnmsub
 ; CHECK: fmul
 ; CHECK-NEXT: fmadd
 ; CHECK-NEXT: fmul
 ; CHECK-NEXT: fmul
 ; CHECK-NEXT: fmadd
 ; CHECK-NEXT: fmul
 ; CHECK-NEXT: frsp
 ; CHECK-NEXT: fmuls
 ; CHECK-NEXT: blr
 
-; CHECK-SAFE: @foo
+; CHECK-VSX: @food
+; CHECK-DAG-VSX: xsrsqrtedp
+; CHECK-DAG-VSX: xsnmsubadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: frsp
+; CHECK-VSX: fmuls
+; CHECK-VSX: blr
+
+; CHECK-SAFE: @food
 ; CHECK-SAFE: fsqrt
 ; CHECK-SAFE: fdivs
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @food
+; CHECK-SAFE-VSX: xssqrtdp
+; CHECK-SAFE-VSX: fdivs
+; CHECK-SAFE-VSX: blr
 }
 
 define float @goo(float %a, float %b) nounwind {
   %x = call float @llvm.sqrt.f32(float %b)
   %r = fdiv float %a, %x
   ret float %r
 
 ; CHECK: @goo
 ; CHECK-DAG: frsqrtes
 ; CHECK-DAG: fnmsubs
 ; CHECK: fmuls
 ; CHECK: fmadds
 ; CHECK: fmuls
 ; CHECK: fmuls
 ; CHECK: blr
 
+; CHECK-VSX: @goo
+; CHECK-DAG-VSX: frsqrtes
+; CHECK-DAG-VSX: fnmsubs
+; CHECK-VSX: fmuls
+; CHECK-VSX: fmadds
+; CHECK-VSX: fmuls
+; CHECK-VSX: fmuls
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @goo
 ; CHECK-SAFE: fsqrts
 ; CHECK-SAFE: fdivs
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @goo
+; CHECK-SAFE-VSX: fsqrts
+; CHECK-SAFE-VSX: fdivs
+; CHECK-SAFE-VSX: blr
 }
 
 define <4 x float> @hoo(<4 x float> %a, <4 x float> %b) nounwind {
   %x = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
   %r = fdiv <4 x float> %a, %x
   ret <4 x float> %r
 
 ; CHECK: @hoo
 ; CHECK: vrsqrtefp
 
+; CHECK-VSX: @hoo
+; CHECK-VSX: xvrsqrtesp
+
 ; CHECK-SAFE: @hoo
 ; CHECK-SAFE-NOT: vrsqrtefp
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @hoo
+; CHECK-SAFE-VSX: xvsqrtsp
+; CHECK-SAFE-VSX: xvdivsp
+; CHECK-SAFE-VSX: blr
 }
 
 define double @foo2(double %a, double %b) nounwind {
   %r = fdiv double %a, %b
   ret double %r
 
 ; CHECK: @foo2
 ; CHECK-DAG: fre
 ; CHECK-DAG: fnmsub
 ; CHECK: fmadd
 ; CHECK: fnmsub
 ; CHECK: fmadd
 ; CHECK: fmul
 ; CHECK: blr
 
+; CHECK-VSX: @foo2
+; CHECK-DAG-VSX: xsredp
+; CHECK-DAG-VSX: xsnmsubadp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsnmsubadp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @foo2
 ; CHECK-SAFE: fdiv
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @foo2
+; CHECK-SAFE-VSX: xsdivdp
+; CHECK-SAFE-VSX: blr
 }
 
 define float @goo2(float %a, float %b) nounwind {
   %r = fdiv float %a, %b
   ret float %r
 
 ; CHECK: @goo2
 ; CHECK-DAG: fres
 ; CHECK-DAG: fnmsubs
 ; CHECK: fmadds
 ; CHECK: fmuls
 ; CHECK: blr
 
+; CHECK-VSX: @goo2
+; CHECK-DAG-VSX: fres
+; CHECK-DAG-VSX: fnmsubs
+; CHECK-VSX: fmadds
+; CHECK-VSX: fmuls
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @goo2
 ; CHECK-SAFE: fdivs
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @goo2
+; CHECK-SAFE-VSX: fdivs
+; CHECK-SAFE-VSX: blr
 }
 
 define <4 x float> @hoo2(<4 x float> %a, <4 x float> %b) nounwind {
   %r = fdiv <4 x float> %a, %b
   ret <4 x float> %r
 
 ; CHECK: @hoo2
 ; CHECK: vrefp
 
+; CHECK-VSX: @hoo2
+; CHECK-VSX: xvresp
+
 ; CHECK-SAFE: @hoo2
 ; CHECK-SAFE-NOT: vrefp
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @hoo2
+; CHECK-SAFEVSX: xvdivsp
+; CHECK-SAFE-VSX: blr
 }
 
 define double @foo3(double %a) nounwind {
   %r = call double @llvm.sqrt.f64(double %a)
   ret double %r
   
 ; CHECK: @foo3
 ; CHECK: fcmpu
 ; CHECK-DAG: frsqrte
 ; CHECK-DAG: fnmsub
 ; CHECK: fmul
 ; CHECK: fmadd
 ; CHECK: fmul
 ; CHECK: fmul
 ; CHECK: fmadd
 ; CHECK: fmul
 ; CHECK: fre
 ; CHECK: fnmsub
 ; CHECK: fmadd
 ; CHECK: fnmsub
 ; CHECK: fmadd
 ; CHECK: blr
 
+; CHECK-VSX: @foo3
+; CHECK-VSX: xscmpudp
+; CHECK-DAG-VSX: xsrsqrtedp
+; CHECK-DAG-VSX: xsnmsubadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: fmr
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsredp
+; CHECK-VSX: xsnmsubadp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsnmsubadp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @foo3
 ; CHECK-SAFE: fsqrt
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @foo3
+; CHECK-SAFE-VSX: xssqrtdp
+; CHECK-SAFE-VSX: blr
 }
 
 define float @goo3(float %a) nounwind {
   %r = call float @llvm.sqrt.f32(float %a)
   ret float %r
 
 ; CHECK: @goo3
 ; CHECK: fcmpu
 ; CHECK-DAG: frsqrtes
 ; CHECK-DAG: fnmsubs
 ; CHECK: fmuls
 ; CHECK: fmadds
 ; CHECK: fmuls
 ; CHECK: fres
 ; CHECK: fnmsubs
 ; CHECK: fmadds
 ; CHECK: blr
 
+; CHECK-VSX: @goo3
+; CHECK-VSX: fcmpu
+; CHECK-DAG-VSX: frsqrtes
+; CHECK-DAG-VSX: fnmsubs
+; CHECK-VSX: fmuls
+; CHECK-VSX: fmadds
+; CHECK-VSX: fmuls
+; CHECK-VSX: fres
+; CHECK-VSX: fnmsubs
+; CHECK-VSX: fmadds
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @goo3
 ; CHECK-SAFE: fsqrts
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @goo3
+; CHECK-SAFE-VSX: fsqrts
+; CHECK-SAFE-VSX: blr
 }
 
 define <4 x float> @hoo3(<4 x float> %a) nounwind {
   %r = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 
 ; CHECK: @hoo3
 ; CHECK: vrsqrtefp
 ; CHECK-DAG: vrefp
 ; CHECK-DAG: vcmpeqfp
 
+; CHECK-VSX: @hoo3
+; CHECK-VSX: xvrsqrtesp
+; CHECK-DAG-VSX: xvresp
+; CHECK-DAG-VSX: xvcmpeqsp
+
 ; CHECK-SAFE: @hoo3
 ; CHECK-SAFE-NOT: vrsqrtefp
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @hoo3
+; CHECK-SAFE-VSX: xvsqrtsp
+; CHECK-SAFE-VSX: blr
 }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/rounding-ops.ll

-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck -check-prefix=NOVSX %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define float @test1(float %x) nounwind  {
   %call = tail call float @floorf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-LABEL: test1:
-; CHECK: frim 1, 1
+; NOVSX-LABEL: test1:
+; NOVSX: frim 1, 1
+; VSX-LABEL: test1:
+; VSX: frim 1, 1
 }
 
 declare float @floorf(float) nounwind readnone
 
 define double @test2(double %x) nounwind  {
   %call = tail call double @floor(double %x) nounwind readnone
   ret double %call
 
-; CHECK-LABEL: test2:
-; CHECK: frim 1, 1
+; NOVSX-LABEL: test2:
+; NOVSX: frim 1, 1
+; VSX-LABEL: test2:
+; VSX: xsrdpim 1, 1
 }
 
 declare double @floor(double) nounwind readnone
 
 define float @test3(float %x) nounwind  {
   %call = tail call float @roundf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-LABEL: test3:
-; CHECK: frin 1, 1
+; NOVSX-LABEL: test3:
+; NOVSX: frin 1, 1
+; VSX-LABEL: test3:
+; VSX: frin 1, 1
 }
 
 declare float @roundf(float) nounwind readnone
 
 define double @test4(double %x) nounwind  {
   %call = tail call double @round(double %x) nounwind readnone
   ret double %call
 
-; CHECK-LABEL: test4:
-; CHECK: frin 1, 1
+; NOVSX-LABEL: test4:
+; NOVSX: frin 1, 1
+; VSX-LABEL: test4:
+; VSX: xsrdpi 1, 1
 }
 
 declare double @round(double) nounwind readnone
 
 define float @test5(float %x) nounwind  {
   %call = tail call float @ceilf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-LABEL: test5:
-; CHECK: frip 1, 1
+; NOVSX-LABEL: test5:
+; NOVSX: frip 1, 1
+; VSX-LABEL: test5:
+; VSX: frip 1, 1
 }
 
 declare float @ceilf(float) nounwind readnone
 
 define double @test6(double %x) nounwind  {
   %call = tail call double @ceil(double %x) nounwind readnone
   ret double %call
 
-; CHECK-LABEL: test6:
-; CHECK: frip 1, 1
+; NOVSX-LABEL: test6:
+; NOVSX: frip 1, 1
+; VSX-LABEL: test6:
+; VSX: xsrdpip 1, 1
 }
 
 declare double @ceil(double) nounwind readnone
 
 define float @test9(float %x) nounwind  {
   %call = tail call float @truncf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-LABEL: test9:
-; CHECK: friz 1, 1
+; NOVSX-LABEL: test9:
+; NOVSX: friz 1, 1
+; VSX-LABEL: test9:
+; VSX: friz 1, 1
 }
 
 declare float @truncf(float) nounwind readnone
 
 define double @test10(double %x) nounwind  {
   %call = tail call double @trunc(double %x) nounwind readnone
   ret double %call
 
-; CHECK-LABEL: test10:
-; CHECK: friz 1, 1
+; NOVSX-LABEL: test10:
+; NOVSX: friz 1, 1
+; VSX-LABEL: test10:
+; VSX: xsrdpiz 1, 1
 }
 
 declare double @trunc(double) nounwind readnone
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/select-cc.ll

-; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -mattr=-vsx -march=ppc32
 ; PR3011
 
 define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind  {
   %x.lo = extractelement <2 x double> %x, i32 0    ; <double> [#uses=1]
   %x.lo.ge = fcmp oge double %x.lo, 0.000000e+00    ; <i1> [#uses=1]
   %a.d = select i1 %x.lo.ge, <2 x double> %y, <2 x double> %x    ; <<2 x double>> [#uses=1]
   ret <2 x double> %a.d
 }

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/unaligned.ll

-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=VSX %s
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
 
 define void @foo1(i16* %p, i16* %r) nounwind {
 entry:
   %v = load i16* %p, align 1
   store i16 %v, i16* %r, align 1
   ret void
 
 ; CHECK: @foo1
 ; CHECK: lhz
 ; CHECK: sth
+
+; VSX: @foo1
+; VSX: lhz
+; VSX: sth
 }
 
 define void @foo2(i32* %p, i32* %r) nounwind {
 entry:
   %v = load i32* %p, align 1
   store i32 %v, i32* %r, align 1
   ret void
 
 ; CHECK: @foo2
 ; CHECK: lwz
 ; CHECK: stw
+
+; VSX: @foo2
+; VSX: lwz
+; VSX: stw
 }
 
 define void @foo3(i64* %p, i64* %r) nounwind {
 entry:
   %v = load i64* %p, align 1
   store i64 %v, i64* %r, align 1
   ret void
 
 ; CHECK: @foo3
 ; CHECK: ld
 ; CHECK: std
+
+; VSX: @foo3
+; VSX: ld
+; VSX: std
 }
 
 define void @foo4(float* %p, float* %r) nounwind {
 entry:
   %v = load float* %p, align 1
   store float %v, float* %r, align 1
   ret void
 
 ; CHECK: @foo4
 ; CHECK: lfs
 ; CHECK: stfs
+
+; VSX: @foo4
+; VSX: lfs
+; VSX: stfs
 }
 
 define void @foo5(double* %p, double* %r) nounwind {
 entry:
   %v = load double* %p, align 1
   store double %v, double* %r, align 1
   ret void
 
 ; CHECK: @foo5
 ; CHECK: lfd
 ; CHECK: stfd
+
+; VSX: @foo5
+; VSX: lxsdx
+; VSX: stxsdx
 }
 
 define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind {
 entry:
   %v = load <4 x float>* %p, align 1
   store <4 x float> %v, <4 x float>* %r, align 1
   ret void
 
 ; These loads and stores are legalized into aligned loads and stores
 ; using aligned stack slots.
 ; CHECK: @foo6
 ; CHECK-DAG: ld
 ; CHECK-DAG: ld
 ; CHECK-DAG: stdx
 ; CHECK: stdx
+
+; VSX: @foo6
+; VSX-DAG: ld
+; VSX-DAG: ld
+; VSX-DAG: stdx
+; VSX: stdx
 }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/unsafe-math.ll

-; RUN: llc < %s -march=ppc32 | grep fmul | count 2
-; RUN: llc < %s -march=ppc32 -enable-unsafe-fp-math | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fmul | count 2
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -enable-unsafe-fp-math | \
 ; RUN:   grep fmul | count 1
 
 define double @foo(double %X) nounwind {
         %tmp1 = fmul double %X, 1.23
         %tmp2 = fmul double %tmp1, 4.124
         ret double %tmp2
 }
 

/home/seurer/llvm/llvm-test/test/CodeGen/PowerPC/vec_mul.ll

-; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s -check-prefix=CHECK-LE
+; RUN: llc < %s -mattr=-vsx -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s -check-prefix=CHECK-LE
 
 define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
   %tmp = load <4 x i32>* %X    ; <<4 x i32>> [#uses=1]
   %tmp2 = load <4 x i32>* %Y    ; <<4 x i32>> [#uses=1]
   %tmp3 = mul <4 x i32> %tmp, %tmp2    ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %tmp3
 }
 ; CHECK-LABEL: test_v4i32: