[ARM] Use the Cortex-A57 sched model for Cortex-A72

[samparker]

Summary

This mirrors what we already do for AArch64 and LNT scores are improved by a geomean of 1.57%.

[fhahn]

LGTM. AFAIK cortex-a57 and cortex-a72 are close enough for this to be beneficial. AArch64 re-uses the A57 model for A72 too.

[samparker]

Hey Florian,

It was brought to my attention that the scheduler still wasn't enabled because of the missing feature. I've now added this and the geomean improvement is 2.23%. I will shortly add a couple of tests too.

[samparker]

Added the a72 to a couple of scheduling tests, as well as the basic unroll one.

[fhahn]

In D53562#1273812, @samparker wrote:

Hey Florian,

It was brought to my attention that the scheduler still wasn't enabled because of the missing feature. I've now added this and the geomean improvement is 2.23%. I will shortly add a couple of tests too.

So yes, to enable the machine scheduler for a core on ARM, FeatureUseMISched is required. I think it is worth splitting using the Cortex-A57 model and enabling the machine scheduler for Cortex-A72. The A57 model should be more accurate for A72 than no model.

For changing to using the MachineScheduler, the last time I looked at it (about a year ago), I remember seeing some relatively big regressions on some benchmarks, so we might want to be a bit more cautious there, as there might be potential to tweak the scheduling heuristics for ARM. Also, I think it would be good to have numbers for a large set of benchmarks (test-suite + commercial ones)

[samparker]

Ok, fair enough, my LNT numbers show that the MISched results are more variable:

Regressions (%):

benchmark	Model	Model + MISched
Stanford/FloatMM		40.1
McGill/queens	29.6	29.4
Stanford/Puzzle	16.05	15.6
FreeBench/mason/mason		9.27
Olden/power/power		7.61
VersaBench/ecbdes/ecbdes		5.25
BenchmarkGame/fannkuch	6.55
Fhourstones/fhourstones	5.75

Improvements (%):

benchmark	Model	Model + MISched
Stanford/Perm	21.7	22.53
Olden/mst/mst	22.05	22.21
FreeBench/fourinarow/fourinarow	22.83	21.21
TSVC/CrossingThresholds-dbl/CrossingThresholds-dbl	14.17	19.52
TSVC/Searching-flt/Searching-flt	16.26	19.23
TSVC/Searching-dbl/Searching-dbl	16.28	19.15

I will remove the use of the feature for now.

cheers,

lib/Target/ARM/ARM.td

                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC,
                                                          FeatureFPAO,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureCheapPredicableCPSR]>;
 
-def : ProcNoItin<"cortex-a72",                          [ARMv8a, ProcA72,
+def : ProcessorModel<"cortex-a72", CortexA57Model,      [ARMv8a, ProcA72,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
+                                                         FeatureUseMISched,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 

test/CodeGen/ARM/cortex-a57-misched-alu.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED
+; RUN: llc < %s -mtriple=armv8-eabi -mcpu=cortex-a72 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 
 ; Check the latency for ALU shifted operand variants.
 ;
 ; CHECK:       ********** MI Scheduling **********
 ; CHECK:      foo:%bb.0 entry
 
 ; ALU, basic - 1 cyc I0/I1
 ; CHECK:      EORrr

test/CodeGen/ARM/cortex-a57-misched-basic.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=A57_SCHED
+; RUN: llc < %s -mtriple=armv8-eabi -mcpu=cortex-a72 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=A57_SCHED
 ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic    -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
 
 ; Check the latency for instructions for both generic and cortex-a57.
 ; SDIV should be scheduled at the block's begin (20 cyc of independent M unit).
 ;
 ; CHECK:       ********** MI Scheduling **********
 ; CHECK:      foo:%bb.0 entry
 

 ; A57_SCHED:  SUBrr
 ; A57_SCHED:  Latency    : 1
 
 ; CHECK:      ** Final schedule for %bb.0 ***
 ; GENERIC:    LDRi12
 ; GENERIC:    SDIV
 ; A57_SCHED:  SDIV
 ; A57_SCHED:  LDRi12
-; CHECK:      ********** INTERVALS **********
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "armv8r-arm-none-eabi"
 
 ; Function Attrs: norecurse nounwind readnone
 define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr #0 {
 entry:
   %xor = xor i32 %c, %b
   %ld = load i32, i32* %d
   %add = add nsw i32 %xor, %ld
   %div = sdiv i32 %a, %b
   %sub = sub i32 %div, %add
   ret i32 %sub
 }
 

test/Transforms/LoopUnroll/ARM/loop-unrolling.ll

 ; RUN: opt -mtriple=armv7 -mcpu=cortex-a57 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-A
 ; RUN: opt -mtriple=thumbv7 -mcpu=cortex-a57 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-A
+; RUN: opt -mtriple=thumbv7 -mcpu=cortex-a72 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-A
 ; RUN: opt -mtriple=thumbv8m -mcpu=cortex-m23 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-T1
 ; RUN: opt -mtriple=thumbv8m.main -mcpu=cortex-m33 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-T2
 ; RUN: opt -mtriple=thumbv7em -mcpu=cortex-m7 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-T2
 
 ; CHECK-LABEL: partial
 define arm_aapcs_vfpcc void @partial(i32* nocapture %C, i32* nocapture readonly %A, i32* nocapture readonly %B) local_unnamed_addr #0 {
 entry:
   br label %for.body