[X86][compiler-rt] Add additional CPUs and features to the cpu detection to match libgcc

[craig.topper]

Summary

This patch adds additional features and cpus from libgcc. Unfortunately we've overflowed the existing 32-bits of features so we had to add a new __cpu_features2 variable to hold the additional bits. This matches libgcc as far as I can tell.

[echristo]

LGTM.

-eric

[vitalybuka]

FYI http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-ubsan/builds/7970/steps/build%20stage1%20clang/logs/stdio

/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c: In function ‘getAvailableFeatures’:
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c:470:22: warning: left shift count is negative [-Wshift-count-negative]
       Features2 |= 1 << (F - 32);  \
                      ^
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c:474:5: note: in expansion of macro ‘setFeature’
     setFeature(FEATURE_CMOV);
     ^~~~~~~~~~
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c:470:22: warning: left shift count is negative [-Wshift-count-negative]
       Features2 |= 1 << (F - 32);  \
                      ^
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c:476:5: note: in expansion of macro ‘setFeature’
     setFeature(FEATURE_MMX);
     ^~~~~~~~~~
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c:470:22: warning: left shift count is negative [-Wshift-count-negative]
       Features2 |= 1 << (F - 32);  \
                      ^
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c:478:5: note: in expansion of macro ‘setFeature’
     setFeature(FEATURE_SSE);
     ^~~~~~~~~~
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c:470:22: warning: left shift count is negative [-Wshift-count-negative]
       Features2 |= 1 << (F - 32);  \
                      ^
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c:480:5: note: in expansion of macro ‘setFeature’
     setFeature(FEATURE_SSE2);
     ^~~~~~~~~~
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm/projects/compiler-rt/lib/builtins/cpu_model.c:470:22: warning: left shift count is negative [-Wshift-count-negative]
       Features2 |= 1 << (F - 32);  \
                      ^

...

[craig.topper]

@vitalybuka, the macro in the code specifically checks the value before doing the shift. Is there something wrong with my logic?

#define setFeature(F) \

do {                             \
  if (F < 32)                    \
    Features |= 1 << F;          \
  else if (F < 64)               \
    Features2 |= 1 << (F - 32);  \
} while (0)

[lebedev.ri]

compiler-rt/trunk/lib/builtins/cpu_model.c

467–468 ↗

(On Diff #170297)

F = 31
F < 32
1 << 31
2147483648
which is just the sign bit set

This should probably be

Features |= 1U << F;

lib/builtins/cpu_model.c

enum ProcessorTypes {
   AMDFAM10H,
   AMDFAM15H,
   INTEL_SILVERMONT,
   INTEL_KNL,
   AMD_BTVER1,
   AMD_BTVER2,
   AMDFAM17H,
   INTEL_KNM,
+  INTEL_GOLDMONT,
+  INTEL_GOLDMONT_PLUS,
+  INTEL_TREMONT,
   CPU_TYPE_MAX
 };
 
 enum ProcessorSubtypes {
   INTEL_COREI7_NEHALEM = 1,
   INTEL_COREI7_WESTMERE,
   INTEL_COREI7_SANDYBRIDGE,
   AMDFAM10H_BARCELONA,
   AMDFAM10H_SHANGHAI,
   AMDFAM10H_ISTANBUL,
   AMDFAM15H_BDVER1,
   AMDFAM15H_BDVER2,
   AMDFAM15H_BDVER3,
   AMDFAM15H_BDVER4,
   AMDFAM17H_ZNVER1,
   INTEL_COREI7_IVYBRIDGE,
   INTEL_COREI7_HASWELL,
   INTEL_COREI7_BROADWELL,
   INTEL_COREI7_SKYLAKE,
   INTEL_COREI7_SKYLAKE_AVX512,
   INTEL_COREI7_CANNONLAKE,
+  INTEL_COREI7_ICELAKE_CLIENT,
+  INTEL_COREI7_ICELAKE_SERVER,
   CPU_SUBTYPE_MAX
 };
 
 enum ProcessorFeatures {
   FEATURE_CMOV = 0,
   FEATURE_MMX,
   FEATURE_POPCNT,
   FEATURE_SSE,
enum ProcessorFeatures {
   FEATURE_AVX512DQ,
   FEATURE_AVX512CD,
   FEATURE_AVX512ER,
   FEATURE_AVX512PF,
   FEATURE_AVX512VBMI,
   FEATURE_AVX512IFMA,
   FEATURE_AVX5124VNNIW,
   FEATURE_AVX5124FMAPS,
-  FEATURE_AVX512VPOPCNTDQ
+  FEATURE_AVX512VPOPCNTDQ,
+  FEATURE_AVX512VBMI2,
+  FEATURE_GFNI,
+  FEATURE_VPCLMULQDQ,
+  FEATURE_AVX512VNNI,
+  FEATURE_AVX512BITALG
 };
 
 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
 // support. Consequently, for i386, the presence of CPUID is checked first
 // via the corresponding eflags bit.
 static bool isCpuIdSupported() {
 #if defined(__GNUC__) || defined(__clang__)
case 6:
     case 0x37:
     case 0x4a:
     case 0x4d:
     case 0x5a:
     case 0x5d:
     case 0x4c: // really airmont
       *Type = INTEL_SILVERMONT;
       break; // "silvermont"
+    // Goldmont:
+    case 0x5c: // Apollo Lake
+    case 0x5f: // Denverton
+      *Type = INTEL_GOLDMONT;
+      break; // "goldmont"
+    case 0x7a:
+      *Type = INTEL_GOLDMONT_PLUS;
+      break;
 
     case 0x57:
       *Type = INTEL_KNL; // knl
       break;
 
     case 0x85:
       *Type = INTEL_KNM; // knm
       break;
case 23:
     *Subtype = AMDFAM17H_ZNVER1;
     break;
   default:
     break; // "generic"
   }
 }
 
 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
-                                 unsigned *FeaturesOut) {
+                                 unsigned *FeaturesOut,
+                                 unsigned *Features2Out) {
   unsigned Features = 0;
+  unsigned Features2 = 0;
   unsigned EAX, EBX;
 
+#define setFeature(F)              \
+  do {                             \
+    if (F < 32)                    \
+      Features |= 1 << F;          \
+    else if (F < 64)               \
+      Features2 |= 1 << (F - 32);  \
+  } while (0)
+
   if ((EDX >> 15) & 1)
-    Features |= 1 << FEATURE_CMOV;
+    setFeature(FEATURE_CMOV);
   if ((EDX >> 23) & 1)
-    Features |= 1 << FEATURE_MMX;
+    setFeature(FEATURE_MMX);
   if ((EDX >> 25) & 1)
-    Features |= 1 << FEATURE_SSE;
+    setFeature(FEATURE_SSE);
   if ((EDX >> 26) & 1)
-    Features |= 1 << FEATURE_SSE2;
+    setFeature(FEATURE_SSE2);
 
   if ((ECX >> 0) & 1)
-    Features |= 1 << FEATURE_SSE3;
+    setFeature(FEATURE_SSE3);
   if ((ECX >> 1) & 1)
-    Features |= 1 << FEATURE_PCLMUL;
+    setFeature(FEATURE_PCLMUL);
   if ((ECX >> 9) & 1)
-    Features |= 1 << FEATURE_SSSE3;
+    setFeature(FEATURE_SSSE3);
   if ((ECX >> 12) & 1)
-    Features |= 1 << FEATURE_FMA;
+    setFeature(FEATURE_FMA);
   if ((ECX >> 19) & 1)
-    Features |= 1 << FEATURE_SSE4_1;
+    setFeature(FEATURE_SSE4_1);
   if ((ECX >> 20) & 1)
-    Features |= 1 << FEATURE_SSE4_2;
+    setFeature(FEATURE_SSE4_2);
   if ((ECX >> 23) & 1)
-    Features |= 1 << FEATURE_POPCNT;
+    setFeature(FEATURE_POPCNT);
   if ((ECX >> 25) & 1)
-    Features |= 1 << FEATURE_AES;
+    setFeature(FEATURE_AES);
 
   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
   // indicates that the AVX registers will be saved and restored on context
   // switch, then we have full AVX support.
   const unsigned AVXBits = (1 << 27) | (1 << 28);
   bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
                 ((EAX & 0x6) == 0x6);
   bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
 
   if (HasAVX)
-    Features |= 1 << FEATURE_AVX;
+    setFeature(FEATURE_AVX);
 
   bool HasLeaf7 =
       MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
 
   if (HasLeaf7 && ((EBX >> 3) & 1))
-    Features |= 1 << FEATURE_BMI;
+    setFeature(FEATURE_BMI);
   if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
-    Features |= 1 << FEATURE_AVX2;
+    setFeature(FEATURE_AVX2);
   if (HasLeaf7 && ((EBX >> 9) & 1))
-    Features |= 1 << FEATURE_BMI2;
+    setFeature(FEATURE_BMI2);
   if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512F;
+    setFeature(FEATURE_AVX512F);
   if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512DQ;
+    setFeature(FEATURE_AVX512DQ);
   if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512IFMA;
+    setFeature(FEATURE_AVX512IFMA);
   if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512PF;
+    setFeature(FEATURE_AVX512PF);
   if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512ER;
+    setFeature(FEATURE_AVX512ER);
   if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512CD;
+    setFeature(FEATURE_AVX512CD);
   if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512BW;
+    setFeature(FEATURE_AVX512BW);
   if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512VL;
+    setFeature(FEATURE_AVX512VL);
 
   if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512VBMI;
+    setFeature(FEATURE_AVX512VBMI);
+  if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
+    setFeature(FEATURE_AVX512VBMI2);
+  if (HasLeaf7 && ((ECX >> 8) & 1))
+    setFeature(FEATURE_GFNI);
+  if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
+    setFeature(FEATURE_VPCLMULQDQ);
+  if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
+    setFeature(FEATURE_AVX512VNNI);
+  if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
+    setFeature(FEATURE_AVX512BITALG);
   if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512VPOPCNTDQ;
+    setFeature(FEATURE_AVX512VPOPCNTDQ);
 
   if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX5124VNNIW;
+    setFeature(FEATURE_AVX5124VNNIW);
   if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX5124FMAPS;
+    setFeature(FEATURE_AVX5124FMAPS);
 
   unsigned MaxExtLevel;
   getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
 
   bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
                      !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
   if (HasExtLeaf1 && ((ECX >> 6) & 1))
-    Features |= 1 << FEATURE_SSE4_A;
+    setFeature(FEATURE_SSE4_A);
   if (HasExtLeaf1 && ((ECX >> 11) & 1))
-    Features |= 1 << FEATURE_XOP;
+    setFeature(FEATURE_XOP);
   if (HasExtLeaf1 && ((ECX >> 16) & 1))
-    Features |= 1 << FEATURE_FMA4;
+    setFeature(FEATURE_FMA4);
 
   *FeaturesOut = Features;
+  *Features2Out = Features2;
+#undef setFeature
 }
 
 #if defined(HAVE_INIT_PRIORITY)
 #define CONSTRUCTOR_ATTRIBUTE __attribute__((__constructor__ 101))
 #elif __has_attribute(__constructor__)
 #define CONSTRUCTOR_ATTRIBUTE __attribute__((__constructor__))
 #else
 // FIXME: For MSVC, we should make a function pointer global in .CRT$X?? so that
 // this runs during initialization.
 #define CONSTRUCTOR_ATTRIBUTE
 #endif
 
 int __cpu_indicator_init(void) CONSTRUCTOR_ATTRIBUTE;
 
 struct __processor_model {
   unsigned int __cpu_vendor;
   unsigned int __cpu_type;
   unsigned int __cpu_subtype;
   unsigned int __cpu_features[1];
 } __cpu_model = {0, 0, 0, {0}};
+unsigned int __cpu_features2;
 
-/* A constructor function that is sets __cpu_model and __cpu_features with
+/* A constructor function that is sets __cpu_model and __cpu_features2 with
    the right values.  This needs to run only once.  This constructor is
    given the highest priority and it should run before constructors without
    the priority set.  However, it still runs after ifunc initializers and
    needs to be called explicitly there.  */
 
 int CONSTRUCTOR_ATTRIBUTE
 __cpu_indicator_init(void) {
   unsigned EAX, EBX, ECX, EDX;
   unsigned MaxLeaf = 5;
   unsigned Vendor;
   unsigned Model, Family, Brand_id;
   unsigned Features = 0;
+  unsigned Features2 = 0;
 
   /* This function needs to run just once.  */
   if (__cpu_model.__cpu_vendor)
     return 0;
 
   if (!isCpuIdSupported())
     return -1;
 
   /* Assume cpuid insn present. Run in level 0 to get vendor id. */
   if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) {
     __cpu_model.__cpu_vendor = VENDOR_OTHER;
     return -1;
   }
   getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
   detectX86FamilyModel(EAX, &Family, &Model);
   Brand_id = EBX & 0xff;
 
   /* Find available features. */
-  getAvailableFeatures(ECX, EDX, MaxLeaf, &Features);
+  getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2);
   __cpu_model.__cpu_features[0] = Features;
+  __cpu_features2 = Features2;
 
   if (Vendor == SIG_INTEL) {
     /* Get CPU type.  */
     getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
                                     &(__cpu_model.__cpu_type),
                                     &(__cpu_model.__cpu_subtype));
     __cpu_model.__cpu_vendor = VENDOR_INTEL;
   } else if (Vendor == SIG_AMD) {