[PowerPC] Fix some missed optimization opportunities in combineSetCC

[HLJ2009]

Summary

1. 0-x == y -> x + y ==0

0-x == y ir is

define i64 @eq(i64, i64) local_unnamed_addr #0 {
  %3 = sub nsw i64 0, %0
  %4 = icmp eq i64 %3, %1
  %5 = zext i1 %4 to i64
  ret i64 %5
}

Now the code generated by llvm is as follows

0000000000000000 <eq>:
   0:	d0 00 63 7c 	neg     r3,r3
   4:	78 22 63 7c 	xor     r3,r3,r4
   8:	74 00 63 7c 	cntlzd  r3,r3
   c:	e2 d7 63 78 	rldicl  r3,r3,58,63
  10:	20 00 80 4e 	blr

We can optimize the code as follows

0000000000000000 <eq>:
   0:	14 1a 64 7c 	add     r3,r4,r3
   4:	74 00 63 7c 	cntlzd  r3,r3
   8:	e2 d7 63 78 	rldicl  r3,r3,58,63
   c:	20 00 80 4e 	blr

2. 0 - x != y -> x + y != 0 0 - x != y ir is

define i64 @neq(i64, i64) local_unnamed_addr #0 {
  %3 = sub nsw i64 0, %0
  %4 = icmp ne i64 %3, %1
  %5 = zext i1 %4 to i64
  ret i64 %5
}

Now the code generated by llvm is as follows

0000000000000000 <neq>:
   0:	d0 00 63 7c 	neg     r3,r3
   4:	78 22 63 7c 	xor     r3,r3,r4
   8:	ff ff 83 30 	addic   r4,r3,-1
   c:	10 19 64 7c 	subfe   r3,r4,r3
  10:	20 00 80 4e 	blr

We can optimize the code as follows

0000000000000000 <neq>:
   0:	14 1a 64 7c 	add     r3,r4,r3
   4:	ff ff 83 30 	addic   r4,r3,-1
   8:	10 19 64 7c 	subfe   r3,r4,r3
   c:	20 00 80 4e 	blr

[nemanjai]

Other than the minor nit, LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12482 ↗

(On Diff #169972)

I think we should probably return an empty SDValue() from that function and change this section to something like:

if (SDValue CSCC = combineSetCC(N, DCI))
  return CSCC;
LLVM_FALLTHROUGH;

14285 ↗

(On Diff #169972)

This is kind of hidden from the top-level view of what combine function is called for which node. I think it is clearer to the reader if we actually call this from PerformDAGCombine() above as I suggested in my comment.

[HLJ2009]

In D53360#1269076, @nemanjai wrote:

Other than the minor nit, LGTM.

Thank you for pointing this out and also thank you for review the code.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h

private:
     SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
+    SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
 
     /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
     /// SETCC with integer subtraction when (1) there is a legal way of doing it
     /// (2) keeping the result of comparison in GPR has performance benefit.
     SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
 
     SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
                             int &RefinementSteps, bool &UseOneConstNR,

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
   SDValue ShiftCst =
       DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
   return DAG.getNode(
       ISD::SRA, dl, N->getValueType(0),
       DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
       ShiftCst);
 }
 
+SDValue PPCTargetLowering::combineSetCC(SDNode *N,
+                                        DAGCombinerInfo &DCI) const {
+  assert(N->getOpcode() == ISD::SETCC &&
+         "Should be called with a SETCC node");
+
+  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+  if (CC == ISD::SETNE || CC == ISD::SETEQ) {
+    SDValue LHS = N->getOperand(0);
+    SDValue RHS = N->getOperand(1);
+
+    // If there is a '0 - y' pattern, canonicalize the pattern to the RHS.
+    if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
+        LHS.hasOneUse())
+      std::swap(LHS, RHS);
+
+    // x == 0-y --> x+y == 0
+    // x != 0-y --> x+y != 0
+    if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
+        RHS.hasOneUse()) {
+      SDLoc DL(N);
+      SelectionDAG &DAG = DCI.DAG;
+      EVT VT = N->getValueType(0);
+      EVT OpVT = LHS.getValueType();
+      SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
+      return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
+    }
+  }
+
+  return DAGCombineTruncBoolExt(N, DCI);
+}
+
 // Is this an extending load from an f32 to an f64?
 static bool isFPExtLoad(SDValue Op) {
   if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op.getNode()))
     return LD->getExtensionType() == ISD::EXTLOAD &&
       Op.getValueType() == MVT::f64;
   return false;
 }
 
case PPCISD::SRA:
     break;
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND:
   case ISD::ANY_EXTEND:
     return DAGCombineExtBoolTrunc(N, DCI);
   case ISD::TRUNCATE:
     return combineTRUNCATE(N, DCI);
   case ISD::SETCC:
+    if (SDValue CSCC = combineSetCC(N, DCI))
+      return CSCC;
+    LLVM_FALLTHROUGH;
   case ISD::SELECT_CC:
     return DAGCombineTruncBoolExt(N, DCI);
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
     return combineFPToIntToFP(N, DCI);
   case ISD::STORE: {
 
     EVT Op1VT = N->getOperand(1).getValueType();

llvm/trunk/test/CodeGen/PowerPC/combine-setcc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:  -ppc-asm-full-reg-names < %s  | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
 ; RUN:  -ppc-asm-full-reg-names < %s  | FileCheck %s
 
 define zeroext i1 @eq1(i1 zeroext %x, i1 zeroext %y) {
 ; CHECK-LABEL: eq1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %sub = sext i1 %x to i32
   %conv3 = zext i1 %y to i32
   %cmp = icmp eq i32 %sub, %conv3
   ret i1 %cmp
 }
 
 define zeroext i8 @eq2(i8 zeroext %x, i8 zeroext %y) {
 ; CHECK-LABEL: eq2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %conv = zext i8 %x to i32
   %sub = sub nsw i32 0, %conv
   %conv1 = zext i8 %y to i32
   %cmp = icmp eq i32 %sub, %conv1
   %conv3 = zext i1 %cmp to i8
   ret i8 %conv3
 }
 
 define signext i16 @eq3(i16 signext %x, i16 signext %y) {
 ; CHECK-LABEL: eq3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %conv = sext i16 %x to i32
   %sub = sub nsw i32 0, %conv
   %conv1 = sext i16 %y to i32
   %cmp = icmp eq i32 %sub, %conv1
   %conv3 = zext i1 %cmp to i16
   ret i16 %conv3
 }
 
 define zeroext i16 @eq4(i16 zeroext %x, i16 zeroext %y) {
 ; CHECK-LABEL: eq4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %conv = zext i16 %x to i32
   %sub = sub nsw i32 0, %conv
   %conv1 = zext i16 %y to i32
   %cmp = icmp eq i32 %sub, %conv1
   %conv3 = zext i1 %cmp to i16
   ret i16 %conv3
 }
 
 define signext i32 @eq5(i32 signext %x, i32 signext %y) {
 ; CHECK-LABEL: eq5:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %sub = sub nsw i32 0, %x
   %cmp = icmp eq i32 %sub, %y
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define zeroext i32 @eq6(i32 zeroext %x, i32 zeroext %y) {
 ; CHECK-LABEL: eq6:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %sub = sub i32 0, %x
   %cmp = icmp eq i32 %sub, %y
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i64 @eq7(i64 %x, i64 %y) {
 ; CHECK-LABEL: eq7:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
 ; CHECK-NEXT:    blr
   %sub = sub nsw i64 0, %x
   %cmp = icmp eq i64 %sub, %y
   %zext = zext i1 %cmp to i64
   ret i64 %zext
 }
 
 define zeroext i1 @eq8(i1 zeroext %x, i1 zeroext %y) {
 ; CHECK-LABEL: eq8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r4, r3
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %conv = zext i1 %y to i32
   %sub = sext i1 %x to i32
   %cmp = icmp eq i32 %conv, %sub
   ret i1 %cmp
 }
 
 define zeroext i8 @eq9(i8 zeroext %x, i8 zeroext %y) {
 ; CHECK-LABEL: eq9:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r4, r4
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %conv = zext i8 %x to i32
   %conv1 = zext i8 %y to i32
   %sub = sub nsw i32 0, %conv1
   %cmp = icmp eq i32 %conv, %sub
   %conv3 = zext i1 %cmp to i8
   ret i8 %conv3
 }
 
 define signext i16 @eq10(i16 signext %x, i16 signext %y) {
 ; CHECK-LABEL: eq10:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r4, r4
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %conv = sext i16 %x to i32
   %conv1 = sext i16 %y to i32
   %sub = sub nsw i32 0, %conv1
   %cmp = icmp eq i32 %conv, %sub
   %conv3 = zext i1 %cmp to i16
   ret i16 %conv3
 }
 
 define zeroext i16 @eq11(i16 zeroext %x, i16 zeroext %y) {
 ; CHECK-LABEL: eq11:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r4, r4
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %conv = zext i16 %x to i32
   %conv1 = zext i16 %y to i32
   %sub = sub nsw i32 0, %conv1
   %cmp = icmp eq i32 %conv, %sub
   %conv3 = zext i1 %cmp to i16
   ret i16 %conv3
 }
 
 define signext i32 @eq12(i32 signext %x, i32 signext %y) {
 ; CHECK-LABEL: eq12:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r4, r4
-; CHECK-NEXT:    xor r3, r4, r3
+; CHECK-NEXT:    add r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %sub = sub nsw i32 0, %y
   %cmp = icmp eq i32 %sub, %x
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define zeroext i32 @eq13(i32 zeroext %x, i32 zeroext %y) {
 ; CHECK-LABEL: eq13:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r4, r4
-; CHECK-NEXT:    xor r3, r4, r3
+; CHECK-NEXT:    add r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
   %sub = sub i32 0, %y
   %cmp = icmp eq i32 %sub, %x
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i64 @eq14(i64 %x, i64 %y) {
 ; CHECK-LABEL: eq14:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r4, r4
-; CHECK-NEXT:    xor r3, r4, r3
+; CHECK-NEXT:    add r3, r3, r4
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
 ; CHECK-NEXT:    blr
   %sub = sub nsw i64 0, %y
   %cmp = icmp eq i64 %sub, %x
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
 }
 
 define zeroext i1 @neq1(i1 zeroext %x, i1 zeroext %y) {
 ; CHECK-LABEL: neq1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
   %sub = sext i1 %x to i32
   %conv3 = zext i1 %y to i32
   %cmp = icmp ne i32 %sub, %conv3
   ret i1 %cmp
 }
 
 define zeroext i8 @neq2(i8 zeroext %x, i8 zeroext %y) {
 ; CHECK-LABEL: neq2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
   %conv = zext i8 %x to i32
   %sub = sub nsw i32 0, %conv
   %conv1 = zext i8 %y to i32
   %cmp = icmp ne i32 %sub, %conv1
   %conv3 = zext i1 %cmp to i8
   ret i8 %conv3
 }
 
 define signext i16 @neq3(i16 signext %x, i16 signext %y) {
 ; CHECK-LABEL: neq3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
   %conv = sext i16 %x to i32
   %sub = sub nsw i32 0, %conv
   %conv1 = sext i16 %y to i32
   %cmp = icmp ne i32 %sub, %conv1
   %conv3 = zext i1 %cmp to i16
   ret i16 %conv3
 }
 
 define zeroext i16 @neq4(i16 zeroext %x, i16 zeroext %y) {
 ; CHECK-LABEL: neq4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
   %conv = zext i16 %x to i32
   %sub = sub nsw i32 0, %conv
   %conv1 = zext i16 %y to i32
   %cmp = icmp ne i32 %sub, %conv1
   %conv3 = zext i1 %cmp to i16
   ret i16 %conv3
 }
 
 define signext i32 @neq5(i32 signext %x, i32 signext %y) {
 ; CHECK-LABEL: neq5:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
   %sub = sub nsw i32 0, %x
   %cmp = icmp ne i32 %sub, %y
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define zeroext i32 @neq6(i32 zeroext %x, i32 zeroext %y) {
 ; CHECK-LABEL: neq6:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
   %sub = sub i32 0, %x
   %cmp = icmp ne i32 %sub, %y
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i64 @neq7(i64 %x, i64 %y) {
 ; CHECK-LABEL: neq7:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
 ; CHECK-NEXT:    blr
   %sub = sub nsw i64 0, %x
   %cmp = icmp ne i64 %sub, %y
   %zext = zext i1 %cmp to i64
   ret i64 %zext
 }
 
 define zeroext i1 @neq8(i1 zeroext %x, i1 zeroext %y) {
 ; CHECK-LABEL: neq8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r4, r3
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
   %conv = zext i1 %y to i32
   %sub = sext i1 %x to i32
   %cmp = icmp ne i32 %conv, %sub
   ret i1 %cmp
 }
 
 define zeroext i8 @neq9(i8 zeroext %x, i8 zeroext %y) {
 ; CHECK-LABEL: neq9:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r4, r3
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
   %conv = zext i8 %y to i32
   %conv1 = zext i8 %x to i32
   %sub = sub nsw i32 0, %conv1
   %cmp = icmp ne i32 %conv, %sub
   %conv3 = zext i1 %cmp to i8
   ret i8 %conv3
 }
 
 define signext i16 @neq10(i16 signext %x, i16 signext %y) {
 ; CHECK-LABEL: neq10:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r4, r3
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
   %conv = sext i16 %y to i32
   %conv1 = sext i16 %x to i32
   %sub = sub nsw i32 0, %conv1
   %cmp = icmp ne i32 %conv, %sub
   %conv3 = zext i1 %cmp to i16
   ret i16 %conv3
 }
 
 define zeroext i16 @neq11(i16 zeroext %x, i16 zeroext %y) {
 ; CHECK-LABEL: neq11:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r4, r3
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i16 %y to i32
   %conv1 = zext i16 %x to i32
   %sub = sub nsw i32 0, %conv1
   %cmp = icmp ne i32 %conv, %sub
   %conv3 = zext i1 %cmp to i16
   ret i16 %conv3
 }
 
 define signext i32 @neq12(i32 signext %x, i32 signext %y) {
 ; CHECK-LABEL: neq12:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %sub = sub nsw i32 0, %x
   %cmp = icmp ne i32 %sub, %y
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define zeroext i32 @neq13(i32 zeroext %x, i32 zeroext %y) {
 ; CHECK-LABEL: neq13:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %sub = sub i32 0, %x
   %cmp = icmp ne i32 %sub, %y
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i64 @neq14(i64 %x, i64 %y) {
 ; CHECK-LABEL: neq14:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    xor r3, r4, r3
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
 ; CHECK-NEXT:    blr
   %sub = sub nsw i64 0, %x
   %cmp = icmp ne i64 %y, %sub
   %zext = zext i1 %cmp to i64
   ret i64 %zext
 }