[Tablegen/SubtargetEmitter] Add Id field to ProcResource

[kariddi]

Summary

Hi,

I made a patch to add a Target managed Id field to the ProcResource structure in the backend scheduling infrastructure.

The idea is that it can be useful to make a scheduling decisions based on which resources a certain instruction/node is using.
The problem is that there's no way to tell what a resource is when you iterate over it in code and because of that you cannot make a decision. We would need a way to know that a certain resource is for example "ALU" or "Issue" to do so.
Another way would be to attach target flags to the instructions and check that (like TSFlags for example) or maintain a function that returns a predicate depending on the instruction opcode, but if the information you need is already encoded in the scheduling resources then duplicating it in the TSFlags and keeping it in sync with your scheduling model seems wasteful and error prone.

This patch adds an Id that the developer can assign any value he wants to and then in C++ code then you could have an enum connecting the values specified in the tablegen model that are easy to read.

For example you could have a procresource called ALU with TargetId = 1 and then have an enum in the scheduler that looks like this:

enum { ProcALU = 1, .... };

You can query the TargetId of a ProcResource by using the getProcResourceTargetId() function passing the ProcResourceId.

[RKSimon]

@kariddi Are you still looking at this, otherwise abandon it?

include/llvm/CodeGen/TargetSchedule.h

unsigned getNumProcResourceKinds() const {
     return SchedModel.getNumProcResourceKinds();
   }
 
   /// Get a processor resource by ID for convenience.
   const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
     return SchedModel.getProcResource(PIdx);
   }
 
+  /// Return the TargetId for the specified ProcResourceIdx.
+  /// The TargetId is a user defined value for the target that
+  /// can be used uniquely identify the type of a processor resource for an
+  /// architecture in C++ code.
+  int getProcResourceTargetId(unsigned ProcResourceIdx) const {
+    return SchedModel.getProcResourceTargetId(ProcResourceIdx);
+  }
+
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
   const char *getResourceName(unsigned PIdx) const {
     if (!PIdx)
       return "MOps";
     return SchedModel.getProcResource(PIdx)->Name;
   }
 #endif
 

include/llvm/MC/MCSchedule.h

struct MCSchedModel {
   static const unsigned DefaultMispredictPenalty = 10;
 
   bool PostRAScheduler; // default value is false
 
   bool CompleteModel;
 
   unsigned ProcID;
   const MCProcResourceDesc *ProcResourceTable;
+  const int *ProcResourceTargetIdTable;
   const MCSchedClassDesc *SchedClassTable;
   unsigned NumProcResourceKinds;
   unsigned NumSchedClasses;
   // Instruction itinerary tables used by InstrItineraryData.
   friend class InstrItineraryData;
   const InstrItinerary *InstrItineraries;
 
   const MCExtraProcessorInfo *ExtraProcessorInfo;
struct MCSchedModel {
 
   const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
     assert(hasInstrSchedModel() && "No scheduling machine model");
 
     assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
     return &ProcResourceTable[ProcResourceIdx];
   }
 
+  /// Return the TargetId for the specified ProcResourceIdx.
+  /// The TargetId is a user defined value for the target that
+  /// can be used uniquely identify the type of a processor resource for an
+  /// architecture in C++ code.
+  int getProcResourceTargetId(unsigned ProcResourceIdx) const {
+    assert(hasInstrSchedModel() && "No scheduling machine model");
+
+    assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
+    return ProcResourceTargetIdTable[ProcResourceIdx];
+  }
+
   const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
     assert(hasInstrSchedModel() && "No scheduling machine model");
 
     assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
     return &SchedClassTable[SchedClassIdx];
   }
 
   /// Returns the latency value for the scheduling class.

include/llvm/Target/TargetSchedule.td

 // EponymousProcResourceKind helps implement ProcResourceUnits by
 // allowing a ProcResourceUnits definition to reference itself. It
 // should not be referenced anywhere else.
 def EponymousProcResourceKind : ProcResourceKind;
 
 // Subtargets typically define processor resource kind and number of
 // units in one place.
 class ProcResource<int num> : ProcResourceKind,
-  ProcResourceUnits<EponymousProcResourceKind, num>;
+  ProcResourceUnits<EponymousProcResourceKind, num> {
+  int TargetId = -1;
+}
 
 class ProcResGroup<list<ProcResource> resources> : ProcResourceKind {
   list<ProcResource> Resources = resources;
   SchedMachineModel SchedModel = ?;
   int BufferSize = -1;
+  int TargetId = -1;
 }
 
 // A target architecture may define SchedReadWrite types and associate
 // them with instruction operands.
 class SchedReadWrite;
 
 // List the per-operand types that map to the machine model of an
 // instruction. One SchedWrite type must be listed for each explicit

lib/MC/MCSchedule.cpp

const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
                                             DefaultLoadLatency,
                                             DefaultHighLatency,
                                             DefaultMispredictPenalty,
                                             false,
                                             true,
                                             0,
                                             nullptr,
                                             nullptr,
+                                            nullptr,
                                             0,
                                             0,
                                             nullptr,
                                             nullptr};
 
 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
                                       const MCSchedClassDesc &SCDesc) {
   int Latency = 0;

test/TableGen/TargetIdTest.td

+// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s -o -
+// Check that the TargetId feature produces the expected output.
+
+include "llvm/Target/Target.td"
+
+def WriteFake : SchedWrite;
+def WriteFake2 : SchedWrite;
+def WriteFake3 : SchedWrite;
+
+def FakeModel : SchedMachineModel {
+  let LoadLatency = 100;
+  let HighLatency = 100;
+
+  let IssueWidth = 1;
+  let MicroOpBufferSize = 0;
+  let CompleteModel = 0;
+}
+
+def FakeUnit : ProcResource<1> {
+  let TargetId = 1;
+  let BufferSize = 0;
+}
+
+def FakeUnit2 : ProcResource<1> {
+  let TargetId = 4;
+  let BufferSize = 0;
+}
+
+def FakeUnit3 : ProcResource<1> {
+  let TargetId = 7;
+  let BufferSize = 0;
+}
+
+def FakeUnit4 : ProcResource<1> {
+  let TargetId = 8;
+  let BufferSize = 0;
+}
+
+let SchedModel = FakeModel in {
+def : WriteRes<WriteFake, [FakeUnit, FakeUnit2]> {
+  let Latency = 10;
+  let ResourceCycles = [1, 2];
+}
+def : WriteRes<WriteFake2, [FakeUnit3]> {
+  let Latency = 10;
+  let ResourceCycles = [1];
+}
+def : WriteRes<WriteFake3, [FakeUnit4]> {
+  let Latency = 10;
+  let ResourceCycles = [1];
+}
+}
+
+def : ProcessorModel<"fake", FakeModel, []>;
+def FakeTarget : Target;
+
+// CHECK: // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
+// CHECK-NEXT: static const llvm::MCProcResourceDesc FakeModelProcResources[] = {
+// CHECK-NEXT:   {"InvalidUnit", 0, 0, 0, 0},
+// CHECK-NEXT:   {"FakeUnit",        1, 0, 0, nullptr}, // #1
+// CHECK-NEXT:   {"FakeUnit2",       1, 0, 0, nullptr}, // #2
+// CHECK-NEXT:   {"FakeUnit3",       1, 0, 0, nullptr}, // #3
+// CHECK-NEXT:   {"FakeUnit4",       1, 0, 0, nullptr}, // #4
+// CHECK-NEXT: };
+// CHECK-EMPTY:
+// CHECK-NEXT: // {Id}
+// CHECK-NEXT: static const int FakeModelProcResourcesTargetIds[] = {
+// CHECK-NEXT:   -1,
+// CHECK-NEXT:   1, // #1
+// CHECK-NEXT:   4, // #2
+// CHECK-NEXT:   7, // #3
+// CHECK-NEXT:   8, // #4
+// CHECK-NEXT: };

utils/TableGen/SubtargetEmitter.cpp

void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
 
   OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n";
   OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
      << "ProcResources"
      << "[] = {\n"
      << "  {\"InvalidUnit\", 0, 0, 0, 0},\n";
 
   unsigned SubUnitsOffset = 1;
+  bool AnyTargetIdPresent = false;
   for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
     Record *PRDef = ProcModel.ProcResourceDefs[i];
 
     Record *SuperDef = nullptr;
     unsigned SuperIdx = 0;
     unsigned NumUnits = 0;
     const unsigned SubUnitsBeginOffset = SubUnitsOffset;
     int BufferSize = PRDef->getValueAsInt("BufferSize");
else {
       if (PRDef->getValueInit("Super")->isComplete()) {
         SuperDef =
             SchedModels.findProcResUnits(PRDef->getValueAsDef("Super"),
                                          ProcModel, PRDef->getLoc());
         SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
       }
       NumUnits = PRDef->getValueAsInt("NumUnits");
     }
+    if (PRDef->getValueAsInt("TargetId") != -1)
+      AnyTargetIdPresent = true;
     // Emit the ProcResourceDesc
     OS << "  {\"" << PRDef->getName() << "\", ";
     if (PRDef->getName().size() < 15)
       OS.indent(15 - PRDef->getName().size());
     OS << NumUnits << ", " << SuperIdx << ", " << BufferSize << ", ";
     if (SubUnitsBeginOffset != SubUnitsOffset) {
       OS << ProcModel.ModelName << "ProcResourceSubUnits + "
          << SubUnitsBeginOffset;
     } else {
       OS << "nullptr";
     }
     OS << "}, // #" << i+1;
     if (SuperDef)
       OS << ", Super=" << SuperDef->getName();
     OS << "\n";
   }
   OS << "};\n";
+  // Emit TargetId table for processor if IDs are present
+  if (AnyTargetIdPresent) {
+    OS << "\n// {Id}\n";
+    OS << "static const int " << ProcModel.ModelName << "ProcResourcesTargetIds"
+       << "[] = {\n"
+       << "  -1,"
+       << "\n";
+    for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
+      Record *PRDef = ProcModel.ProcResourceDefs[i];
+      int TargetId = PRDef->getValueAsInt("TargetId");
+      OS << "  " << TargetId << ", // #" << i + 1 << "\n";
+    }
+    OS << "};\n";
+  }
 }
 
 // Find the WriteRes Record that defines processor resources for this
 // SchedWrite.
 Record *SubtargetEmitter::FindWriteResources(
   const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {
 
   // Check if the SchedWrite is already subtarget-specific and directly
for (const CodeGenProcModel &PM : SchedModels.procModels()) {
 
     bool CompleteModel =
       (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false);
 
     OS << "  " << (CompleteModel ? "true" : "false") << ", // "
        << "CompleteModel\n";
 
     OS << "  " << PM.Index << ", // Processor ID\n";
-    if (PM.hasInstrSchedModel())
-      OS << "  " << PM.ModelName << "ProcResources" << ",\n"
-         << "  " << PM.ModelName << "SchedClasses" << ",\n"
-         << "  " << PM.ProcResourceDefs.size()+1 << ",\n"
-         << "  " << (SchedModels.schedClassEnd()
-                     - SchedModels.schedClassBegin()) << ",\n";
+    if (PM.hasInstrSchedModel()) {
+      bool HasProcResourceDefsId = false;
+      for (auto *PRG : PM.ProcResourceDefs)
+        if (PRG->getValueAsInt("TargetId") != -1) {
+          HasProcResourceDefsId = true;
+          break;
+        }
+      OS << "  " << PM.ModelName << "ProcResources"
+         << ",\n";
+      if (HasProcResourceDefsId)
+        OS << "  " << PM.ModelName << "ProcResourcesTargetIds"
+           << ",\n";
       else
-      OS << "  nullptr, nullptr, 0, 0,"
+        OS << "  "
+           << "nullptr,\n";
+      OS << "  " << PM.ModelName << "SchedClasses"
+         << ",\n"
+         << "  " << PM.ProcResourceDefs.size() + 1 << ",\n"
+         << "  "
+         << (SchedModels.schedClassEnd() - SchedModels.schedClassBegin())
+         << ",\n";
+    } else
+      OS << "  nullptr, nullptr, nullptr, 0, 0,"
          << " // No instruction-level machine model.\n";
     if (PM.hasItineraries())
       OS << "  " << PM.ItinsDef->getName() << ",\n";
     else
       OS << "  nullptr, // No Itinerary\n";
     if (PM.hasExtraProcessorInfo())
       OS << "  &" << PM.ModelName << "ExtraInfo,\n";
     else