This is an archive of the discontinued LLVM Phabricator instance.

AMDGPU: Only add implicit super-reg def for first subreg
ClosedPublic

Authored by arsenm on Oct 2 2018, 6:23 PM.

Download Raw Diff

Details

Reviewers

rampitec
MatzeB
ronlieb

Diff Detail

Event Timeline

arsenm created this revision.Oct 2 2018, 6:23 PM

Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptOct 2 2018, 6:23 PM

ping

is this patch worthy of a lit test ?

In D52817#1259935, @ronlieb wrote:

is this patch worthy of a lit test ?

Not really. This doesn't really change anything, but simplifies a future patch

ronlieb accepted this revision.Oct 9 2018, 8:16 PM

This revision is now accepted and ready to land.Oct 9 2018, 8:16 PM

r347572

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

SIRegisterInfo.cpp

4 lines

Diff 168065

lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 895 Lines • ▼ Show 20 Lines	if (SpillToSMEM) {

auto MIB =		auto MIB =
BuildMI(*MBB, MI, DL, TII->get(ScalarLoadOp), SubReg)		BuildMI(*MBB, MI, DL, TII->get(ScalarLoadOp), SubReg)
.addReg(MFI->getScratchRSrcReg()) // sbase		.addReg(MFI->getScratchRSrcReg()) // sbase
.addReg(OffsetReg, RegState::Kill) // soff		.addReg(OffsetReg, RegState::Kill) // soff
.addImm(0) // glc		.addImm(0) // glc
.addMemOperand(MMO);		.addMemOperand(MMO);

if (NumSubRegs > 1)		if (NumSubRegs > 1 && i == 0)
MIB.addReg(SuperReg, RegState::ImplicitDefine);		MIB.addReg(SuperReg, RegState::ImplicitDefine);

continue;		continue;
}		}

if (SpillToVGPR) {		if (SpillToVGPR) {
SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];		SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
auto MIB =		auto MIB =
BuildMI(*MBB, MI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),		BuildMI(*MBB, MI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
SubReg)		SubReg)
.addReg(Spill.VGPR)		.addReg(Spill.VGPR)
.addImm(Spill.Lane);		.addImm(Spill.Lane);

if (NumSubRegs > 1)		if (NumSubRegs > 1 && i == 0)
MIB.addReg(SuperReg, RegState::ImplicitDefine);		MIB.addReg(SuperReg, RegState::ImplicitDefine);
} else {		} else {
if (OnlyToVGPR)		if (OnlyToVGPR)
return false;		return false;

// Restore SGPR from a stack slot.		// Restore SGPR from a stack slot.
// FIXME: We should use S_LOAD_DWORD here for VI.		// FIXME: We should use S_LOAD_DWORD here for VI.
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);		unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
▲ Show 20 Lines • Show All 675 Lines • Show Last 20 Lines