AArch64FastISel: Abort intrinsic selection if the left operand didn't select

[MatzeB]

Summary

Unfortunately I cannot produce a testcase for this as I would need an llvm constant expression that would fail to select via fast-isel. So far all my attempts at forcing this situation failed.

rdar://44642447

[t.p.northover]

I've had a go at producing an example too with no luck. The Constant involved on the breaking config is ridiculously complex (even after reduction): i32 or (i32 shl (i32 or (i32 shl (i32 or (i32 shl (i32 and (i32 ptrtoint ([19 x i8]* @0 to i32), i32 63), i32 8), i32 and (i32 lshr (i32 ptrtoint ([19 x i8]* @0 to i32), i32 6), i32 63)), i32 8), i32 and (i32 lshr (i32 lshr (i32 ptrtoint ([19 x i8]* @0 to i32), i32 6), i32 6), i32 63)), i32 8), i32 lshr (i32 lshr (i32 lshr (i32 ptrtoint ([19 x i8]* @0 to i32), i32 6), i32 6), i32 6))

And since the change is obviously right, I think you should go ahead.

lib/Target/AArch64/AArch64FastISel.cpp

case Intrinsic::umul_with_overflow: {
     }
 
     if (MulReg) {
       ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
               TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
     }
 
+    if (!ResultReg1)
+      return false;
+
     ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
                                   AArch64::WZR, /*IsKill=*/true, AArch64::WZR,
                                   /*IsKill=*/true, getInvertedCondCode(CC));
     (void)ResultReg2;
     assert((ResultReg1 + 1) == ResultReg2 &&
            "Nonconsecutive result registers.");
     updateValueMap(II, ResultReg1, 2);
     return true;