[WebAssembly] v4f32.abs and v2f64.abs

[tlively]

Summary

implement lowering of @llvm.fabs for vector types.

[tlively]

Closed by rL342513.

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst,
   defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
                               !add(!add(baseInst, step), step)>;
 }
 multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
   defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
   defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
                               !add(baseInst, 1)>;
 }
+multiclass SIMDAbs<ValueType vec_t, string vec, bits<32> simdop> {
+  defm ABS_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+                           [(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))],
+                           vec#".abs\t$dst, $vec", vec#".abs", simdop>;
+}
 
 let Defs = [ARGUMENTS] in {
 defm "" : ConstVec<v16i8,
                    (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
                         vec_i8imm_op:$i2, vec_i8imm_op:$i3,
                         vec_i8imm_op:$i4, vec_i8imm_op:$i5,
                         vec_i8imm_op:$i6, vec_i8imm_op:$i7,
                         vec_i8imm_op:$i8, vec_i8imm_op:$i9,

 defm LE : SIMDConditionFP<"le", SETOLE, 96>;
 defm GT_S : SIMDConditionInt<"gt_s", SETGT, 98, 2>;
 defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 99, 2>;
 defm GT : SIMDConditionFP<"gt", SETOGT, 104>;
 defm GE_S : SIMDConditionInt<"ge_s", SETGE, 106, 2>;
 defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 107, 2>;
 defm GE : SIMDConditionFP<"ge", SETOGE, 112>;
 
+defm "" : SIMDAbs<v4f32, "f32x4", 116>;
+defm "" : SIMDAbs<v2f64, "f64x2", 117>;
+
 } // Defs = [ARGUMENTS]
 
 // Def load and store patterns from WebAssemblyInstrMemory.td for vector types
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
 
 def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>;

test/CodeGen/WebAssembly/simd-arith.ll

 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @neg_v4f32(<4 x float> %x) {
   %a = fsub <4 x float> <float 0., float 0., float 0., float 0.>, %x
   ret <4 x float> %a
 }
 
+; CHECK-LABEL: abs_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.abs $push0=, $0{{$}}
+; SIMD128-NEXT: return $pop0{{$}}
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
+define <4 x float> @abs_v4f32(<4 x float> %x) {
+  %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
+  ret <4 x float> %a
+}
+
 ; CHECK-LABEL: add_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .param v128, v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fadd <4 x float> %x, %y

 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @neg_v2f64(<2 x double> %x) {
   %a = fsub <2 x double> <double 0., double 0.>, %x
   ret <2 x double> %a
 }
 
+; CHECK-LABEL: abs_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.abs $push0=, $0{{$}}
+; SIMD128-NEXT: return $pop0{{$}}
+declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone
+define <2 x double> @abs_v2f64(<2 x double> %x) {
+  %a = call <2 x double> @llvm.fabs.v2f64(<2 x double> %x)
+  ret <2 x double> %a
+}
+
+
 ; CHECK-LABEL: add_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .param v128, v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {

test/MC/WebAssembly/simd-encodings.s

# RUN: llvm-mc -show-encoding -triple=wasm32-unkown-unknown -mattr=+sign-ext,+simd128 < %s | FileCheck %s
     f64x2.ge
 
     # CHECK: f32x4.neg # encoding: [0xfd,0x72]
     f32x4.neg
 
     # CHECK: f64x2.neg # encoding: [0xfd,0x73]
     f64x2.neg
 
+    # CHECK: f32x4.abs # encoding: [0xfd,0x74]
+    f32x4.abs
+
+    # CHECK: f64x2.abs # encoding: [0xfd,0x75]
+    f64x2.abs
+
     # CHECK: f32x4.add # encoding: [0xfd,0x7a]
     f32x4.add
 
     # CHECK: f64x2.add # encoding: [0xfd,0x7b]
     f64x2.add
 
     # CHECK: f32x4.sub # encoding: [0xfd,0x7c]
     f32x4.sub