[PowerPC] Support operand modifier 'x' in inline asm

[syzaara]

Summary

gcc uses operand modifier 'x' in inline asm for VSX registers. Without this modifier, instructions which use VSX numbering for their operands are printed as VMX registers. This patch adds support for the operand modifier 'x'.

[jsji]

Is this also supported and defined in Intel syntax? Do we need to check AsmVariant here?

[jsji]

llvm/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll

1 ↗

(On Diff #166016)

Add -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names ?

8 ↗

(On Diff #166016)

The testcase here tests path of isVRRegister and VSL register, is it possible that we include another testcase to go through isVFRegister register path?

[nemanjai]

LGTM after Jinsong's comments are addressed.
+1 for the test case comments.

I don't think we need to worry about Intel syntax for this modifier since we don't for any of the other modifiers. In fact, I don't think we have any support for Intel syntax on PPC.

llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp

case 'L': // Write second word of DImode reference.
       ++OpNo;   // Return the high-part.
       break;
     case 'I':
       // Write 'i' if an integer constant, otherwise nothing.  Used to print
       // addi vs add, etc.
       if (MI->getOperand(OpNo).isImm())
         O << "i";
       return false;
+    case 'x':
+      if(!MI->getOperand(OpNo).isReg())
+        return true;
+      // This operand uses VSX numbering.
+      // If the operand is a VMX register, convert it to a VSX register.
+      unsigned Reg = MI->getOperand(OpNo).getReg();
+      if (PPCInstrInfo::isVRRegister(Reg))
+        Reg = PPC::VSX32 + (Reg - PPC::V0);
+      else if (PPCInstrInfo::isVFRegister(Reg))
+        Reg = PPC::VSX32 + (Reg - PPC::VF0);
+      const char *RegName;
+      RegName = PPCInstPrinter::getRegisterName(Reg);
+      RegName = stripRegisterPrefix(RegName);
+      O << RegName;
+      return false;
     }
   }
 
   printOperand(MI, OpNo, O);
   return false;
 }
 
 // At the moment, all inline asm memory operands are a single register.

llvm/trunk/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll

+; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names  -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+define signext i32 @foo(<4 x float> %__A) {
+entry:
+  %0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3;\0Axscvspdp ${1:x},${1:x};\0Afctiw  $1,$1;\0Amfvsrd  $0,${1:x};\0A", "=r,=&^wa,^wa"(<4 x float> %__A)
+  %asmresult = extractvalue { i32, <4 x float> } %0, 0
+  ret i32 %asmresult
+; CHECK: #APP
+; CHECK: xxsldwi vs0, v2, v2, 3
+; CHECK: xscvspdp f0, f0
+; CHECK: fctiw f0, f0
+; CHECK: mffprd r3, f0
+; CHECK: #NO_APP
+}
+
+define double @test() {
+  entry:
+    %0 = tail call double asm "mtvsrd ${0:x}, 1", "=^ws,~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14}"()
+    ret double %0
+; CHECK: #APP
+; CHECK: mtvsrd v2, r1
+; CHECK: #NO_APP
+}