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[docs][AtomicExpandPass] Document the alternate lowering strategy for part-word atomicrmw/cmpxchg
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Authored by asb on Sep 18 2018, 7:33 AM.

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Summary

D47882, D48130 and D48131 introduce a new lowering strategy for part-word atomicrmw/cmpxchg and uses it to lower these operations for the RISC-V target. Rather than having AtomicExpandPass produce the LL/SC loop in the IR level, it instead calculates the necessary mask values and inserts a target-specific intrinsic, which is lowered at a much later stage (after register allocation). This ensures that architecture-specific restrictions for forward-progress in LL/SC loops can be guaranteed.

This patch documents this new AtomicExpandPass functionality. See the previous llvm-dev RFC for more info.

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rL LLVM

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asb created this revision.Sep 18 2018, 7:33 AM
jyknight accepted this revision.Sep 18 2018, 9:59 AM

I'd prefer it to more strongly indicate that the IR-level LL/SC lowering is broken and should not be used in the future, and hopefully will be removed once targets have migrated off of it.

But since there is not yet universal agreement for doing that, this is fine for the moment.

docs/Atomics.rst
474 ↗(On Diff #165975)

I'd insert a "However, " here.

This revision is now accepted and ready to land.Sep 18 2018, 9:59 AM
asb updated this revision to Diff 166131.Sep 19 2018, 8:03 AM
asb marked an inline comment as done.

Update to add a 'However' has suggested by @jyknight. Thanks for the review.

I'd also prefer to stronger statements to encourage the use of late-stage lowering, but as you say there's more work to be done in terms of getting community support for that.

I'll hold off on committing until D48131 lands, as that contains the masked cmpxchg expansion implementation that is referenced.

This revision was automatically updated to reflect the committed changes.