[WebAssembly] Handle V128RegClass in more places

[tlively]

Summary

Adds logic to handle V128RegClass wherever possible. It is still not
handled in selectSelect in WebAssemblyFastISel, but there is no v128
select, so that would be more complicated anyway.

[dschuff]

Are there tests that trigger these? It might make sense to add a case at least to the explicit locals and reg stackify. Probably fast-isel support should be a separate change (you can take the existing SIMD tests and run the same test, forcing fast-isel as some of the other tests do)

[aheejin]

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

123

Do we have a test for this?

[tlively]

Needs to be split up and tested.

lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

static MVT typeForRegClass(const TargetRegisterClass *RC) {
   if (RC == &WebAssembly::I32RegClass)
     return MVT::i32;
   if (RC == &WebAssembly::I64RegClass)
     return MVT::i64;
   if (RC == &WebAssembly::F32RegClass)
     return MVT::f32;
   if (RC == &WebAssembly::F64RegClass)
     return MVT::f64;
+  if (RC == &WebAssembly::V128RegClass)
+    return MVT::v16i8;
   if (RC == &WebAssembly::EXCEPT_REFRegClass)
     return MVT::ExceptRef;
   llvm_unreachable("unrecognized register class");
 }
 
 /// Given a MachineOperand of a stackified vreg, return the instruction at the
 /// start of the expression tree.
 static MachineInstr *findStartOfTree(MachineOperand &MO,

lib/Target/WebAssembly/WebAssemblyFastISel.cpp

bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
   case MVT::f32:
     Opc = WebAssembly::LOAD_F32;
     RC = &WebAssembly::F32RegClass;
     break;
   case MVT::f64:
     Opc = WebAssembly::LOAD_F64;
     RC = &WebAssembly::F64RegClass;
     break;
+  case MVT::v16i8:
+    Opc = WebAssembly::LOAD_v16i8;
+    RC = &WebAssembly::V128RegClass;
+    break;
+  case MVT::v8i16:
+    Opc = WebAssembly::LOAD_v8i16;
+    RC = &WebAssembly::V128RegClass;
+    break;
+  case MVT::v4i32:
+    Opc = WebAssembly::LOAD_v4i32;
+    RC = &WebAssembly::V128RegClass;
+    break;
+  case MVT::v2i64:
+    Opc = WebAssembly::LOAD_v2i64;
+    RC = &WebAssembly::V128RegClass;
+    break;
+  case MVT::v4f32:
+    Opc = WebAssembly::LOAD_v4f32;
+    RC = &WebAssembly::V128RegClass;
+    break;
+  case MVT::v2f64:
+    Opc = WebAssembly::LOAD_v2f64;
+    RC = &WebAssembly::V128RegClass;
+    break;
   default:
     return false;
   }
 
   materializeLoadStoreOperands(Addr);
 
   unsigned ResultReg = createResultReg(RC);
   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),

lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (RC == &WebAssembly::I32RegClass)
     CopyOpcode = WebAssembly::COPY_I32;
   else if (RC == &WebAssembly::I64RegClass)
     CopyOpcode = WebAssembly::COPY_I64;
   else if (RC == &WebAssembly::F32RegClass)
     CopyOpcode = WebAssembly::COPY_F32;
   else if (RC == &WebAssembly::F64RegClass)
     CopyOpcode = WebAssembly::COPY_F64;
+  else if (RC == &WebAssembly::V128RegClass)
+    CopyOpcode = WebAssembly::COPY_V128;
   else
     llvm_unreachable("Unexpected register class");
 
   BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
       .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
 }
 
 MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl(

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

if (RegClass == &WebAssembly::I32RegClass) {
     ConstantFP *Val = cast<ConstantFP>(Constant::getNullValue(
         Type::getFloatTy(MF.getFunction().getContext())));
     MI->addOperand(MachineOperand::CreateFPImm(Val));
   } else if (RegClass == &WebAssembly::F64RegClass) {
     MI->setDesc(TII->get(WebAssembly::CONST_F64));
     ConstantFP *Val = cast<ConstantFP>(Constant::getNullValue(
         Type::getDoubleTy(MF.getFunction().getContext())));
     MI->addOperand(MachineOperand::CreateFPImm(Val));
+  } else if (RegClass == &WebAssembly::V128RegClass) {
+    MI->setDesc(TII->get(WebAssembly::CONST_V128_v2i64));
+    MI->addOperand(MachineOperand::CreateImm(0));
+    MI->addOperand(MachineOperand::CreateImm(0));
   } else {
     llvm_unreachable("Unexpected reg class");
   }
 }
 
 // Determine whether a call to the callee referenced by
 // MI->getOperand(CalleeOpNo) reads memory, writes memory, and/or has side
 // effects.