This is an archive of the discontinued LLVM Phabricator instance.

Differential D52060

AMDGPU: Add a fast path for icmp.i1(src, false, NE)
ClosedPublic

Authored by mareko on Sep 13 2018, 2:30 PM.

Details

Reviewers
arsenm
nhaehnle
Commits
rG33eb4d947d82: AMDGPU: Add a fast path for icmp.i1(src, false, NE)
rL351150: AMDGPU: Add a fast path for icmp.i1(src, false, NE)
Summary

This allows moving the condition from the intrinsic to the standard ICmp
opcode, so that LLVM can do simplifications on it. The icmp.i1 intrinsic
is an identity for retrieving the SGPR mask.

And we can also get the mask from and i1, or i1, xor i1.

Diff Detail

Repository
rL LLVM

Event Timeline

mareko created this revision.Sep 13 2018, 2:30 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptSep 13 2018, 2:30 PM
Harbormaster completed remote builds in B22617: Diff 165383.Sep 13 2018, 2:30 PM
arsenm added a comment.Sep 13 2018, 10:05 PM

Should the instcombine part change also to allow creation of i1 uses?

mareko added a comment.Sep 21 2018, 12:01 AM
In D52060#1234370, @arsenm wrote:

Should the instcombine part change also to allow creation of i1 uses?

What do you mean by that? I'm not sure what you mean.

arsenm added a comment.Sep 24 2018, 6:04 AM
In D52060#1241470, @mareko wrote:
In D52060#1234370, @arsenm wrote:

Should the instcombine part change also to allow creation of i1 uses?

What do you mean by that? I'm not sure what you mean.

In InstCombineCalls we whitelist bitwidth sizes that are legal, so if the input compare is an i1 compare, it will fold into the intrinsic

mareko updated this revision to Diff 168520.Oct 5 2018, 1:31 PM
mareko edited the summary of this revision. (Show Details)

AMDGPU: Add a fast path for icmp.i1(src, false, NE)

Summary:
This allows moving the condition from the intrinsic to the standard ICmp
opcode, so that LLVM can do simplifications on it. The icmp.i1 intrinsic
is an identity for retrieving the SGPR mask.

And we can also get the mask from and i1, or i1, xor i1.

Don't fold icmp in InstCombineCalls.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D52060

Harbormaster completed remote builds in B23531: Diff 168520.Oct 5 2018, 1:31 PM
arsenm added inline comments.Oct 29 2018, 6:30 PM
lib/Transforms/InstCombine/InstCombineCalls.cpp
3656–3658 ↗(On Diff #168520)

Needs test in InstCombine

mareko added inline comments.Nov 20 2018, 3:18 PM
lib/Transforms/InstCombine/InstCombineCalls.cpp
3656–3658 ↗(On Diff #168520)

What should the test do?

arsenm added inline comments.Nov 20 2018, 3:59 PM
lib/Transforms/InstCombine/InstCombineCalls.cpp
3656–3658 ↗(On Diff #168520)

use an original i1 eq/ne comparison. Like the others, just i1

mareko updated this revision to Diff 175387.Nov 26 2018, 8:29 PM
mareko edited the summary of this revision. (Show Details)

Add InstCombine tests.

Harbormaster completed remote builds in B25359: Diff 175387.Nov 26 2018, 8:30 PM
This revision was not accepted when it landed; it landed in state Needs Review.Jan 14 2019, 6:17 PM
Closed by commit rL351150: AMDGPU: Add a fast path for icmp.i1(src, false, NE) (authored by mareko). · Explain Why
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
5 lines
5 lines
Transforms/
InstCombine/
5 lines
test/
CodeGen/
AMDGPU/
18 lines
Transforms/
InstCombine/
AMDGPU/
193 lines

Diff 181693

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,349 Lines • ▼ Show 20 Lines case Intrinsic::amdgcn_div_scale: {
// division operation. // division operation.
SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator; SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0, return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
Denominator, Numerator); Denominator, Numerator);
} }
case Intrinsic::amdgcn_icmp: { case Intrinsic::amdgcn_icmp: {
// There is a Pat that handles this variant, so return it as-is.
if (Op.getOperand(1).getValueType() == MVT::i1 &&
Op.getConstantOperandVal(2) == 0 &&
Op.getConstantOperandVal(3) == ICmpInst::Predicate::ICMP_NE)
return Op;
return lowerICMPIntrinsic(*this, Op.getNode(), DAG); return lowerICMPIntrinsic(*this, Op.getNode(), DAG);
} }
case Intrinsic::amdgcn_fcmp: { case Intrinsic::amdgcn_fcmp: {
return lowerFCMPIntrinsic(*this, Op.getNode(), DAG); return lowerFCMPIntrinsic(*this, Op.getNode(), DAG);
} }
case Intrinsic::amdgcn_fmed3: case Intrinsic::amdgcn_fmed3:
return DAG.getNode(AMDGPUISD::FMED3, DL, VT, return DAG.getNode(AMDGPUISD::FMED3, DL, VT,
Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
▲ Show 20 Lines • Show All 4,256 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 577 Lines • ▼ Show 20 Lines
def : Pat < def : Pat <
(int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))), (int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))),
(SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond)) (SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond))
>; >;
// TODO: we could add more variants for other types of conditionals // TODO: we could add more variants for other types of conditionals
def : Pat <
(int_amdgcn_icmp i1:$src, (i1 0), (i32 33)),
(COPY $src) // Return the SGPRs representing i1 src
>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VOP1 Patterns // VOP1 Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] in { let SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] in {
//def : RcpPat<V_RCP_F64_e32, f64>; //def : RcpPat<V_RCP_F64_e32, f64>;
//defm : RsqPat<V_RSQ_F64_e32, f64>; //defm : RsqPat<V_RSQ_F64_e32, f64>;
▲ Show 20 Lines • Show All 1,092 Lines • Show Last 20 Lines

llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp

Show First 20 Lines • Show All 3,754 Lines • ▼ Show 20 Lines if (match(Src1, m_Zero()) &&
Intrinsic::ID NewIID = CmpInst::isFPPredicate(SrcPred) ? Intrinsic::ID NewIID = CmpInst::isFPPredicate(SrcPred) ?
Intrinsic::amdgcn_fcmp : Intrinsic::amdgcn_icmp; Intrinsic::amdgcn_fcmp : Intrinsic::amdgcn_icmp;
Type *Ty = SrcLHS->getType(); Type *Ty = SrcLHS->getType();
if (auto *CmpType = dyn_cast<IntegerType>(Ty)) { if (auto *CmpType = dyn_cast<IntegerType>(Ty)) {
// Promote to next legal integer type. // Promote to next legal integer type.
unsigned Width = CmpType->getBitWidth(); unsigned Width = CmpType->getBitWidth();
unsigned NewWidth = Width; unsigned NewWidth = Width;
// Don't do anything for i1 comparisons.
if (Width == 1)
break;
if (Width <= 16) if (Width <= 16)
NewWidth = 16; NewWidth = 16;
else if (Width <= 32) else if (Width <= 32)
NewWidth = 32; NewWidth = 32;
else if (Width <= 64) else if (Width <= 64)
NewWidth = 64; NewWidth = 64;
else if (Width > 64) else if (Width > 64)
break; // Can't handle this. break; // Can't handle this.
▲ Show 20 Lines • Show All 947 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0 declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) #0 declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) #0
declare i64 @llvm.amdgcn.icmp.i16(i16, i16, i32) #0 declare i64 @llvm.amdgcn.icmp.i16(i16, i16, i32) #0
declare i64 @llvm.amdgcn.icmp.i1(i1, i1, i32) #0
; No crash on invalid input ; No crash on invalid input
; GCN-LABEL: {{^}}v_icmp_i32_dynamic_cc: ; GCN-LABEL: {{^}}v_icmp_i32_dynamic_cc:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @v_icmp_i32_dynamic_cc(i64 addrspace(1)* %out, i32 %src, i32 %cc) { define amdgpu_kernel void @v_icmp_i32_dynamic_cc(i64 addrspace(1)* %out, i32 %src, i32 %cc) {
%result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 %cc) %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 %cc)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 294 Lines • ▼ Show 20 Lines
; SI-DAG: s_sext_i32_i16 [[CVT:s[0-9]+]], s{{[0-9]+}} ; SI-DAG: s_sext_i32_i16 [[CVT:s[0-9]+]], s{{[0-9]+}}
; SI: v_cmp_le_i32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] ; SI: v_cmp_le_i32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]]
define amdgpu_kernel void @v_icmp_i16_sle(i64 addrspace(1)* %out, i16 %src) { define amdgpu_kernel void @v_icmp_i16_sle(i64 addrspace(1)* %out, i16 %src) {
%result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 41) %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 41)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_icmp_i1_ne0:
; GCN: v_cmp_gt_u32_e64 s[[C0:\[[0-9]+:[0-9]+\]]],
; GCN: v_cmp_gt_u32_e64 s[[C1:\[[0-9]+:[0-9]+\]]],
; GCN: s_and_b64 s[[SRC:\[[0-9]+:[0-9]+\]]], s[[C0]], s[[C1]]
; SI-NEXT: s_mov_b32 s{{[0-9]+}}, -1
; GCN-NEXT: v_mov_b32_e32
; GCN-NEXT: v_mov_b32_e32
; GCN-NEXT: {{global|flat|buffer}}_store_dwordx2
define amdgpu_kernel void @v_icmp_i1_ne0(i64 addrspace(1)* %out, i32 %a, i32 %b) {
%c0 = icmp ugt i32 %a, 1
%c1 = icmp ugt i32 %b, 2
%src = and i1 %c0, %c1
%result = call i64 @llvm.amdgcn.icmp.i1(i1 %src, i1 false, i32 33)
store i64 %result, i64 addrspace(1)* %out
ret void
}
attributes #0 = { nounwind readnone convergent } attributes #0 = { nounwind readnone convergent }

llvm/trunk/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll

Show First 20 Lines • Show All 1,400 Lines • ▼ Show 20 Lines
} }
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; llvm.amdgcn.icmp ; llvm.amdgcn.icmp
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) nounwind readnone convergent declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) nounwind readnone convergent
declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) nounwind readnone convergent declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) nounwind readnone convergent
declare i64 @llvm.amdgcn.icmp.i1(i1, i1, i32) nounwind readnone convergent
; Make sure there's no crash for invalid input ; Make sure there's no crash for invalid input
; CHECK-LABEL: @invalid_nonconstant_icmp_code( ; CHECK-LABEL: @invalid_nonconstant_icmp_code(
; CHECK: call i64 @llvm.amdgcn.icmp.i32(i32 %a, i32 %b, i32 %c) ; CHECK: call i64 @llvm.amdgcn.icmp.i32(i32 %a, i32 %b, i32 %c)
define i64 @invalid_nonconstant_icmp_code(i32 %a, i32 %b, i32 %c) { define i64 @invalid_nonconstant_icmp_code(i32 %a, i32 %b, i32 %c) {
%result = call i64 @llvm.amdgcn.icmp.i32(i32 %a, i32 %b, i32 %c) %result = call i64 @llvm.amdgcn.icmp.i32(i32 %a, i32 %b, i32 %c)
ret i64 %result ret i64 %result
} }
▲ Show 20 Lines • Show All 393 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret i64 [[MASK]] ; CHECK-NEXT: ret i64 [[MASK]]
define i64 @fold_icmp_ne_0_zext_icmp_ult_i16(i16 %a, i16 %b) { define i64 @fold_icmp_ne_0_zext_icmp_ult_i16(i16 %a, i16 %b) {
%cmp = icmp ult i16 %a, %b %cmp = icmp ult i16 %a, %b
%zext.cmp = zext i1 %cmp to i32 %zext.cmp = zext i1 %cmp to i32
%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33) %mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
ret i64 %mask ret i64 %mask
} }
; 1-bit NE comparisons
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i1(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_eq_i1(i32 %a, i32 %b) {
%cmp = icmp eq i32 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ne_i1(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_ne_i1(i32 %a, i32 %b) {
%cmp = icmp ne i32 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_sle_i1(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_sle_i1(i32 %a, i32 %b) {
%cmp = icmp sle i32 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ugt_i64(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_ugt_i64(i64 %a, i64 %b) {
%cmp = icmp ugt i64 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_swap_i64(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_ult_swap_i64(i64 %a, i64 %b) {
%cmp = icmp ugt i64 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 false, i1 %cmp, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_oeq_f32(
; CHECK-NEXT: fcmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_fcmp_oeq_f32(float %a, float %b) {
%cmp = fcmp oeq float %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_une_f32(
; CHECK-NEXT: fcmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_fcmp_une_f32(float %a, float %b) {
%cmp = fcmp une float %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_olt_f64(
; CHECK-NEXT: fcmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_fcmp_olt_f64(double %a, double %b) {
%cmp = fcmp olt double %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i4(
; CHECK-NEXT: icmp
; CHECK: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_eq_i4(i4 %a, i4 %b) {
%cmp = icmp eq i4 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i8(
; CHECK-NEXT: icmp
; CHECK: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_eq_i8(i8 %a, i8 %b) {
%cmp = icmp eq i8 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i16(
; CHECK-NEXT: icmp
; CHECK: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_eq_i16(i16 %a, i16 %b) {
%cmp = icmp eq i16 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i36(
; CHECK-NEXT: icmp
; CHECK: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_eq_i36(i36 %a, i36 %b) {
%cmp = icmp eq i36 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i128(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_eq_i128(i128 %a, i128 %b) {
%cmp = icmp eq i128 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_oeq_f16(
; CHECK-NEXT: fcmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_fcmp_oeq_f16(half %a, half %b) {
%cmp = fcmp oeq half %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_oeq_f128(
; CHECK-NEXT: fcmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_fcmp_oeq_f128(fp128 %a, fp128 %b) {
;
%cmp = fcmp oeq fp128 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_slt_i4(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_slt_i4(i4 %a, i4 %b) {
%cmp = icmp slt i4 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_slt_i8(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_slt_i8(i8 %a, i8 %b) {
%cmp = icmp slt i8 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_slt_i16(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_slt_i16(i16 %a, i16 %b) {
%cmp = icmp slt i16 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_i4(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_ult_i4(i4 %a, i4 %b) {
%cmp = icmp ult i4 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_i8(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_ult_i8(i8 %a, i8 %b) {
%cmp = icmp ult i8 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_i16(
; CHECK-NEXT: icmp
; CHECK-NEXT: call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
define i64 @fold_icmp_i1_ne_0_icmp_ult_i16(i16 %a, i16 %b) {
%cmp = icmp ult i16 %a, %b
%mask = call i64 @llvm.amdgcn.icmp.i1(i1 %cmp, i1 false, i32 33)
ret i64 %mask
}
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; llvm.amdgcn.fcmp ; llvm.amdgcn.fcmp
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
declare i64 @llvm.amdgcn.fcmp.f32(float, float, i32) nounwind readnone convergent declare i64 @llvm.amdgcn.fcmp.f32(float, float, i32) nounwind readnone convergent
; Make sure there's no crash for invalid input ; Make sure there's no crash for invalid input
; CHECK-LABEL: @invalid_nonconstant_fcmp_code( ; CHECK-LABEL: @invalid_nonconstant_fcmp_code(
▲ Show 20 Lines • Show All 115 Lines • Show Last 20 Lines