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Differential D52040

[PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8
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Authored by jsji on Sep 13 2018, 8:13 AM.

Details

Reviewers
hfinkel
nemanjai
stefanp
Commits
rGf1b0b47b2d04: [PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8
rL342441: [PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8
Summary

When doing some instruction scheduling work, we noticed some missing itineraries.

Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling,
because we can still get same latency due to default values.

With machine scheduler, however, itineraries will have impact to scheduling.
eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class.
And most of the instruction class with itineraries will have NumMicroOps default to 1.

This will has impact on the count of RetiredMOps, affects the Pending/Available Queue,
then causing different scheduling or suboptimal scheduling further.

This patch is for IIC_IntMulHD, and we add a new testcase in https://reviews.llvm.org/D52039 to show the difference.

Diff Detail

Event Timeline

jsji created this revision.Sep 13 2018, 8:13 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptSep 13 2018, 8:13 AM
nemanjai accepted this revision.Sep 14 2018, 7:35 AM

LGTM.

This revision is now accepted and ready to land.Sep 14 2018, 7:35 AM
Closed by commit rL342441: [PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8 (authored by • qshanz). · Explain WhySep 17 2018, 7:06 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
4 lines
4 lines
test/
CodeGen/
PowerPC/
2 lines

Diff 165299

llvm/lib/Target/PowerPC/PPCScheduleP7.td

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Linesdef P7Itineraries : ProcessorItineraries<
InstrItinData<IIC_IntMulHW , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_IntMulHW , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>, P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>], InstrStage<1, [P7_FX1, P7_FX2]>],
[4, 1, 1]>, [4, 1, 1]>,
InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>, P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>], InstrStage<1, [P7_FX1, P7_FX2]>],
[4, 1, 1]>, [4, 1, 1]>,
InstrItinData<IIC_IntMulHD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntMulLI , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_IntMulLI , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>, P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>], InstrStage<1, [P7_FX1, P7_FX2]>],
[4, 1, 1]>, [4, 1, 1]>,
InstrItinData<IIC_IntRotate , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_IntRotate , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>, P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>], InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>, [1, 1, 1]>,
▲ Show 20 Lines • Show All 277 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCScheduleP8.td

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesdef P8Itineraries : ProcessorItineraries<
InstrItinData<IIC_IntMulHW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, InstrItinData<IIC_IntMulHW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>, P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>], InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>, [4, 1, 1]>,
InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>, P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>], InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>, [4, 1, 1]>,
InstrItinData<IIC_IntMulHD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntMulLI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, InstrItinData<IIC_IntMulLI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>, P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>], InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>, [4, 1, 1]>,
InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>, P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>], InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>, [1, 1, 1]>,
▲ Show 20 Lines • Show All 310 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/mulld.ll

Show All 12 Lines
; CHECK-NEXT: mulld ; CHECK-NEXT: mulld
; CHECK-NEXT: mulhdu ; CHECK-NEXT: mulhdu
; CHECK-NEXT: mulld ; CHECK-NEXT: mulld
; CHECK-NEXT: mulhdu ; CHECK-NEXT: mulhdu
; CHECK-ITIN-LABEL: bn_mul_comba8: ; CHECK-ITIN-LABEL: bn_mul_comba8:
; CHECK-ITIN: mulhdu ; CHECK-ITIN: mulhdu
; CHECK-ITIN-NEXT: mulhdu
; CHECK-ITIN-NEXT: mulld ; CHECK-ITIN-NEXT: mulld
; CHECK-ITIN-NEXT: mulhdu ; CHECK-ITIN-NEXT: mulhdu
; CHECK-ITIN-NEXT: mulld ; CHECK-ITIN-NEXT: mulld
; CHECK-ITIN-NEXT: mulhdu
%1 = load i64, i64* %a, align 8 %1 = load i64, i64* %a, align 8
%conv = zext i64 %1 to i128 %conv = zext i64 %1 to i128
%2 = load i64, i64* %b, align 8 %2 = load i64, i64* %b, align 8
%conv2 = zext i64 %2 to i128 %conv2 = zext i64 %2 to i128
%mul = mul nuw i128 %conv2, %conv %mul = mul nuw i128 %conv2, %conv
%shr = lshr i128 %mul, 64 %shr = lshr i128 %mul, 64
%agep = getelementptr inbounds i64, i64* %a, i64 1 %agep = getelementptr inbounds i64, i64* %a, i64 1
Show All 21 Lines