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[mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instruction
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Authored by atanasyan on Sep 7 2018, 12:47 AM.

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Summary

MIPS ISAs start to support third operand for the rdhwr instruction starting from Revision 6. But LLVM generates assembler code with three-operands version of this instruction on any MIPS64 ISA. The third operand is always zero, so in case of direct code generation we get correct code.

This patch fixes the bug by adding an instruction alias. The same alias already exists for 32-bit ISA.

Ideally, we also need to reject three-operands version of the rdhwr instruction in an assembler code if ISA revision is less than 6. That is a task for a separate patch.

This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861)

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rL LLVM

Event Timeline

atanasyan created this revision.Sep 7 2018, 12:47 AM
This revision was not accepted when it landed; it landed in state Needs Review.Sep 11 2018, 2:59 AM
This revision was automatically updated to reflect the committed changes.