[WebAssembly] Add missing SIMD instruction attributes

[tlively]

Summary

These attributes are copied from equivalent instructions in
WebAssemblyInstrInfo.td.

[tlively]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

22 ↗

(On Diff #163426)

I actually have no idea what isReMaterializable means, but the other const instructions had it.

[dschuff]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

29 ↗

(On Diff #163426)

I don't think loads and stores are really as cheap as a move (I think "move" means the RISC definition of a move, i.e. "not also a load"). Also wasm loads and stores are potentially more expensive than x86 loads and stores anyway if bounds checking is not free.

[tlively]

• Remove isAsCheapAsAMove from mem ops

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

29 ↗

(On Diff #163426)

You're right, I think I got these loads and stores mixed up with set_local/get_local.

[aheejin]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

22 ↗

(On Diff #163426)

Is isAsCheapAsAMove true for this? Because it basically means putting 128-bit worth of values onto the stack.

[tlively]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

22 ↗

(On Diff #163426)

Not actually sure, especially when you think about what this instruction turns into on the backend. I could imagine that for some embedders this is as cheap as a move and for others it is not.

[tlively]

• Remove isAsCheapAsAMove from v128.const

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 
 // constrained immediate argument types
 foreach SIZE = [8, 16] in
 def ImmI#SIZE : ImmLeaf<i32, "return (Imm & ((1UL << "#SIZE#") - 1)) == Imm;">;
 foreach SIZE = [2, 4, 8, 16, 32] in
 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
 
 multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
+  let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in
   defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
                                   [(set V128:$dst, (vec_t pat))],
                                   "v128.const\t$dst, "#args,
                                   "v128.const\t"#args, 0>;
 }
 multiclass SIMDLoad<ValueType vec_t> {
-  let mayLoad = 1 in
+  let mayLoad = 1, isAsCheapAsAMove = 1 in
   defm LOAD_#vec_t :
     SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
            (outs), (ins P2Align:$align, offset32_op:$off), [],
            "v128.load\t$dst, ${off}(${addr})$align",
            "v128.load\t$off$align", 1>;
 }
 multiclass SIMDStore<ValueType vec_t> {
-  let mayStore = 1 in
+  let mayStore = 1, isAsCheapAsAMove = 1 in
   defm STORE_#vec_t :
     SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
            (outs), (ins P2Align:$align, offset32_op:$off), [],
            "v128.store\t${off}(${addr})$align, $vec",
            "v128.store\t$off$align", 2>;
 }
 multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t,
                        WebAssemblyRegClass reg_t, bits<32> simdop,