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[AArch64] NFC: Refactoring to prepare for vector PCS.
ClosedPublic

Authored by sdesmalen on Aug 30 2018, 2:16 AM.

Details

Summary

This patch refactors several parts of AArch64FrameLowering
so that it can be easily extended to support saving/restoring
of FPR128 (Q) registers.

Diff Detail

Event Timeline

sdesmalen created this revision.Aug 30 2018, 2:16 AM
thegameg added inline comments.Aug 30 2018, 5:57 AM
lib/Target/AArch64/AArch64FrameLowering.cpp
495

You can probably get rid of this now.

1377

I think the size should always be 8 even if it's paired. The instruction will end up having 2 x MachineMemOperand load of size 8.

test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll
209

I agree that this should be fixed, but I think the assumption here is wrong, and I think this is where this should be fixed.

sdesmalen marked 2 inline comments as done.Aug 31 2018, 2:51 AM
sdesmalen added inline comments.
lib/Target/AArch64/AArch64FrameLowering.cpp
1377

You're absolutely right! I'll fix that in AsmPrinter.cpp in a separate patch.

sdesmalen updated this revision to Diff 163492.Aug 31 2018, 2:52 AM

Fixed issue with incorrect size of MachineMemOperand.

thegameg accepted this revision.Aug 31 2018, 5:17 AM

Thanks @sdesmalen, LGTM!

This revision is now accepted and ready to land.Aug 31 2018, 5:17 AM

Thanks @thegameg ! I've also created a patch to better describe the size of bytes spilled/reloaded for LDP/STP instructions in D51537.

This revision was automatically updated to reflect the committed changes.