[WebAssembly] v128.not

[tlively]

Summary

Implementation and tests.

[tlively]

• Fix SIMD-VM tests for bitwise instructions

[aheejin]

test/CodeGen/WebAssembly/simd-arith.ll

50

What causes this change? Is this relevant to this patch?

[tlively]

test/CodeGen/WebAssembly/simd-arith.ll

50

No, I just realized they should be changed because the bitwise instructions do not have the vector types in their names, so these checks were previously infallible. I'll split this into a separate CL.

[tlively]

• remove unrelated test changes

[tlively]

Closed by commit rL340857

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 1)>;
 }
 multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
   defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
 }
+multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> {
+  defm NOT_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
+                           (outs), (ins),
+                           [(set
+                             (vec_t V128:$dst),
+                             (vec_t (xor
+                               (vec_t V128:$vec),
+                               (vec_t (splat_pat (lane_t -1)))
+                             ))
+                           )],
+                           "v128.not\t$dst, $vec", "v128.not", 62>;
+}
 
 let Defs = [ARGUMENTS] in {
 defm "" : ConstVec<v16i8,
                    (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
                         vec_i8imm_op:$i2, vec_i8imm_op:$i3,
                         vec_i8imm_op:$i4, vec_i8imm_op:$i5,
                         vec_i8imm_op:$i6, vec_i8imm_op:$i7,
                         vec_i8imm_op:$i8, vec_i8imm_op:$i9,

 defm DIV : SIMDBinaryFP<fdiv, "div", 126>;
 
 let isCommutable = 1 in {
 defm AND : SIMDBitwise<and, "and", 59>;
 defm OR : SIMDBitwise<or, "or", 60>;
 defm XOR : SIMDBitwise<xor, "xor", 61>;
 } // isCommutable = 1
 
+defm "" : SIMDNot<v16i8, splat16, i32>;
+defm "" : SIMDNot<v8i16, splat8, i32>;
+defm "" : SIMDNot<v4i32, splat4, i32>;
+defm "" : SIMDNot<v2i64, splat2, i64>;
+
 } // Defs = [ARGUMENTS]
 
 // follow convention of making implicit expansions unsigned
 def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
           (EXTRACT_LANE_v16i8_u V128:$vec, (i32 LaneIdx16:$idx))>;
 def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
           (EXTRACT_LANE_v8i16_u V128:$vec, (i32 LaneIdx8:$idx))>;
 

test/CodeGen/WebAssembly/simd-arith.ll

 ; SIMD128: i8x16.mul $push0=, $0, $1 # encoding: [0xfd,0x20]{{$}}
 ; SIMD128: return $pop0 #
 define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = mul <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: and_v16i8
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: v128.and $push0=, $0, $1 # encoding: [0xfd,0x3b]{{$}}
 ; SIMD128: return $pop0 #
 define <16 x i8> @and_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = and <16 x i8> %x, %y
   ret <16 x i8> %a
 }

 ; SIMD128: .result v128{{$}}
 ; SIMD128: v128.xor $push0=, $0, $1 # encoding: [0xfd,0x3d]{{$}}
 ; SIMD128: return $pop0 #
 define <16 x i8> @xor_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = xor <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
+; CHECK-LABEL: not_v16i8
+; NO-SIMD128-NOT: v128
+; SIMD128: .param v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}}
+; SIMD128: return $pop0 #
+define <16 x i8> @not_v16i8(<16 x i8> %x) {
+  %a = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1,
+                          i8 -1, i8 -1, i8 -1, i8 -1,
+                          i8 -1, i8 -1, i8 -1, i8 -1,
+                          i8 -1, i8 -1, i8 -1, i8 -1>
+  ret <16 x i8> %a
+}
+
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: add_v8i16
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i16x8.add $push0=, $0, $1 # encoding: [0xfd,0x19]{{$}}

 ; SIMD128: .result v128{{$}}
 ; SIMD128: v128.xor $push0=, $0, $1 # encoding: [0xfd,0x3d]{{$}}
 ; SIMD128: return $pop0 #
 define <8 x i16> @xor_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = xor <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
+; CHECK-LABEL: not_v8i16
+; NO-SIMD128-NOT: v128
+; SIMD128: .param v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}}
+; SIMD128: return $pop0 #
+define <8 x i16> @not_v8i16(<8 x i16> %x) {
+  %a = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1,
+                          i16 -1, i16 -1, i16 -1, i16 -1>
+  ret <8 x i16> %a
+}
+
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: add_v4i32
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i32x4.add $push0=, $0, $1 # encoding: [0xfd,0x1a]{{$}}

 ; SIMD128: .result v128{{$}}
 ; SIMD128: v128.xor $push0=, $0, $1 # encoding: [0xfd,0x3d]{{$}}
 ; SIMD128: return $pop0 #
 define <4 x i32> @xor_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = xor <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
+; CHECK-LABEL: not_v4i32
+; NO-SIMD128-NOT: v128
+; SIMD128: .param v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}}
+; SIMD128: return $pop0 #
+define <4 x i32> @not_v4i32(<4 x i32> %x) {
+  %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %a
+}
+
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: add_v2i64
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}

 ; SIMD128: .result v128{{$}}
 ; SIMD128: v128.xor $push0=, $0, $1 # encoding: [0xfd,0x3d]{{$}}
 ; SIMD128: return $pop0 #
 define <2 x i64> @xor_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = xor <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
+; CHECK-LABEL: not_v2i64
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128: .param v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}}
+; SIMD128: return $pop0 #
+define <2 x i64> @not_v2i64(<2 x i64> %x) {
+  %a = xor <2 x i64> %x, <i64 -1, i64 -1>
+  ret <2 x i64> %a
+}
+
 ; ==============================================================================
 ; 4 x float
 ; ==============================================================================
 ; CHECK-LABEL: add_v4f32
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: f32x4.add $push0=, $0, $1 # encoding: [0xfd,0x7a]{{$}}