[PPC64] Fix DQ-form instruction handeling and emit error for misalignment on a *_DS relocations

[sfertile]

Summary

Patch fixes the handling of *_DS relocations used on DQ-form instructions where we were overwriting some of the extended opcode bits. Also adds an alignment check so that the user will receive a diagnostic error if the value we are writing isn't properly aligned.

[ruiu]

LGTM

ELF/Arch/PPC64.cpp

102

encoding -> Encoding

103

Add a blank line before comment.

104

This function is small and used only once. I'd inline it and remove it.

ELF/Arch/PPC64.cpp

 static uint16_t lo(uint64_t V) { return V; }
 static uint16_t hi(uint64_t V) { return V >> 16; }
 static uint16_t ha(uint64_t V) { return (V + 0x8000) >> 16; }
 static uint16_t higher(uint64_t V) { return V >> 32; }
 static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; }
 static uint16_t highest(uint64_t V) { return V >> 48; }
 static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; }
 
+// Extracts the 'PO' field of an instruction encoding.
+static uint8_t getPrimaryOpCode(uint32_t Encoding) { return (Encoding >> 26); }
+
+static bool isDQFormInstruction(uint32_t Encoding) {
+  switch (getPrimaryOpCode(Encoding)) {
+  default:
+    return false;
+  case 56:
+    // The only instruction with a primary opcode of 56 is `lq`.
+    return true;
+  case 61:
+    // There are both DS and DQ instruction forms with this primary opcode.
+    // Namely `lxv` and `stxv` are the DQ-forms that use it.
+    // The DS 'XO' bits being set to 01 is restricted to DQ form.
+    return (Encoding & 3) == 0x1;
+  }
+}
+
 PPC64::PPC64() {
   GotRel = R_PPC64_GLOB_DAT;
   PltRel = R_PPC64_JMP_SLOT;
   RelativeRel = R_PPC64_RELATIVE;
   IRelativeRel = R_PPC64_IRELATIVE;
   GotEntrySize = 8;
   PltEntrySize = 4;
   GotPltEntrySize = 8;
void PPC64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
   case R_PPC64_GOT_TPREL16_LO_DS:
   case R_PPC64_GOT_TPREL16_DS: {
     uint32_t RegNo = read32(Loc - Offset) & 0x03E00000; // bits 6-10
     write32(Loc - Offset, 0x3C0D0000 | RegNo);          // addis RegNo, r13
     relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
     break;
   }
   case R_PPC64_TLS: {
-    uint32_t PrimaryOp = (read32(Loc) & 0xFC000000) >> 26; // bits 0-5
+    uint32_t PrimaryOp = getPrimaryOpCode(read32(Loc));
     if (PrimaryOp != 31)
       error("unrecognized instruction for IE to LE R_PPC64_TLS");
     uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30
     uint32_t DFormOp = getDFormOp(SecondaryOp);
     write32(Loc, ((DFormOp << 26) | (read32(Loc) & 0x03FFFFFF)));
     relocateOne(Loc + Offset, R_PPC64_TPREL16_LO, Val);
     break;
   }
case R_PPC64_ADDR14: {
     break;
   }
   case R_PPC64_ADDR16:
   case R_PPC64_TPREL16:
     checkInt(Loc, Val, 16, Type);
     write16(Loc, Val);
     break;
   case R_PPC64_ADDR16_DS:
-  case R_PPC64_TPREL16_DS:
+  case R_PPC64_TPREL16_DS: {
     checkInt(Loc, Val, 16, Type);
-    write16(Loc, (read16(Loc) & 3) | (Val & ~3));
-    break;
+    // DQ-form instructions use bits 28-31 as part of the instruction encoding
+    // DS-form instructions only use bits 30-31.
+    uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 2U : 0U;
+    uint16_t Mask = isDQFormInstruction(read32(Loc - EndianOffset)) ? 0xF : 0x3;
+    checkAlignment(Loc, lo(Val), Mask + 1, Type);
+    write16(Loc, (read16(Loc) & Mask) | lo(Val));
+  } break;
   case R_PPC64_ADDR16_HA:
   case R_PPC64_REL16_HA:
   case R_PPC64_TPREL16_HA:
     write16(Loc, ha(Val));
     break;
   case R_PPC64_ADDR16_HI:
   case R_PPC64_REL16_HI:
   case R_PPC64_TPREL16_HI:
case R_PPC64_TPREL16_HIGHESTA:
     write16(Loc, highesta(Val));
     break;
   case R_PPC64_ADDR16_LO:
   case R_PPC64_REL16_LO:
   case R_PPC64_TPREL16_LO:
     write16(Loc, lo(Val));
     break;
   case R_PPC64_ADDR16_LO_DS:
-  case R_PPC64_TPREL16_LO_DS:
-    write16(Loc, (read16(Loc) & 3) | (lo(Val) & ~3));
-    break;
+  case R_PPC64_TPREL16_LO_DS: {
+    // DQ-form instructions use bits 28-31 as part of the instruction encoding
+    // DS-form instructions only use bits 30-31.
+    uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 2U : 0U;
+    uint16_t Mask = isDQFormInstruction(read32(Loc - EndianOffset)) ? 0xF : 0x3;
+    checkAlignment(Loc, lo(Val), Mask + 1, Type);
+    write16(Loc, (read16(Loc) & Mask) | lo(Val));
+  } break;
   case R_PPC64_ADDR32:
   case R_PPC64_REL32:
     checkInt(Loc, Val, 32, Type);
     write32(Loc, Val);
     break;
   case R_PPC64_ADDR64:
   case R_PPC64_REL64:
   case R_PPC64_TOC:

test/ELF/ppc64-dq.s

+# REQUIRES: ppc
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: llvm-objdump -D %t | FileCheck %s
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: llvm-objdump -D %t | FileCheck %s
+
+        .global test
+        .p2align        4
+        .type   test,@function
+test:
+.Lgep:
+        addis 2, 12, .TOC.-.Lgep@ha
+        addi  2, 2,  .TOC.-.Lgep@l
+.Llep:
+        .localentry test, .Llep-.Lgep
+        addis 3, 2, qword@toc@ha
+        lxv   3, qword@toc@l(3)
+        addis 3, 2, qword@toc@ha
+        stxv  3, qword@toc@l(3)
+        blr
+
+       .comm qword, 16, 16
+
+# Verify that we don't overwrite any of the extended opcode bits on a DQ form
+# instruction.
+# CHECK-LABEL: test
+# CHECK:         lxv 3, -32768(3)
+# CHECK:         stxv 3, -32768(3)

test/ELF/ppc64-error-missaligned-dq.s

+# REQUIRES: ppc
+#
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
+# RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
+# RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
+
+# CHECK: improper alignment for relocation R_PPC64_ADDR16_LO_DS: 0x8001 is not aligned to 16 bytes
+
+        .global test
+        .p2align        4
+        .type   test,@function
+test:
+.Lgep:
+        addis 2, 12, .TOC.-.Lgep@ha
+        addi  2, 2,  .TOC.-.Lgep@l
+.Llep:
+        .localentry test, .Llep-.Lgep
+        addis 3, 2, qword@toc@ha
+        lxv   3, qword@toc@l(3)
+        blr
+
+       .comm pad, 1, 1
+       .comm qword, 16, 1
+

test/ELF/ppc64-error-missaligned-ds.s

+# REQUIRES: ppc
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
+# RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
+# RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
+
+# CHECK: improper alignment for relocation R_PPC64_ADDR16_LO_DS: 0x8001 is not aligned to 4 bytes
+
+        .global test
+        .p2align        4
+        .type   test,@function
+test:
+.Lgep:
+        addis 2, 12, .TOC.-.Lgep@ha
+        addi  2, 2,  .TOC.-.Lgep@l
+.Llep:
+        .localentry test, .Llep-.Lgep
+        addis 3, 2, word@toc@ha
+        lwa   3, word@toc@l(3)
+        blr
+
+       .comm pad, 1, 1
+       .comm word, 4, 1
+