Add R_HEX_B9_PCREL and R_HEX_B9_PCREL_X relocation support

[sidneym]

Summary

Add support for 2 more relocs and a testcase.

[sidneym]

I'd like to get these patches merged if they are OK. More are on the way.

[ruiu]

LGTM

This should be fine to be merged, and as long as other patches are as simple as this, they should be fine too, given that they won't at least harm non-Hexagon users.

lld/trunk/ELF/Arch/Hexagon.cpp

for (size_t Bit = 0; Bit != 32; ++Bit) {
     }
   }
   return Result;
 }
 
 RelExpr Hexagon::getRelExpr(RelType Type, const Symbol &S,
                             const uint8_t *Loc) const {
   switch (Type) {
+  case R_HEX_B9_PCREL:
+  case R_HEX_B9_PCREL_X:
   case R_HEX_B15_PCREL:
   case R_HEX_B15_PCREL_X:
   case R_HEX_B22_PCREL:
   case R_HEX_B22_PCREL_X:
   case R_HEX_B32_PCREL_X:
   case R_HEX_6_PCREL_X:
     return R_PC;
   default:
case R_HEX_16_X:  // This reloc only has 6 effective bits.
     or32le(Loc, applyMask(findMaskR16(read32le(Loc)), Val & 0x3f));
     break;
   case R_HEX_32:
     or32le(Loc, Val);
     break;
   case R_HEX_32_6_X:
     or32le(Loc, applyMask(0x0fff3fff, Val >> 6));
     break;
+  case R_HEX_B9_PCREL:
+    or32le(Loc, applyMask(0x003000fe, Val >> 2));
+    break;
+  case R_HEX_B9_PCREL_X:
+    or32le(Loc, applyMask(0x003000fe, Val & 0x3f));
+    break;
   case R_HEX_B15_PCREL:
     or32le(Loc, applyMask(0x00df20fe, Val >> 2));
     break;
   case R_HEX_B15_PCREL_X:
     or32le(Loc, applyMask(0x00df20fe, Val & 0x3f));
     break;
   case R_HEX_B22_PCREL:
     or32le(Loc, applyMask(0x1ff3ffe, Val >> 2));

lld/trunk/test/ELF/hexagon.s

 
 # 0x78000000
 r0 = ##_start
 # CHECK: 7800c000   r0 = ##69632 }
 
 # 0xb0000000
 r0 = add(r1, ##_start)
 # CHECK: b001c000   r0 = add(r1,##69632) }
+
+# R_HEX_B9_PCREL:
+{r0=#1 ; jump #_start}
+# CHECK: jump 0x11000
+
+# R_HEX_B9_PCREL_X:
+{r0=#1 ; jump ##_start}
+# CHECK: jump 0x11000