[mips][microMIPS] Implement ADDIUSP instruction

[jkolek]

Summary

Implement 16-bit microMIPS add immediate unsigned word to stack pointer - ADDIUSP.

[sstankovic]

For this instruction there seems to be a difference between microMIPS reference and GAS, regarding the decoded value of a offset. microMIPS reference says that allowable values for a offset are [2, 3, ..., 256, 257] and [-3, -4, ..., -257, -258], and this value is shifted by 2 to give final stack offset. GAS allows only shifted (final) values: [8, 12, ... , 1024, 1028] and [-12, -16, ... , -1028, -1032]. I suggest to follow GAS approach, because .s file is much easier to read if final offset is used. Of course, encoded values are identical.

[sstankovic]

LGTM, with a change of variable name to uppercase.

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

380

Variable name should start with uppercase.

Closed by commit rL219500 (authored by zjovanovic).

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
             expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
             return false;
           }
         }
       }
     } // for
   }   // if load/store
 
-  if (inMicroMipsMode() && Inst.getOpcode() == Mips::ADDIUS5_MM) {
+  if (inMicroMipsMode() && (Inst.getOpcode() == Mips::ADDIUS5_MM ||
+                            Inst.getOpcode() == Mips::ADDIUSP_MM)) {
+    if (Inst.getOpcode() == Mips::ADDIUS5_MM) {
       MCOperand Opnd = Inst.getOperand(2);
       if (!Opnd.isImm())
         return Error(IDLoc, "expected immediate operand kind");
       int Imm = Opnd.getImm();
       if (Imm < -8 || Imm > 7)
         return Error(IDLoc, "immediate operand value out of range");
+    } else {
+      MCOperand Opnd = Inst.getOperand(0);
+      if (!Opnd.isImm())
+        return Error(IDLoc, "expected immediate operand kind");
+      int Imm = Opnd.getImm();
+      if (Imm < -258 || Imm > 257 || (Imm < 2 && Imm > -3))
+        return Error(IDLoc, "unexpected immediate operand value");
+    }
   }
 
   if (needsExpansion(Inst))
     return expandInstruction(Inst, IDLoc, Instructions);
   else
     Instructions.push_back(Inst);
 
   return false;

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

unsigned getImm5Shr2Value(const MCInst &MI, unsigned OpNo,
                             const MCSubtargetInfo &STI) const;
 
   // getAddius5Value - Return binary encoding of the microMIPS addius5
   // instruction immediate operand.
   unsigned getAddius5Value(const MCInst &MI, unsigned OpNo,
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const;
 
+  // getAddiuspValue - Return binary encoding of the microMIPS addiusp
+  // instruction immediate operand.
+  unsigned getAddiuspValue(const MCInst &MI, unsigned OpNo,
+                           SmallVectorImpl<MCFixup> &Fixups,
+                           const MCSubtargetInfo &STI) const;
+
   // getBranchTargetOpValue - Return binary encoding of the branch
   // target operand. If the machine operand requires relocation,
   // record the relocation and return zero.
   unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
                                   SmallVectorImpl<MCFixup> &Fixups,
                                   const MCSubtargetInfo &STI) const;
 
   // getBranchTargetOpValue - Return binary encoding of the microMIPS branch

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

getAddius5Value(const MCInst &MI, unsigned OpNo,
 
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isImm()) return MO.getImm() & 0xf;
 
   return 0;
 }
 
 unsigned MipsMCCodeEmitter::
+getAddiuspValue(const MCInst &MI, unsigned OpNo,
+                SmallVectorImpl<MCFixup> &Fixups,
+                const MCSubtargetInfo &STI) const {
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+  if (MO.isImm()) {
+    unsigned binary = MO.getImm() & 0x0000ffff;
+    return (((binary & 0x8000) >> 7) | (binary & 0x00ff));
+  }
+
+  return 0;
+}
+
+unsigned MipsMCCodeEmitter::
 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
                const MCSubtargetInfo &STI) const {
   int64_t Res;
 
   if (Expr->EvaluateAsAbsolute(Res))
     return Res;
 
   MCExpr::ExprKind Kind = Expr->getKind();

lib/Target/Mips/MicroMipsInstrFormats.td

class ADDIUS5_FM_MM16 {
   bits<16> Inst;
 
   let Inst{15-10} = 0x13;
   let Inst{9-5}   = rd;
   let Inst{4-1}   = imm;
   let Inst{0}     = 0;
 }
 
+class ADDIUSP_FM_MM16 {
+  bits<9> imm;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0x13;
+  let Inst{9-1}   = imm;
+  let Inst{0}     = 1;
+}
+
 class MOVE_FM_MM16<bits<6> funct> {
   bits<5> rs;
   bits<5> rd;
 
   bits<16> Inst;
 
   let Inst{15-10} = funct;
   let Inst{9-5}   = rd;

lib/Target/Mips/MicroMipsInstrInfo.td

 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
 
 def simm12 : Operand<i32> {
   let DecoderMethod = "DecodeSimm12";
 }
 
 def imm5shr2 : Operand<OtherVT> {
   let EncoderMethod = "getImm5Shr2Value";
 }
 
 def addius5_imm : Operand<i32> {
   let EncoderMethod = "getAddius5Value";
 }
 
+def addiusp_imm : Operand<i32> {
+  let EncoderMethod = "getAddiuspValue";
+}
+
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops GPR32, simm12);
   let EncoderMethod = "getMemEncodingMMImm12";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
 }
 

 
 class AddImmUS5<string opstr, RegisterOperand RO> :
   MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, addius5_imm:$imm),
                   !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
   let Constraints = "$rd = $dst";
   let isCommutable = 1;
 }
 
+class AddImmUSP<string opstr> :
+  MicroMipsInst16<(outs), (ins addiusp_imm:$imm),
+                  !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
+
 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
       MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
   [], II_MFHI_MFLO, FrmR> {
   let Uses = [UseReg];
   let hasSideEffects = 0;
 }
 
 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
             [], IIBranch, FrmR>;
 
   class BranchZeroLinkMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
     InstSE<(outs), (ins RO:$rs, opnd:$offset),
            !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
 }
 
 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
+def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
 def JALRS16_MM : JumpLinkRegSMM16<"jalrs", GPR32Opnd>, JALR_FM_MM16<0x09>;
 def JRC16_MM : JumpLinkRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;

lib/Target/Mips/MipsCodeEmitter.cpp

private:
 
   unsigned getRelocation(const MachineInstr &MI,
                          const MachineOperand &MO) const;
 
   unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getImm5Shr2Value(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getAddius5Value(const MachineInstr &MI, unsigned OpNo) const;
+  unsigned getAddiuspValue(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
                                     unsigned OpNo) const;
 
   unsigned getBranchTarget21OpValue(const MachineInstr &MI,
                                     unsigned OpNo) const;
   unsigned getBranchTarget26OpValue(const MachineInstr &MI,
                                     unsigned OpNo) const;
   unsigned getJumpOffset16OpValue(const MachineInstr &MI, unsigned OpNo) const;

 }
 
 unsigned MipsCodeEmitter::getAddius5Value(const MachineInstr &MI,
                                           unsigned OpNo) const {
   llvm_unreachable("Unimplemented function.");
   return 0;
 }
 
+unsigned MipsCodeEmitter::getAddiuspValue(const MachineInstr &MI,
+                                          unsigned OpNo) const {
+  llvm_unreachable("Unimplemented function.");
+  return 0;
+}
+
 unsigned MipsCodeEmitter::getBranchTargetOpValueMM(const MachineInstr &MI,
                                                    unsigned OpNo) const {
   llvm_unreachable("Unimplemented function.");
   return 0;
 }
 
 unsigned MipsCodeEmitter::getBranchTarget21OpValue(const MachineInstr &MI,
                                                    unsigned OpNo) const {

test/MC/Mips/micromips-16-bit-instructions.s

 # RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips | \
 # RUN: FileCheck -check-prefix=CHECK-EL %s
 # RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips | \
 # RUN: FileCheck -check-prefix=CHECK-EB %s
 # Check that the assembler can handle the documented syntax
 # for arithmetic and logical instructions.
 #------------------------------------------------------------------------------
 # MicroMIPS 16-bit Instructions
 #------------------------------------------------------------------------------
 # Little endian
 #------------------------------------------------------------------------------
 # CHECK-EL: addius5 $7, -2          # encoding: [0xfc,0x4c]
+# CHECK-EL: addiusp -255            # encoding: [0x03,0x4e]
 # CHECK-EL: mfhi    $9              # encoding: [0x09,0x46]
 # CHECK-EL: mflo    $9              # encoding: [0x49,0x46]
 # CHECK-EL: move    $25, $1         # encoding: [0x21,0x0f]
 # CHECK-EL: jrc     $9              # encoding: [0xa9,0x45]
 # CHECK-EL: jr16    $9              # encoding: [0x89,0x45]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: jalr    $9              # encoding: [0xc9,0x45]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: jalrs   $9              # encoding: [0x29,0x45]
 # CHECK-EL: move    $zero, $zero    # encoding: [0x00,0x0c]
 # CHECK-EL: jraddiusp 20            # encoding: [0x05,0x47]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
 # CHECK-EB: addius5 $7, -2          # encoding: [0x4c,0xfc]
+# CHECK-EB: addiusp -255            # encoding: [0x4e,0x03]
 # CHECK-EB: mfhi    $9              # encoding: [0x46,0x09]
 # CHECK-EB: mflo    $9              # encoding: [0x46,0x49]
 # CHECK-EB: move    $25, $1         # encoding: [0x0f,0x21]
 # CHECK-EB: jrc     $9              # encoding: [0x45,0xa9]
 # CHECK-EB: jr16    $9              # encoding: [0x45,0x89]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: jalr    $9              # encoding: [0x45,0xc9]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: jalrs   $9              # encoding: [0x45,0x29]
 # CHECK-EB: move    $zero, $zero    # encoding: [0x0c,0x00]
 # CHECK-EB: jraddiusp 20            # encoding: [0x47,0x05]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 
     addius5 $7, -2
+    addiusp -255
     mfhi    $9
     mflo    $9
     move    $25, $1
     jrc     $9
     jr16    $9
     jalr    $9
     jalrs   $9
     jraddiusp 20