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[mips][microMIPS] Implement ADDIUS5 instruction
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Authored by jkolek on Aug 25 2014, 8:16 AM.

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Summary

Implement 16-bit microMIPS add immediate unsigned word 5-bit register select instruction - ADDIUS5.

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rL LLVM

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jkolek updated this revision to Diff 12901.Aug 25 2014, 8:16 AM
jkolek retitled this revision from to [mips][microMIPS] Implement ADDIUS5 instruction.
jkolek updated this object.
jkolek edited the test plan for this revision. (Show Details)
jkolek added reviewers: dsanders, vmedic.
jkolek added a subscriber: zoran.jovanovic.
jkolek updated this revision to Diff 14105.Sep 26 2014, 5:11 AM
jkolek added a reviewer: sstankovic.
sstankovic added inline comments.Sep 29 2014, 4:11 AM
lib/Target/Mips/MicroMipsInstrInfo.td
13 ↗(On Diff #14105)

I think that you don't need to define EncoderMethod, because this method (getSImm5Addius5Value) only truncates operand to 4 bits. The pattern for this operand (which I suppose will be added in one of the future patches) will ensure that operand is 4 bits.

test/MC/Mips/micromips-16-bit-instructions.s
12 ↗(On Diff #14105)

You should also check whether the error messages are issued when the operand is out of range.

jkolek updated this revision to Diff 14161.Sep 29 2014, 6:27 AM

Removed encoder method and added check for invalid instruction operand.

sstankovic accepted this revision.Oct 1 2014, 7:14 AM
sstankovic edited edge metadata.
This revision is now accepted and ready to land.Oct 1 2014, 7:14 AM
Diffusion closed this revision.Oct 10 2014, 6:55 AM
Diffusion updated this revision to Diff 14723.

Closed by commit rL219495 (authored by zjovanovic).

jkolek edited edge metadata.Nov 18 2014, 5:56 AM
jkolek added a subscriber: Unknown Object (MLST).