use an integer constant for FABS / FNEG (x86)

[spatel]

Summary

This patch is just a bit of cleanup to ease refactoring LowerFABS() and LowerFNEG() since they have a lot of overlap.

I've removed the creation of a floating point constant from an integer because it's going to be used for a bitwise integer op anyway.

I don't intend for this to make any difference to codegen, and AFAICT there isn't. There's no difference in test-suite either.

[spatel]

Updated to use APInt::getSignBit() - no need to mess around with bit shifting here.

[majnemer]

lib/Target/X86/X86ISelLowering.cpp

12124 ↗

(On Diff #12916)

I think you can replace ~APInt::getSignBit(EltBits) with APInt::getSignedMaxValue(EltBits)

[spatel]

Updated to use APInt::getSignedMaxValue() - thanks, David!

[spatel]

Ok to commit?

[spatel]

Ping.

I think it would be ok to commit this small change, but the dev policy page (code review rule #5) says that I need an explicit LGTM because I posted this as a patch for review. Please let me know if I'm misunderstanding the rules.

[spatel]

Closed by commit rL216889 (authored by @spatel).

[spatel]

Thanks, Andrea! Committed at r216889.

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
   SDLoc dl(Op);
   MVT VT = Op.getSimpleValueType();
   MVT EltVT = VT;
   unsigned NumElts = VT == MVT::f64 ? 2 : 4;
   if (VT.isVector()) {
     EltVT = VT.getVectorElementType();
     NumElts = VT.getVectorNumElements();
   }
-  Constant *C;
-  if (EltVT == MVT::f64)
-    C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
-                                          APInt(64, ~(1ULL << 63))));
-  else
-    C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
-                                          APInt(32, ~(1U << 31))));
+
+  unsigned EltBits = EltVT.getSizeInBits();
+  Constant *C = ConstantInt::get(*Context, APInt::getSignedMaxValue(EltBits));
   C = ConstantVector::getSplat(NumElts, C);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
   unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
   SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
                              MachinePointerInfo::getConstantPool(),
                              false, false, false, Alignment);
   if (VT.isVector()) {
static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
   SDLoc dl(Op);
   MVT VT = Op.getSimpleValueType();
   MVT EltVT = VT;
   unsigned NumElts = VT == MVT::f64 ? 2 : 4;
   if (VT.isVector()) {
     EltVT = VT.getVectorElementType();
     NumElts = VT.getVectorNumElements();
   }
-  Constant *C;
-  if (EltVT == MVT::f64)
-    C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
-                                          APInt(64, 1ULL << 63)));
-  else
-    C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
-                                          APInt(32, 1U << 31)));
+  
+  unsigned EltBits = EltVT.getSizeInBits();
+  Constant *C = ConstantInt::get(*Context, APInt::getSignBit(EltBits));
   C = ConstantVector::getSplat(NumElts, C);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
   unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
   SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
                              MachinePointerInfo::getConstantPool(),
                              false, false, false, Alignment);
   if (VT.isVector()) {