[InstCombine] Optimize redundant 'signed truncation check pattern'.

[lebedev.ri]

Summary

This comes with Implicit Conversion Sanitizer - integer sign change (D50250):

signed char test(unsigned int x) { return x; }

clang++ -fsanitize=implicit-conversion -S -emit-llvm -o - /tmp/test.cpp -O3

• Old:
  old.ll2 KBDownload
• With this patch:
  new.ll2 KBDownload

General pattern:

X & Y

Where Y is checking that all the high bits (covered by a mask 4294967168)
are uniform, i.e. %arg & 4294967168 can be either 4294967168 or 0
Pattern can be one of:

%t = add        i32 %arg,    128
%r = icmp   ult i32 %t,      256

Or

%t0 = shl       i32 %arg,    24
%t1 = ashr      i32 %t0,     24
%r  = icmp  eq  i32 %t1,     %arg

Or

%t0 = trunc     i32 %arg  to i8
%t1 = sext      i8  %t0   to i32
%r  = icmp  eq  i32 %t1,     %arg

This pattern is a signed truncation check.

And X is checking that some bit in that same mask is zero.
I.e. can be one of:

%r = icmp sgt i32   %arg,    -1

Or

%t = and      i32   %arg,    2147483648
%r = icmp eq  i32   %t,      0

Since we are checking that all the bits in that mask are the same,
and a particular bit is zero, what we are really checking is that all the
masked bits are zero.
So this should be transformed to:

%r = icmp ult i32 %arg, 128

The transform itself ended up being rather horrible, even though i omitted some cases.
Surely there is some infrastructure that can help clean this up that i missed?

https://rise4fun.com/Alive/3Ou

[lebedev.ri]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1404

@RKSimon: if i don't set a name here, the utils/update_test_checks.py goes mad,
and produces strange (wrong) check-lines:

$ ninja check-llvm-transforms-instcombine -v
[0/1] cd /build/llvm-build-GCC-release/test && /usr/bin/python2.7 /build/llvm-build-GCC-release/./bin/llvm-lit -sv /build/llvm/test/Transforms/InstCombine
FAIL: LLVM :: Transforms/InstCombine/signed-truncation-check.ll (696 of 824)
******************** TEST 'LLVM :: Transforms/InstCombine/signed-truncation-check.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   /build/llvm-build-GCC-release/bin/opt < /build/llvm/test/Transforms/InstCombine/signed-truncation-check.ll -instcombine -S | /build/llvm-build-GCC-release/bin/FileCheck /build/llvm/test/Transforms/InstCombine/signed-truncation-check.ll
--
Exit Code: 1

Command Output (stderr):
--
/build/llvm/test/Transforms/InstCombine/signed-truncation-check.ll:281:15: error: CHECK-NEXT: expected string not found in input
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i16 [[TMP1]], 128
              ^
<stdin>:114:2: note: scanning from here
 %1 = icmp ult i16 %tmp1, 128
 ^

--

********************
Testing Time: 5.48s
********************
Failing Tests (1):
    LLVM :: Transforms/InstCombine/signed-truncation-check.ll

  Expected Passes    : 808
  Unsupported Tests  : 15
  Unexpected Failures: 1
FAILED: test/CMakeFiles/check-llvm-transforms-instcombine 
cd /build/llvm-build-GCC-release/test && /usr/bin/python2.7 /build/llvm-build-GCC-release/./bin/llvm-lit -sv /build/llvm/test/Transforms/InstCombine
ninja: build stopped: subcommand failed.

[spatel]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1404

Independent of this patch: the script uses "TMP###" as the substitute for unnamed (%###) values. So if a test already has values named "%tmp###", things will likely go wrong. The quick fix is to replace all of the "%tmp###" names in these tests with "%t###" (or anything other than "%tmp###").

[lebedev.ri]

Ping.

[spatel]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1307–1308

It's better to include the comment from the test file directly (or at least a shorter description) instead of asking the reader to jump to another file for documentation.

1311–1316

Can this be moved within InstCombiner::foldAndOfICmps() to eliminate these preliminary checks?

Any chance for shared functionality with foldAndOrOfICmpsOfAndWithPow2() or simplifyRangeCheck()?

[lebedev.ri]

Rebased ontop of committed tests, NFC.

[lebedev.ri]

Sink the call down into InstCombiner::foldAndOfICmps().

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1311–1316

I don't think i should squeeze it into InstCombiner::foldAndOrOfICmpsOfAndWithPow2(),
as that looks for a *very* specific, different pattern.

InstCombiner::simplifyRangeCheck() also does not look too promising,
we will then only handle the extreme cases (which is, admittedly, probably
sufficient for my needs right now), but not the general case :/

None of those handle this case because they mostly require for the both icmp's
to operate on the same value, and don't understand what

%t = add        i32 %arg,    128
%r = icmp   ult i32 %t,      256

(and similar patterns) mean.

So i have sunk it down into InstCombiner::foldAndOfICmps() for now..

[spatel]

LGTM.

About the autogen script problem - we could hack that to use something less likely than 'TMP' as its regex string (eg, 'AUTOGEN'), but that will result in significant test file churn if someone updates an existing file.

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1311–1316

Ok, thanks for checking. I think we've noted this before - the whole thing is a complicated mess, and there should be some better way to generalize it, but it's not clear how to do it.

[lebedev.ri]

Thank you for taking a look!

In D50465#1197796, @spatel wrote:

LGTM.

(i'm not sure if you've meant to accept this, because you have only posted the comment, not clicked 'accept')

To be noted, i still don't quite like this code, but i'm not sure how to improve this.

In D50465#1197796, @spatel wrote:

About the autogen script problem - we could hack that to use something less likely than 'TMP' as its regex string (eg, 'AUTOGEN'), but that will result in significant test file churn if someone updates an existing file.

Yeah... I think some note in the docs would be good-enough, too.

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1311–1316

Auto-generated (souper) tablegen-driven transforms would be The Solution :)
Else i suspect we'll be hitting missing corner cases and patterns for eternities to come.

[spatel]

Forgot to click 'Accept' here in Phab.

[lebedev.ri]

In D50465#1197824, @spatel wrote:

Forgot to click 'Accept' here in Phab.

Hmm, okay, thank you for the review!

[lebedev.ri]

Temporarily reverted.
That assert at the beginning is to greedy.

[lebedev.ri]

NFC, revert, just so the diffs are sane.

[lebedev.ri]

Test + less eager assert.
We can indeed do that fold: https://rise4fun.com/Alive/0lz

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

static Instruction *foldAndToXor(BinaryOperator &I,
   if (Op0->hasOneUse() || Op1->hasOneUse())
     if (match(&I, m_BinOp(m_c_Or(m_Value(A), m_Not(m_Value(B))),
                           m_c_Or(m_Not(m_Deferred(A)), m_Deferred(B)))))
       return BinaryOperator::CreateNot(Builder.CreateXor(A, B));
 
   return nullptr;
 }
 
+// See detailed explaination of the pattern in
+// test/Transforms/InstCombine/signed-truncation-check.ll
+static Value *foldSignedTruncationCheck(BinaryOperator &I,
+                                        InstCombiner::BuilderTy &Builder) {
+  assert(I.getOpcode() == Instruction::And);
+  // We are looking for an 'and' of two icmp's
+  auto *ICmp0 = dyn_cast<ICmpInst>(I.getOperand(0));
+  auto *ICmp1 = dyn_cast<ICmpInst>(I.getOperand(1));
+  if (!(ICmp0 && ICmp1))
+    return nullptr;
+
+  // Match  icmp ult (add %arg, C01), C1   (C1 == C01 << 1; powers of two)
+  auto tryToMatchSignedTruncationCheck = [](ICmpInst *ICmp, Value *&X,
+                                            APInt &SignBitMask) -> bool {
+    CmpInst::Predicate Pred;
+    const APInt *I01, *I1; // powers of two; I1 == I01 << 1
+    if (!(match(ICmp,
+                m_ICmp(Pred, m_Add(m_Value(X), m_Power2(I01)), m_Power2(I1))) &&
+          Pred == ICmpInst::ICMP_ULT && I1->ugt(*I01) && I01->shl(1) == *I1))
+      return false;
+    // Which bit is the new sign bit as per the 'signed truncation' pattern?
+    SignBitMask = *I01;
+    return true;
+  };
+
+  // One icmp needs to be 'signed truncation check'.
+  // We need to match this first, else we will mismatch commutative cases.
+  Value *X1;
+  APInt HighestBit;
+  ICmpInst *OtherICmp;
+  if (tryToMatchSignedTruncationCheck(ICmp1, X1, HighestBit))
+    OtherICmp = ICmp0;
+  else if (tryToMatchSignedTruncationCheck(ICmp0, X1, HighestBit))
+    OtherICmp = ICmp1;
+  else
+    return nullptr;
+
+  assert(HighestBit.isPowerOf2() && "expected to be power of two (non-zero)");
+
+  // Try to match/decompose into:  icmp eq (X & Mask), 0
+  auto tryToDecompose = [](ICmpInst *ICmp, Value *&X,
+                           APInt &UnsetBitsMask) -> bool {
+    CmpInst::Predicate Pred = ICmp->getPredicate();
+    // Can it be decomposed into  icmp eq (X & Mask), 0  ?
+    if (llvm::decomposeBitTestICmp(ICmp->getOperand(0), ICmp->getOperand(1),
+                                   Pred, X, UnsetBitsMask,
+                                   /*LookThruTrunc=*/false) &&
+        Pred == ICmpInst::ICMP_EQ)
+      return true;
+    // Is it  icmp eq (X & Mask), 0  already?
+    const APInt *Mask;
+    if (match(ICmp, m_ICmp(Pred, m_And(m_Value(X), m_APInt(Mask)), m_Zero())) &&
+        Pred == ICmpInst::ICMP_EQ) {
+      UnsetBitsMask = *Mask;
+      return true;
+    }
+    return false;
+  };
+
+  // And the other icmp needs to be decomposable into a bit test.
+  Value *X0;
+  APInt UnsetBitsMask;
+  if (!tryToDecompose(OtherICmp, X0, UnsetBitsMask))
+    return nullptr;
+
+  assert(!UnsetBitsMask.isNullValue() && "empty mask makes no sense.");
+
+  // Are they working on the same value?
+  Value *X;
+  if (X1 == X0) {
+    // Ok as is.
+    X = X1;
+  } else if (match(X0, m_Trunc(m_Specific(X1)))) {
+    UnsetBitsMask = UnsetBitsMask.zext(X1->getType()->getScalarSizeInBits());
+    X = X1;
+  } else
+    return nullptr;
+
+  // So which bits should be uniform as per the 'signed truncation check'?
+  // (all the bits starting with (i.e. including) HighestBit)
+  APInt SignBitsMask = ~(HighestBit - 1U);
+
+  // UnsetBitsMask must have some common bits with SignBitsMask,
+  if (!UnsetBitsMask.intersects(SignBitsMask))
+    return nullptr;
+
+  // Does UnsetBitsMask contain any bits outside of SignBitsMask?
+  if (!UnsetBitsMask.isSubsetOf(SignBitsMask)) {
+    APInt OtherHighestBit = (~UnsetBitsMask) + 1U;
+    if (!OtherHighestBit.isPowerOf2())
+      return nullptr;
+    HighestBit = APIntOps::umin(HighestBit, OtherHighestBit);
+  }
+  // Else, if it does not, then all is ok as-is.
+
+  // %r = icmp ult %X, SignBit
+  return Builder.CreateICmpULT(X, ConstantInt::get(X->getType(), HighestBit),
+                               I.getName() + ".simplified");
+}
+
 static Instruction *foldOrToXor(BinaryOperator &I,
                                 InstCombiner::BuilderTy &Builder) {
   assert(I.getOpcode() == Instruction::Or);
   Value *Op0 = I.getOperand(0);
   Value *Op1 = I.getOperand(1);
   Value *A, *B;
 
   // Operand complexity canonicalization guarantees that the 'and' is Op0.
Instruction *InstCombiner::visitAnd(BinaryOperator &I) {
   Value *A;
   if (match(Op0, m_OneUse(m_SExt(m_Value(A)))) &&
       A->getType()->isIntOrIntVectorTy(1))
     return SelectInst::Create(A, Op1, Constant::getNullValue(I.getType()));
   if (match(Op1, m_OneUse(m_SExt(m_Value(A)))) &&
       A->getType()->isIntOrIntVectorTy(1))
     return SelectInst::Create(A, Op0, Constant::getNullValue(I.getType()));
 
+  if (Value *NewICmp = foldSignedTruncationCheck(I, Builder))
+    return replaceInstUsesWith(I, NewICmp);
+
   return nullptr;
 }
 
 /// Given an OR instruction, check to see if this is a bswap idiom. If so,
 /// insert the new intrinsic and return it.
 Instruction *InstCombiner::MatchBSwap(BinaryOperator &I) {
   Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
 

test/Transforms/InstCombine/signed-truncation-check.ll

 ;   %r = icmp ult i32 %arg, 128
 
 ; ============================================================================ ;
 ; Basic positive test
 ; ============================================================================ ;
 
 define i1 @positive_with_signbit(i32 %arg) {
 ; CHECK-LABEL: @positive_with_signbit(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
-; CHECK-NEXT:    [[T2:%.*]] = add i32 [[ARG]], 128
-; CHECK-NEXT:    [[T3:%.*]] = icmp ult i32 [[T2]], 256
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
-; CHECK-NEXT:    ret i1 [[T4]]
+; CHECK-NEXT:    [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT:    ret i1 [[T4_SIMPLIFIED]]
 ;
   %t1 = icmp sgt i32 %arg, -1
   %t2 = add i32 %arg, 128
   %t3 = icmp ult i32 %t2, 256
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @positive_with_mask(i32 %arg) {
 ; CHECK-LABEL: @positive_with_mask(
-; CHECK-NEXT:    [[T1:%.*]] = and i32 [[ARG:%.*]], 1107296256
-; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
-; CHECK-NEXT:    [[T3:%.*]] = add i32 [[ARG]], 128
-; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[T3]], 256
-; CHECK-NEXT:    [[T5:%.*]] = and i1 [[T2]], [[T4]]
-; CHECK-NEXT:    ret i1 [[T5]]
+; CHECK-NEXT:    [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT:    ret i1 [[T5_SIMPLIFIED]]
 ;
   %t1 = and i32 %arg, 1107296256
   %t2 = icmp eq i32 %t1, 0
   %t3 = add i32 %arg, 128
   %t4 = icmp ult i32 %t3, 256
   %t5 = and i1 %t2, %t4
   ret i1 %t5
 }
 
 define i1 @positive_with_icmp(i32 %arg) {
 ; CHECK-LABEL: @positive_with_icmp(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[ARG:%.*]], 512
-; CHECK-NEXT:    [[T2:%.*]] = add i32 [[ARG]], 128
-; CHECK-NEXT:    [[T3:%.*]] = icmp ult i32 [[T2]], 256
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
-; CHECK-NEXT:    ret i1 [[T4]]
+; CHECK-NEXT:    [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT:    ret i1 [[T4_SIMPLIFIED]]
 ;
   %t1 = icmp ult i32 %arg, 512
   %t2 = add i32 %arg, 128
   %t3 = icmp ult i32 %t2, 256
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 ; Still the same
 define i1 @positive_with_aggressive_icmp(i32 %arg) {
 ; CHECK-LABEL: @positive_with_aggressive_icmp(
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[ARG:%.*]], 128
-; CHECK-NEXT:    [[T2:%.*]] = add i32 [[ARG]], 256
-; CHECK-NEXT:    [[T3:%.*]] = icmp ult i32 [[T2]], 512
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
-; CHECK-NEXT:    ret i1 [[T4]]
+; CHECK-NEXT:    [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT:    ret i1 [[T4_SIMPLIFIED]]
 ;
   %t1 = icmp ult i32 %arg, 128
   %t2 = add i32 %arg, 256
   %t3 = icmp ult i32 %t2, 512
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 ; I'm sure there is a bunch more patterns possible :/
 
 ; ============================================================================ ;
 ; Vector tests
 ; ============================================================================ ;
 
 define <2 x i1> @positive_vec_splat(<2 x i32> %arg) {
 ; CHECK-LABEL: @positive_vec_splat(
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt <2 x i32> [[ARG:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[T2:%.*]] = add <2 x i32> [[ARG]], <i32 128, i32 128>
-; CHECK-NEXT:    [[T3:%.*]] = icmp ult <2 x i32> [[T2]], <i32 256, i32 256>
-; CHECK-NEXT:    [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]
-; CHECK-NEXT:    ret <2 x i1> [[T4]]
+; CHECK-NEXT:    [[T4_SIMPLIFIED:%.*]] = icmp ult <2 x i32> [[ARG:%.*]], <i32 128, i32 128>
+; CHECK-NEXT:    ret <2 x i1> [[T4_SIMPLIFIED]]
 ;
   %t1 = icmp sgt <2 x i32> %arg, <i32 -1, i32 -1>
   %t2 = add <2 x i32> %arg, <i32 128, i32 128>
   %t3 = icmp ult <2 x i32> %t2, <i32 256, i32 256>
   %t4 = and <2 x i1> %t1, %t3
   ret <2 x i1> %t4
 }
 

 ; Commutativity tests.
 ; ============================================================================ ;
 
 declare i32 @gen32()
 
 define i1 @commutative() {
 ; CHECK-LABEL: @commutative(
 ; CHECK-NEXT:    [[ARG:%.*]] = call i32 @gen32()
-; CHECK-NEXT:    [[T1:%.*]] = icmp sgt i32 [[ARG]], -1
-; CHECK-NEXT:    [[T2:%.*]] = add i32 [[ARG]], 128
-; CHECK-NEXT:    [[T3:%.*]] = icmp ult i32 [[T2]], 256
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T3]], [[T1]]
-; CHECK-NEXT:    ret i1 [[T4]]
+; CHECK-NEXT:    [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
+; CHECK-NEXT:    ret i1 [[T4_SIMPLIFIED]]
 ;
   %arg = call i32 @gen32()
   %t1 = icmp sgt i32 %arg, -1
   %t2 = add i32 %arg, 128
   %t3 = icmp ult i32 %t2, 256
   %t4 = and i1 %t3, %t1 ; swapped order
   ret i1 %t4
 }
 
 define i1 @commutative_with_icmp() {
 ; CHECK-LABEL: @commutative_with_icmp(
 ; CHECK-NEXT:    [[ARG:%.*]] = call i32 @gen32()
-; CHECK-NEXT:    [[T1:%.*]] = icmp ult i32 [[ARG]], 512
-; CHECK-NEXT:    [[T2:%.*]] = add i32 [[ARG]], 128
-; CHECK-NEXT:    [[T3:%.*]] = icmp ult i32 [[T2]], 256
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T3]], [[T1]]
-; CHECK-NEXT:    ret i1 [[T4]]
+; CHECK-NEXT:    [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
+; CHECK-NEXT:    ret i1 [[T4_SIMPLIFIED]]
 ;
   %arg = call i32 @gen32()
   %t1 = icmp ult i32 %arg, 512
   %t2 = add i32 %arg, 128
   %t3 = icmp ult i32 %t2, 256
   %t4 = and i1 %t3, %t1 ; swapped order
   ret i1 %t4
 }
 
 ; ============================================================================ ;
 ; Truncations.
 ; ============================================================================ ;
 
 define i1 @positive_trunc_signbit(i32 %arg) {
 ; CHECK-LABEL: @positive_trunc_signbit(
-; CHECK-NEXT:    [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
-; CHECK-NEXT:    [[T2:%.*]] = icmp sgt i8 [[T1]], -1
-; CHECK-NEXT:    [[T3:%.*]] = add i32 [[ARG]], 128
-; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[T3]], 256
-; CHECK-NEXT:    [[T5:%.*]] = and i1 [[T2]], [[T4]]
-; CHECK-NEXT:    ret i1 [[T5]]
+; CHECK-NEXT:    [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT:    ret i1 [[T5_SIMPLIFIED]]
 ;
   %t1 = trunc i32 %arg to i8
   %t2 = icmp sgt i8 %t1, -1
   %t3 = add i32 %arg, 128
   %t4 = icmp ult i32 %t3, 256
   %t5 = and i1 %t2, %t4
   ret i1 %t5
 }
 
 define i1 @positive_trunc_base(i32 %arg) {
 ; CHECK-LABEL: @positive_trunc_base(
 ; CHECK-NEXT:    [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i16
-; CHECK-NEXT:    [[T2:%.*]] = icmp sgt i16 [[T1]], -1
-; CHECK-NEXT:    [[T3:%.*]] = add i16 [[T1]], 128
-; CHECK-NEXT:    [[T4:%.*]] = icmp ult i16 [[T3]], 256
-; CHECK-NEXT:    [[T5:%.*]] = and i1 [[T2]], [[T4]]
-; CHECK-NEXT:    ret i1 [[T5]]
+; CHECK-NEXT:    [[T5_SIMPLIFIED:%.*]] = icmp ult i16 [[T1]], 128
+; CHECK-NEXT:    ret i1 [[T5_SIMPLIFIED]]
 ;
   %t1 = trunc i32 %arg to i16
   %t2 = icmp sgt i16 %t1, -1
   %t3 = add i16 %t1, 128
   %t4 = icmp ult i16 %t3, 256
   %t5 = and i1 %t2, %t4
   ret i1 %t5
 }

 define i1 @oneuse_with_signbit(i32 %arg) {
 ; CHECK-LABEL: @oneuse_with_signbit(
 ; CHECK-NEXT:    [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
 ; CHECK-NEXT:    call void @use1(i1 [[T1]])
 ; CHECK-NEXT:    [[T2:%.*]] = add i32 [[ARG]], 128
 ; CHECK-NEXT:    call void @use32(i32 [[T2]])
 ; CHECK-NEXT:    [[T3:%.*]] = icmp ult i32 [[T2]], 256
 ; CHECK-NEXT:    call void @use1(i1 [[T3]])
-; CHECK-NEXT:    [[T4:%.*]] = and i1 [[T1]], [[T3]]
-; CHECK-NEXT:    ret i1 [[T4]]
+; CHECK-NEXT:    [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
+; CHECK-NEXT:    ret i1 [[T4_SIMPLIFIED]]
 ;
   %t1 = icmp sgt i32 %arg, -1
   call void @use1(i1 %t1)
   %t2 = add i32 %arg, 128
   call void @use32(i32 %t2)
   %t3 = icmp ult i32 %t2, 256
   call void @use1(i1 %t3)
   %t4 = and i1 %t1, %t3
   ret i1 %t4
 }
 
 define i1 @oneuse_with_mask(i32 %arg) {
 ; CHECK-LABEL: @oneuse_with_mask(
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[ARG:%.*]], 603979776
 ; CHECK-NEXT:    call void @use32(i32 [[T1]])
 ; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
 ; CHECK-NEXT:    call void @use1(i1 [[T2]])
 ; CHECK-NEXT:    [[T3:%.*]] = add i32 [[ARG]], 128
 ; CHECK-NEXT:    call void @use32(i32 [[T3]])
 ; CHECK-NEXT:    [[T4:%.*]] = icmp ult i32 [[T3]], 256
 ; CHECK-NEXT:    call void @use1(i1 [[T4]])
-; CHECK-NEXT:    [[T5:%.*]] = and i1 [[T2]], [[T4]]
-; CHECK-NEXT:    ret i1 [[T5]]
+; CHECK-NEXT:    [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
+; CHECK-NEXT:    ret i1 [[T5_SIMPLIFIED]]
 ;
   %t1 = and i32 %arg, 603979776 ; some bit within the target 4294967168 mask.
   call void @use32(i32 %t1)
   %t2 = icmp eq i32 %t1, 0
   call void @use1(i1 %t2)
   %t3 = add i32 %arg, 128
   call void @use32(i32 %t3)
   %t4 = icmp ult i32 %t3, 256