[WebAssembly] Update SIMD binary arithmetic

[tlively]

Summary

Add missing SIMD types (v2i64 and v2f64) and binary ops. Also adds
tablegen support for automatically prepending prefix byte to SIMD
opcodes. Replaces individual vector ExprTypes with a single V128 type.

[aheejin]

Looks OK with some formatting nits

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

261

Can you clang-format this?

lib/Target/WebAssembly/WebAssemblyInstrFormats.td

63

Nit: space between simdop and =

lib/Target/WebAssembly/WebAssemblyRegisterInfo.td

66

Wrap to 80 cols?

[dschuff]

lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp

214

Replacing the ExprType is not related to the rest of this CL, so it should probably be split into a separate CL.

test/CodeGen/WebAssembly/simd-arith.ll

150

missing div?

[tlively]

• Formatting in .td files

[tlively]

Landed rL339082 to address comments.

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

261

Done in https://reviews.llvm.org/D50367.

test/CodeGen/WebAssembly/simd-arith.ll

150

SIMD integer div ops are not in the spec

[tlively]

• Formatting in .td files
• Remove i64x2.mul since it is not in spec

[tlively]

• Revert "Remove i64x2.mul since it is not in spec." It is unclear this

[dschuff]

Keeping MUL is fine for now. IIRC there was some discussion in the last CG in-person meeting about removing or changing it (e.g. probably not super-useful especially for small types due to the likelihood of overflow). Probably in cases where the spec is still in flux it makes sense for LLVM to match what V8 implements now, so we can test things end-to-end. Then when we settle on things we can just change LLVM (or do LLVM first to see whether a proposal is feasible).

lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp

void WebAssemblyInstPrinter::printWebAssemblySignatureOperand(
     const MCInst *MI, unsigned OpNo, raw_ostream &O) {
   int64_t Imm = MI->getOperand(OpNo).getImm();
   switch (WebAssembly::ExprType(Imm)) {
   case WebAssembly::ExprType::Void: break;
   case WebAssembly::ExprType::I32: O << "i32"; break;
   case WebAssembly::ExprType::I64: O << "i64"; break;
   case WebAssembly::ExprType::F32: O << "f32"; break;
   case WebAssembly::ExprType::F64: O << "f64"; break;
-  case WebAssembly::ExprType::I8x16: O << "i8x16"; break;
-  case WebAssembly::ExprType::I16x8: O << "i16x8"; break;
-  case WebAssembly::ExprType::I32x4: O << "i32x4"; break;
-  case WebAssembly::ExprType::F32x4: O << "f32x4"; break;
-  case WebAssembly::ExprType::B8x16: O << "b8x16"; break;
-  case WebAssembly::ExprType::B16x8: O << "b16x8"; break;
-  case WebAssembly::ExprType::B32x4: O << "b32x4"; break;
+  case WebAssembly::ExprType::V128: O << "v128"; break;
   case WebAssembly::ExprType::ExceptRef: O << "except_ref"; break;
   }
 }
 
 const char *llvm::WebAssembly::TypeToString(MVT Ty) {
   switch (Ty.SimpleTy) {
   case MVT::i32:
     return "i32";
   case MVT::i64:
     return "i64";
   case MVT::f32:
     return "f32";
   case MVT::f64:
     return "f64";
   case MVT::v16i8:
   case MVT::v8i16:
   case MVT::v4i32:
+  case MVT::v2i64:
   case MVT::v4f32:
+  case MVT::v2f64:
     return "v128";
   case MVT::ExceptRef:
     return "except_ref";
   default:
     llvm_unreachable("unsupported type");
   }
 }
 

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

 
 /// This is used to indicate block signatures.
 enum class ExprType : unsigned {
   Void      = 0x40,
   I32       = 0x7F,
   I64       = 0x7E,
   F32       = 0x7D,
   F64       = 0x7C,
-  I8x16     = 0x7B,
-  I16x8     = 0x7A,
-  I32x4     = 0x79,
-  F32x4     = 0x78,
-  B8x16     = 0x77,
-  B16x8     = 0x76,
-  B32x4     = 0x75,
+  V128      = 0x7B,
   ExceptRef = 0x68
 };
 
 /// Instruction opcodes emitted via means other than CodeGen.
 static const unsigned Nop = 0x01;
 static const unsigned End = 0x0b;
 
 wasm::ValType toValType(const MVT &Ty);
 
 } // end namespace WebAssembly
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

 //===----------------------------------------------------------------------===//
 // Helpers.
 //===----------------------------------------------------------------------===//
 
 MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const {
   const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
   const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
   for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
-                MVT::v4i32, MVT::v4f32})
+                MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
     if (TRI->isTypeLegalForClass(*TRC, T))
       return T;
   LLVM_DEBUG(errs() << "Unknown type for register number: " << RegNo);
   llvm_unreachable("Unknown register type");
   return MVT::Other;
 }
 
 std::string WebAssemblyAsmPrinter::regToString(const MachineOperand &MO) {
void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   switch (MI->getOpcode()) {
   case WebAssembly::ARGUMENT_I32:
   case WebAssembly::ARGUMENT_I64:
   case WebAssembly::ARGUMENT_F32:
   case WebAssembly::ARGUMENT_F64:
   case WebAssembly::ARGUMENT_v16i8:
   case WebAssembly::ARGUMENT_v8i16:
   case WebAssembly::ARGUMENT_v4i32:
+  case WebAssembly::ARGUMENT_v2i64:
   case WebAssembly::ARGUMENT_v4f32:
+  case WebAssembly::ARGUMENT_v2f64:
     // These represent values which are live into the function entry, so there's
     // no instruction to emit.
     break;
   case WebAssembly::FALLTHROUGH_RETURN_I32:
   case WebAssembly::FALLTHROUGH_RETURN_I64:
   case WebAssembly::FALLTHROUGH_RETURN_F32:
   case WebAssembly::FALLTHROUGH_RETURN_F64:
   case WebAssembly::FALLTHROUGH_RETURN_v16i8:
   case WebAssembly::FALLTHROUGH_RETURN_v8i16:
   case WebAssembly::FALLTHROUGH_RETURN_v4i32:
-  case WebAssembly::FALLTHROUGH_RETURN_v4f32: {
+  case WebAssembly::FALLTHROUGH_RETURN_v2i64:
+  case WebAssembly::FALLTHROUGH_RETURN_v4f32:
+  case WebAssembly::FALLTHROUGH_RETURN_v2f64: {
     // These instructions represent the implicit return at the end of a
     // function body. The operand is always a pop.
     assert(MFI->isVRegStackified(MI->getOperand(0).getReg()));
 
     if (isVerbose()) {
       OutStreamer->AddComment("fallthrough-return: $pop" +
                               Twine(MFI->getWARegStackId(
                                   MFI->getWAReg(MI->getOperand(0).getReg()))));

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

if (MFI.getResults().empty())
     return;
 
   WebAssembly::ExprType retType;
   switch (MFI.getResults().front().SimpleTy) {
   case MVT::i32: retType = WebAssembly::ExprType::I32; break;
   case MVT::i64: retType = WebAssembly::ExprType::I64; break;
   case MVT::f32: retType = WebAssembly::ExprType::F32; break;
   case MVT::f64: retType = WebAssembly::ExprType::F64; break;
-  case MVT::v16i8: retType = WebAssembly::ExprType::I8x16; break;
-  case MVT::v8i16: retType = WebAssembly::ExprType::I16x8; break;
-  case MVT::v4i32: retType = WebAssembly::ExprType::I32x4; break;
-  case MVT::v4f32: retType = WebAssembly::ExprType::F32x4; break;
+  case MVT::v16i8:
+  case MVT::v8i16:
+  case MVT::v4i32:
+  case MVT::v2i64:
+  case MVT::v4f32:
+  case MVT::v2f64: retType = WebAssembly::ExprType::V128; break;
   case MVT::ExceptRef: retType = WebAssembly::ExprType::ExceptRef; break;
   default: llvm_unreachable("unexpected return type");
   }
 
   for (MachineBasicBlock &MBB : reverse(MF)) {
     for (MachineInstr &MI : reverse(MBB)) {
       if (MI.isPosition() || MI.isDebugInstr())
         continue;

lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp

static unsigned GetNonPseudoCallIndirectOpcode(const MachineInstr &MI) {
   case PCALL_INDIRECT_VOID: return CALL_INDIRECT_VOID;
   case PCALL_INDIRECT_I32: return CALL_INDIRECT_I32;
   case PCALL_INDIRECT_I64: return CALL_INDIRECT_I64;
   case PCALL_INDIRECT_F32: return CALL_INDIRECT_F32;
   case PCALL_INDIRECT_F64: return CALL_INDIRECT_F64;
   case PCALL_INDIRECT_v16i8: return CALL_INDIRECT_v16i8;
   case PCALL_INDIRECT_v8i16: return CALL_INDIRECT_v8i16;
   case PCALL_INDIRECT_v4i32: return CALL_INDIRECT_v4i32;
+  case PCALL_INDIRECT_v2i64: return CALL_INDIRECT_v2i64;
   case PCALL_INDIRECT_v4f32: return CALL_INDIRECT_v4f32;
+  case PCALL_INDIRECT_v2f64: return CALL_INDIRECT_v2f64;
   default: return INSTRUCTION_LIST_END;
   }
 }
 
 static bool IsPseudoCallIndirect(const MachineInstr &MI) {
   return GetNonPseudoCallIndirectOpcode(MI) !=
          WebAssembly::INSTRUCTION_LIST_END;
 }
for (MachineInstr &MI : MBB) {
       }
     }
   }
 
   LLVM_DEBUG(dbgs() << "\nDone fixing up CALL_INDIRECTs\n\n");
 
   return Changed;
 }
-

lib/Target/WebAssembly/WebAssemblyFastISel.cpp

MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
     case MVT::f64:
     case MVT::ExceptRef:
       return VT;
     case MVT::f16:
       return MVT::f32;
     case MVT::v16i8:
     case MVT::v8i16:
     case MVT::v4i32:
+    case MVT::v2i64:
     case MVT::v4f32:
+    case MVT::v2f64:
       if (Subtarget->hasSIMD128())
         return VT;
       break;
     default:
       break;
     }
     return MVT::INVALID_SIMPLE_VALUE_TYPE;
   }
for (auto const &Arg : F->args()) {
     case MVT::v8i16:
       Opc = WebAssembly::ARGUMENT_v8i16;
       RC = &WebAssembly::V128RegClass;
       break;
     case MVT::v4i32:
       Opc = WebAssembly::ARGUMENT_v4i32;
       RC = &WebAssembly::V128RegClass;
       break;
+    case MVT::v2i64:
+      Opc = WebAssembly::ARGUMENT_v2i64;
+      RC = &WebAssembly::V128RegClass;
+      break;
     case MVT::v4f32:
       Opc = WebAssembly::ARGUMENT_v4f32;
       RC = &WebAssembly::V128RegClass;
       break;
+    case MVT::v2f64:
+      Opc = WebAssembly::ARGUMENT_v2f64;
+      RC = &WebAssembly::V128RegClass;
+      break;
     case MVT::ExceptRef:
       Opc = WebAssembly::ARGUMENT_EXCEPT_REF;
       RC = &WebAssembly::EXCEPT_REFRegClass;
       break;
     default:
       return false;
     }
     unsigned ResultReg = createResultReg(RC);
case MVT::v8i16:
           IsDirect ? WebAssembly::CALL_v8i16 : WebAssembly::PCALL_INDIRECT_v8i16;
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
     case MVT::v4i32:
       Opc =
           IsDirect ? WebAssembly::CALL_v4i32 : WebAssembly::PCALL_INDIRECT_v4i32;
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
+    case MVT::v2i64:
+      Opc =
+          IsDirect ? WebAssembly::CALL_v2i64 : WebAssembly::PCALL_INDIRECT_v2i64;
+      ResultReg = createResultReg(&WebAssembly::V128RegClass);
+      break;
     case MVT::v4f32:
       Opc =
           IsDirect ? WebAssembly::CALL_v4f32 : WebAssembly::PCALL_INDIRECT_v4f32;
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
+    case MVT::v2f64:
+      Opc =
+          IsDirect ? WebAssembly::CALL_v2f64 : WebAssembly::PCALL_INDIRECT_v2f64;
+      ResultReg = createResultReg(&WebAssembly::V128RegClass);
+      break;
     case MVT::ExceptRef:
       Opc = IsDirect ? WebAssembly::CALL_EXCEPT_REF
                      : WebAssembly::PCALL_INDIRECT_EXCEPT_REF;
       ResultReg = createResultReg(&WebAssembly::EXCEPT_REFRegClass);
       break;
     default:
       return false;
     }
case MVT::v16i8:
     Opc = WebAssembly::RETURN_v16i8;
     break;
   case MVT::v8i16:
     Opc = WebAssembly::RETURN_v8i16;
     break;
   case MVT::v4i32:
     Opc = WebAssembly::RETURN_v4i32;
     break;
+  case MVT::v2i64:
+    Opc = WebAssembly::RETURN_v2i64;
+    break;
   case MVT::v4f32:
     Opc = WebAssembly::RETURN_v4f32;
     break;
+  case MVT::v2f64:
+    Opc = WebAssembly::RETURN_v2f64;
+    break;
   case MVT::ExceptRef:
     Opc = WebAssembly::RETURN_EXCEPT_REF;
     break;
   default: return false;
   }
 
   unsigned Reg;
   if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::SExt))

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

WebAssemblyTargetLowering::WebAssemblyTargetLowering(
   addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
   addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
   addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
   addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
   if (Subtarget->hasSIMD128()) {
     addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
+    addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
+    addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
   }
   // Compute derived properties from the register classes.
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
   setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
   setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
   setOperationAction(ISD::JumpTable, MVTPtr, Custom);
   setOperationAction(ISD::BlockAddress, MVTPtr, Custom);

lib/Target/WebAssembly/WebAssemblyInstrCall.td

let Uses = [SP32, SP64], isCall = 1 in {
   defm "" : CALL<I32, "i32.">;
   defm "" : CALL<I64, "i64.">;
   defm "" : CALL<F32, "f32.">;
   defm "" : CALL<F64, "f64.">;
   defm "" : CALL<EXCEPT_REF, "except_ref.">;
   defm "" : SIMD_CALL<v16i8, "i8x16.">;
   defm "" : SIMD_CALL<v8i16, "i16x8.">;
   defm "" : SIMD_CALL<v4i32, "i32x4.">;
+  defm "" : SIMD_CALL<v2i64, "i64x2.">;
   defm "" : SIMD_CALL<v4f32, "f32x4.">;
+  defm "" : SIMD_CALL<v2f64, "f64x2.">;
 
   defm CALL_VOID : I<(outs), (ins function32_op:$callee, variable_ops),
                      (outs), (ins function32_op:$callee),
                      [(WebAssemblycall0 (i32 imm:$callee))],
                      "call    \t$callee", "call\t$callee", 0x10>;
 
   let isCodeGenOnly = 1 in {
     defm PCALL_INDIRECT_VOID : I<(outs), (ins I32:$callee, variable_ops),

 def : Pat<(f64 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_F64 tglobaladdr:$callee)>;
 def : Pat<(v16i8 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_v16i8 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v8i16 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_v8i16 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v4i32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_v4i32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
+def : Pat<(v2i64 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
+          (CALL_v2i64 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_v4f32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
+def : Pat<(v2f64 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
+          (CALL_v2f64 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(ExceptRef
            (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
           (CALL_EXCEPT_REF tglobaladdr:$callee)>;
 def : Pat<(WebAssemblycall0 (WebAssemblywrapper tglobaladdr:$callee)),
           (CALL_VOID tglobaladdr:$callee)>;
 
 // Patterns for matching a direct call to an external symbol.
 def : Pat<(i32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_I32 texternalsym:$callee)>;
 def : Pat<(i64 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_I64 texternalsym:$callee)>;
 def : Pat<(f32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_F32 texternalsym:$callee)>;
 def : Pat<(f64 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_F64 texternalsym:$callee)>;
 def : Pat<(v16i8 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_v16i8 texternalsym:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v8i16 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_v8i16 texternalsym:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v4i32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_v4i32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
+def : Pat<(v2i64 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
+          (CALL_v2i64 texternalsym:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_v4f32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
+def : Pat<(v2f64 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
+          (CALL_v2f64 texternalsym:$callee)>, Requires<[HasSIMD128]>;
 def : Pat<(ExceptRef
            (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
           (CALL_EXCEPT_REF texternalsym:$callee)>;
 def : Pat<(WebAssemblycall0 (WebAssemblywrapper texternalsym:$callee)),
           (CALL_VOID texternalsym:$callee)>;

lib/Target/WebAssembly/WebAssemblyInstrControl.td

let isReturn = 1 in {
   defm "": RETURN<I32>;
   defm "": RETURN<I64>;
   defm "": RETURN<F32>;
   defm "": RETURN<F64>;
   defm "": RETURN<EXCEPT_REF>;
   defm "": SIMD_RETURN<v16i8>;
   defm "": SIMD_RETURN<v8i16>;
   defm "": SIMD_RETURN<v4i32>;
+  defm "": SIMD_RETURN<v2i64>;
   defm "": SIMD_RETURN<v4f32>;
+  defm "": SIMD_RETURN<v2f64>;
 
   defm RETURN_VOID : NRI<(outs), (ins), [(WebAssemblyreturn)], "return", 0x0f>;
 
   // This is to RETURN_VOID what FALLTHROUGH_RETURN_#vt is to RETURN_#vt.
   let isCodeGenOnly = 1 in
   defm FALLTHROUGH_RETURN_VOID : NRI<(outs), (ins), []>;
 } // isReturn = 1
 

lib/Target/WebAssembly/WebAssemblyInstrFormats.td

 // For instructions that have no register ops, so both sets are the same.
 multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
                bits<32> inst = -1> {
   defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
 }
 
 multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
                   list<dag> pattern_r, string asmstr_r = "",
-                  string asmstr_s = "", bits<32> inst = -1> {
+                  string asmstr_s = "", bits<32> simdop= -1> {
   defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
-              inst>,
+              !or(0xfd00, !and(0xff, simdop))>,
             Requires<[HasSIMD128]>;
 }
 
 multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
                     list<dag> pattern_r, string asmstr_r = "",
                     string asmstr_s = "", bits<32> inst = -1> {
   defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
               inst>,
defm _F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
                 [(set F32:$dst, (node F32:$lhs, F32:$rhs))],
                 !strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
                 !strconcat("f32.", name), f32Inst>;
   defm _F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs), (outs), (ins),
                 [(set F64:$dst, (node F64:$lhs, F64:$rhs))],
                 !strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
                 !strconcat("f64.", name), f64Inst>;
 }
-multiclass SIMDBinary<SDNode node, SDNode fnode, string name> {
+multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
   defm _I8x16 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
                        (outs), (ins),
                        [(set (v16i8 V128:$dst), (node V128:$lhs, V128:$rhs))],
                        !strconcat("i8x16.",
                          !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("i8x16.", name)>;
+                       !strconcat("i8x16.", name), baseInst>;
   defm _I16x8 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
                        (outs), (ins),
                        [(set (v8i16 V128:$dst), (node V128:$lhs, V128:$rhs))],
                        !strconcat("i16x8.",
                          !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("i16x8.", name)>;
+                       !strconcat("i16x8.", name), !add(baseInst, 1)>;
   defm _I32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
                        (outs), (ins),
                        [(set (v4i32 V128:$dst), (node V128:$lhs, V128:$rhs))],
                        !strconcat("i32x4.",
                          !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("i32x4.", name)>;
+                       !strconcat("i32x4.", name), !add(baseInst, 2)>;
+  defm _I64x2 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
+                       (outs), (ins),
+                       [(set (v2i64 V128:$dst), (node V128:$lhs, V128:$rhs))],
+                       !strconcat("i64x2.",
+                         !strconcat(name, "\t$dst, $lhs, $rhs")),
+                       !strconcat("i64x2.", name), !add(baseInst, 3)>;
+}
+multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
   defm _F32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
                        (outs), (ins),
-                       [(set (v4f32 V128:$dst), (fnode V128:$lhs, V128:$rhs))],
+                       [(set (v4f32 V128:$dst), (node V128:$lhs, V128:$rhs))],
                        !strconcat("f32x4.",
                          !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("f32x4.", name)>;
+                       !strconcat("f32x4.", name), baseInst>;
+  defm _F64x2 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
+                       (outs), (ins),
+                       [(set (v2f64 V128:$dst), (node V128:$lhs, V128:$rhs))],
+                       !strconcat("f64x2.",
+                         !strconcat(name, "\t$dst, $lhs, $rhs")),
+                       !strconcat("f64x2.", name), !add(baseInst, 1)>;
 }
 multiclass ComparisonInt<CondCode cond, string name, bits<32> i32Inst, bits<32> i64Inst> {
   defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
                 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
                 !strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
                 !strconcat("i32.", name), i32Inst>;
   defm _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins),
                 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],

lib/Target/WebAssembly/WebAssemblyInstrInfo.td

 defm "": ARGUMENT<I32>;
 defm "": ARGUMENT<I64>;
 defm "": ARGUMENT<F32>;
 defm "": ARGUMENT<F64>;
 defm "": ARGUMENT<EXCEPT_REF>;
 defm "": SIMD_ARGUMENT<v16i8>;
 defm "": SIMD_ARGUMENT<v8i16>;
 defm "": SIMD_ARGUMENT<v4i32>;
+defm "": SIMD_ARGUMENT<v2i64>;
 defm "": SIMD_ARGUMENT<v4f32>;
+defm "": SIMD_ARGUMENT<v2f64>;
 
 let Defs = [ARGUMENTS] in {
 
 // get_local and set_local are not generated by instruction selection; they
 // are implied by virtual register uses and defs.
 multiclass LOCAL<WebAssemblyRegClass vt> {
 let hasSideEffects = 0 in {
   // COPY is not an actual instruction in wasm, but since we allow get_local and

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 // WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// WebAssembly SIMD operand code-gen constructs.
 ///
 //===----------------------------------------------------------------------===//
 
-let isCommutable = 1 in {
-defm ADD : SIMDBinary<add, fadd, "add ">;
-defm MUL: SIMDBinary<mul, fmul, "mul ">;
-} // isCommutable = 1
-defm SUB: SIMDBinary<sub, fsub, "sub ">;
+let Defs = [ARGUMENTS] in {
+
+let isCommutable = 1 in
+defm ADD : SIMDBinaryInt<add, "add ", 24>;
+defm SUB : SIMDBinaryInt<sub, "sub ", 28>;
+let isCommutable = 1 in
+defm MUL : SIMDBinaryInt<mul, "mul ", 32>;
+
+let isCommutable = 1 in
+defm ADD : SIMDBinaryFP<fadd, "add ", 122>;
+defm SUB : SIMDBinaryFP<fsub, "sub ", 124>;
+defm DIV : SIMDBinaryFP<fdiv, "div ", 126>;
+let isCommutable = 1 in
+defm MUL : SIMDBinaryFP<fmul, "mul ", 128>;
+
+} // Defs = [ARGUMENTS]

lib/Target/WebAssembly/WebAssemblyPeephole.cpp

for (auto &MI : MBB)
             MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_v8i16,
             WebAssembly::COPY_V128);
         break;
       case WebAssembly::RETURN_v4i32:
         Changed |= MaybeRewriteToFallthrough(
             MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_v4i32,
             WebAssembly::COPY_V128);
         break;
+      case WebAssembly::RETURN_v2i64:
+        Changed |= MaybeRewriteToFallthrough(
+            MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_v2i64,
+            WebAssembly::COPY_V128);
+        break;
       case WebAssembly::RETURN_v4f32:
         Changed |= MaybeRewriteToFallthrough(
             MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_v4f32,
             WebAssembly::COPY_V128);
         break;
+      case WebAssembly::RETURN_v2f64:
+        Changed |= MaybeRewriteToFallthrough(
+            MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_v2f64,
+            WebAssembly::COPY_V128);
+        break;
       case WebAssembly::RETURN_VOID:
         Changed |= MaybeRewriteToFallthrough(
             MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_VOID,
             WebAssembly::INSTRUCTION_LIST_END);
         break;
       }
 
   return Changed;
 }

lib/Target/WebAssembly/WebAssemblyRegisterInfo.td

 //===----------------------------------------------------------------------===//
 //  Register classes
 //===----------------------------------------------------------------------===//
 
 def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>;
 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
 def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
 def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
-def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>;
+def V128 : WebAssemblyRegClass<[v4f32, v2f64, v2i64, v4i32, v16i8, v8i16], 128, (add V128_0)>;
 def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>;
-

lib/Target/WebAssembly/WebAssemblyUtilities.cpp

bool WebAssembly::isArgument(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   case WebAssembly::ARGUMENT_I32:
   case WebAssembly::ARGUMENT_I64:
   case WebAssembly::ARGUMENT_F32:
   case WebAssembly::ARGUMENT_F64:
   case WebAssembly::ARGUMENT_v16i8:
   case WebAssembly::ARGUMENT_v8i16:
   case WebAssembly::ARGUMENT_v4i32:
+  case WebAssembly::ARGUMENT_v2i64:
   case WebAssembly::ARGUMENT_v4f32:
+  case WebAssembly::ARGUMENT_v2f64:
     return true;
   default:
     return false;
   }
 }
 
 bool WebAssembly::isCopy(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
bool WebAssembly::isCallDirect(const MachineInstr &MI) {
   case WebAssembly::CALL_VOID:
   case WebAssembly::CALL_I32:
   case WebAssembly::CALL_I64:
   case WebAssembly::CALL_F32:
   case WebAssembly::CALL_F64:
   case WebAssembly::CALL_v16i8:
   case WebAssembly::CALL_v8i16:
   case WebAssembly::CALL_v4i32:
+  case WebAssembly::CALL_v2i64:
   case WebAssembly::CALL_v4f32:
+  case WebAssembly::CALL_v2f64:
   case WebAssembly::CALL_EXCEPT_REF:
     return true;
   default:
     return false;
   }
 }
 
 bool WebAssembly::isCallIndirect(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   case WebAssembly::CALL_INDIRECT_VOID:
   case WebAssembly::CALL_INDIRECT_I32:
   case WebAssembly::CALL_INDIRECT_I64:
   case WebAssembly::CALL_INDIRECT_F32:
   case WebAssembly::CALL_INDIRECT_F64:
   case WebAssembly::CALL_INDIRECT_v16i8:
   case WebAssembly::CALL_INDIRECT_v8i16:
   case WebAssembly::CALL_INDIRECT_v4i32:
+  case WebAssembly::CALL_INDIRECT_v2i64:
   case WebAssembly::CALL_INDIRECT_v4f32:
+  case WebAssembly::CALL_INDIRECT_v2f64:
   case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
     return true;
   default:
     return false;
   }
 }
 
 unsigned WebAssembly::getCalleeOpNo(const MachineInstr &MI) {

test/CodeGen/WebAssembly/simd-arith.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that basic SIMD128 arithmetic operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
-declare i32 @llvm.ctlz.i32(i32, i1)
-declare i32 @llvm.cttz.i32(i32, i1)
-declare i32 @llvm.ctpop.i32(i32)
-
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: add_v16i8
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i8x16.add $push0=, $0, $1{{$}}

 ; SIMD128: i32x4.mul $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = mul <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
 ; ==============================================================================
+; 2 x i64
+; ==============================================================================
+; CHECK-LABEL: add_v2i64
+; NO-SIMD128-NOT: i64x2
+; SIMD128: .param v128, v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i64x2.add $push0=, $0, $1{{$}}
+; SIMD128: return $pop0{{$}}
+define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
+  %a = add <2 x i64> %x, %y
+  ret <2 x i64> %a
+}
+
+; CHECK-LABEL: sub_v2i64
+; NO-SIMD128-NOT: i64x2
+; SIMD128: .param v128, v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i64x2.sub $push0=, $0, $1{{$}}
+; SIMD128: return $pop0{{$}}
+define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
+  %a = sub <2 x i64> %x, %y
+  ret <2 x i64> %a
+}
+
+; CHECK-LABEL: mul_v2i64
+; NO-SIMD128-NOT: i64x2
+; SIMD128: .param v128, v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i64x2.mul $push0=, $0, $1{{$}}
+; SIMD128: return $pop0{{$}}
+define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
+  %a = mul <2 x i64> %x, %y
+  ret <2 x i64> %a
+}
+
+; ==============================================================================
 ; 4 x float
 ; ==============================================================================
 ; CHECK-LABEL: add_v4f32
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: f32x4.add $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fadd <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: sub_v4f32
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: f32x4.sub $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fsub <4 x float> %x, %y
   ret <4 x float> %a
 }
 
+; CHECK-LABEL: div_v4f32
+; NO-SIMD128-NOT: f32x4
+; SIMD128: .param v128, v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: f32x4.div $push0=, $0, $1{{$}}
+; SIMD128: return $pop0{{$}}
+define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
+  %a = fdiv <4 x float> %x, %y
+  ret <4 x float> %a
+}
+
 ; CHECK-LABEL: mul_v4f32
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: f32x4.mul $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fmul <4 x float> %x, %y
   ret <4 x float> %a
 }
 
+; ==============================================================================
+; 2 x double
+; ==============================================================================
+; CHECK-LABEL: add_v2f64
+; NO-SIMD128-NOT: f64x2
+; SIMD128: .param v128, v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: f64x2.add $push0=, $0, $1{{$}}
+; SIMD128: return $pop0{{$}}
+define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
+  %a = fadd <2 x double> %x, %y
+  ret <2 x double> %a
+}
+
+; CHECK-LABEL: sub_v2f64
+; NO-SIMD128-NOT: f64x2
+; SIMD128: .param v128, v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: f64x2.sub $push0=, $0, $1{{$}}
+; SIMD128: return $pop0{{$}}
+define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
+  %a = fsub <2 x double> %x, %y
+  ret <2 x double> %a
+}
+
+; CHECK-LABEL: div_v2f64
+; NO-SIMD128-NOT: f64x2
+; SIMD128: .param v128, v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: f64x2.div $push0=, $0, $1{{$}}
+; SIMD128: return $pop0{{$}}
+define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
+  %a = fdiv <2 x double> %x, %y
+  ret <2 x double> %a
+}
+
+; CHECK-LABEL: mul_v2f64
+; NO-SIMD128-NOT: f64x2
+; SIMD128: .param v128, v128{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: f64x2.mul $push0=, $0, $1{{$}}
+; SIMD128: return $pop0{{$}}
+define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
+  %a = fmul <2 x double> %x, %y
+  ret <2 x double> %a
+}