[ARM] FP16: support VACGT

[SjoerdMeijer]

Summary

I love 1 character fixes. ;-) And vcagt_f16 was actually already passing, so just enabled the test.

[olista01]

Ont nit, other than that LGTM.

test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll

525

The test is "vcagt", but the intrincic/instruction is "vacgt".

[SjoerdMeijer]

test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll

525

Thanks, I will fix the typo before committing.

[SjoerdMeijer]

test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll

525

Mmmm.... it's not a typo: the reason is because the ACLE intrinsic is called "vcagt". I will therefore keep it as it is...

561

But will remove this test, because we don't have an int_arm_neon_vaclt intrinsic, and instead generate/use vcagt.

lib/Target/ARM/ARMInstrNEON.td

 def  VACGTfd   : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
                         "f32", v2i32, v2f32, int_arm_neon_vacgt, 0>;
 def  VACGTfq   : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
                         "f32", v4i32, v4f32, int_arm_neon_vacgt, 0>;
 def  VACGThd   : N3VDInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
                         "f16", v4i16, v4f16, int_arm_neon_vacgt, 0>,
                  Requires<[HasNEON, HasFullFP16]>;
 def  VACGThq   : N3VQInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
-                        "f16", v8f16, v8f16, int_arm_neon_vacgt, 0>,
+                        "f16", v8i16, v8f16, int_arm_neon_vacgt, 0>,
                  Requires<[HasNEON, HasFullFP16]>;
 //   VTST     : Vector Test Bits
 defm VTST     : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
                         IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
 
 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
                    (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",

test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll

 ; CHECKLABEL: test_vcageq_f16:
 ; CHECK:         vacge.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vcageq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half> %a, <8 x half> %b)
   ret <8 x i16> %vcageq_v2.i
 }
 
-; FIXME (PR38404)
-;
-;define dso_local <4 x i16> @test_vcagt_f16(<4 x half> %a, <4 x half> %b) {
-;entry:
-;  %vcagt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b)
-;  ret <4 x i16> %vcagt_v2.i
-;}
-;
-;define dso_local <8 x i16> @test_vcagtq_f16(<8 x half> %a, <8 x half> %b) {
-;entry:
-;  %vcagtq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b)
-;  ret <8 x i16> %vcagtq_v2.i
-;}
+define dso_local <4 x i16> @test_vcagt_f16(<4 x half> %a, <4 x half> %b) {
+; CHECK-LABEL: test_vcagt_f16:
+; CHECK:         vacgt.f16 d0, d0, d1
+; CHECK-NEXT:    bx lr
+entry:
+  %vcagt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b)
+  ret <4 x i16> %vcagt_v2.i
+}
+
+define dso_local <8 x i16> @test_vcagtq_f16(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: test_vcagtq_f16:
+; CHECK:         vacgt.f16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %vcagtq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b)
+  ret <8 x i16> %vcagtq_v2.i
+}
 
 define dso_local <4 x i16> @test_vcale_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vcale_f16:
 ; CHECK:         vacge.f16 d0, d1, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcale_v2.i = tail call <4 x i16> @llvm.arm.neon.vacge.v4i16.v4f16(<4 x half> %b, <4 x half> %a)
   ret <4 x i16> %vcale_v2.i
 }
 
 define dso_local <8 x i16> @test_vcaleq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vcaleq_f16:
 ; CHECK:         vacge.f16 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcaleq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half> %b, <8 x half> %a)
   ret <8 x i16> %vcaleq_v2.i
 }
 
-; FIXME (PR38404)
-;
-;define dso_local <4 x i16> @test_vcalt_f16(<4 x half> %a, <4 x half> %b) {
-;entry:
-;  %vcalt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %b, <4 x half> %a)
-;  ret <4 x i16> %vcalt_v2.i
-;}
+define dso_local <4 x i16> @test_vcalt_f16(<4 x half> %a, <4 x half> %b) {
+; CHECK-LABEL: test_vcalt_f16:
+; CHECK:         vacgt.f16 d0, d1, d0
+; CHECK-NEXT:    bx lr
+entry:
+  %vcalt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %b, <4 x half> %a)
+  ret <4 x i16> %vcalt_v2.i
+}
 
-;define dso_local <8 x i16> @test_vcaltq_f16(<8 x half> %a, <8 x half> %b) {
-;entry:
-;  %vcaltq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %b, <8 x half> %a)
-;  ret <8 x i16> %vcaltq_v2.i
-;}
+define dso_local <8 x i16> @test_vcaltq_f16(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: test_vcaltq_f16:
+; CHECK:         vacgt.f16 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %vcaltq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %b, <8 x half> %a)
+  ret <8 x i16> %vcaltq_v2.i
+}
 
 define dso_local <4 x i16> @test_vceq_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vceq_f16:
 ; CHECK:         vceq.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp oeq <4 x half> %a, %b
   %sext.i = sext <4 x i1> %cmp.i to <4 x i16>