[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate.

[kito-cheng]

Summary

GAS support immediate operand for those instructions without i suffix.

[kito-cheng]

Update testcase.

[sabuasal]

test/MC/RISCV/rvi-aliases-valid.s

179

This test should print the canonical version of the instruction, you are printing the Alias.

[kito-cheng]

test/MC/RISCV/rvi-aliases-valid.s

179

Those alias instructions always disassemble to i version in GAS even -M no-aliases is given, my thought is keep the behavior with GAS.

[asb]

Thanks Kito, I've added a couple of comments. I think the main issue is the pattern for the shift amount immediate, which means invalid assembly is accepted.

lib/Target/RISCV/RISCVInstrInfo.td

562–567

These should use uimmlog2xlen for the shift amount. When fixing this, could you please also add tests that demonstrate the range checks are correct (adding to rv32i-aliases-invalid.s and rv64i-aliases-invalid.s)?

test/MC/RISCV/rvi-aliases-valid.s

179

Yes, we should match gas here. Perhaps add a comment to this test like "The following aliases are accepted as input but the canonical form of the instruction will always be printed."

[kito-cheng]

Changes:

• Add addw, sllw, srlw and sraw including testcase.
• Add comment in testcase.

[asb]

Thanks Kito. This patch breaks rv32i-invalid.s as the error message for add a1, a2, (a3) changes. Could you adjust that test too please?

It probably makes most sense to use 32 as the shamt in the relevant tests in rv32i-aliases-invalid.s and rv64i-aliases-invalid.s

[kito-cheng]

Changes:

• Update testcase for rv32i-aliases-invalid.s and rv64i-aliases-invalid.s
• Fix rv32i-invalid.s

[asb]

Thanks Kito, looks good to me.

lib/Target/RISCV/RISCVInstrInfo.td

 
 def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, uimm12:$csr, uimm5:$imm)>;
 def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, uimm12:$csr, uimm5:$imm)>;
 def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, uimm12:$csr, uimm5:$imm)>;
 
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
+let EmitPriority = 0 in {
+def : InstAlias<"add $rd, $rs1, $imm12",
+                (ADDI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"and $rd, $rs1, $imm12",
+                (ANDI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"xor $rd, $rs1, $imm12",
+                (XORI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"or $rd, $rs1, $imm12",
+                (ORI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"sll $rd, $rs1, $shamt",
+                (SLLI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
+def : InstAlias<"srl $rd, $rs1, $shamt",
+                (SRLI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
+def : InstAlias<"sra $rd, $rs1, $shamt",
+                (SRAI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
+let Predicates = [IsRV64] in {
+def : InstAlias<"addw $rd, $rs1, $imm12",
+                (ADDIW  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"sllw $rd, $rs1, $shamt",
+                (SLLIW  GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
+def : InstAlias<"srlw $rd, $rs1, $shamt",
+                (SRLIW  GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
+def : InstAlias<"sraw $rd, $rs1, $shamt",
+                (SRAIW  GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
+} // Predicates = [IsRV64]
+def : InstAlias<"slt $rd, $rs1, $imm12",
+                (SLTI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"sltu $rd, $rs1, $imm12",
+                (SLTIU  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+}
+
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //
 // Naming convention: For 'generic' pattern classes, we use the naming
 // convention PatTy1Ty2. For pattern classes which offer a more complex
 // expension, prefix the class name, e.g. BccPat.
 //===----------------------------------------------------------------------===//
 

test/MC/RISCV/rv32i-aliases-invalid.s

 # RUN: not llvm-mc %s -triple=riscv32 -riscv-no-aliases 2>&1 | FileCheck %s
 # RUN: not llvm-mc %s -triple=riscv32 2>&1 | FileCheck %s
 
 # TODO ld
 # TODO sd
 
 li x0, 4294967296   # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
 li x0, -2147483649  # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
 li t4, foo          # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
 
 negw x1, x2   # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 
+sll x2, x3, 33  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+srl x2, x3, 33  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+sra x2, x3, 33  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+
+sll x2, x3, -1  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+srl x2, x3, -2  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+sra x2, x3, -3  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+
 foo:
   .space 4

test/MC/RISCV/rv64i-aliases-invalid.s

 # RUN: not llvm-mc %s -triple=riscv64 -riscv-no-aliases 2>&1 | FileCheck %s
 # RUN: not llvm-mc %s -triple=riscv64 2>&1 | FileCheck %s
 
 li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand
 li t4, foo                 # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer
 
 rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 rdcycleh x27   # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 rdtimeh x28    # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 
+sll x2, x3, 64  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+srl x2, x3, 64  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+sra x2, x3, 64  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+
+sll x2, x3, -1  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+srl x2, x3, -2  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+sra x2, x3, -3  # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+
+sllw x2, x3, 33  # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+srlw x2, x3, 33  # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+sraw x2, x3, 33  # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+
+sllw x2, x3, -1  # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+srlw x2, x3, -2  # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+sraw x2, x3, -3  # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+
 foo:
   .space 8

test/MC/RISCV/rv64i-aliases-valid.s

 li t5, 0xFFFFFFFFFFFFFFFF
 
 # CHECK-INST: subw t6, zero, ra
 # CHECK-ALIAS: negw t6, ra
 negw x31, x1
 # CHECK-INST: addiw t6, ra, 0
 # CHECK-ALIAS: sext.w t6, ra
 sext.w x31, x1
+
+# The following aliases are accepted as input but the canonical form
+# of the instruction will always be printed.
+# CHECK-INST: addiw a2, a3, 4
+# CHECK-ALIAS: addiw a2, a3, 4
+addw a2,a3,4
+
+# CHECK-INST: slliw a2, a3, 4
+# CHECK-ALIAS: slliw a2, a3, 4
+sllw a2,a3,4
+
+# CHECK-INST: srliw a2, a3, 4
+# CHECK-ALIAS: srliw a2, a3, 4
+srlw a2,a3,4
+
+# CHECK-INST: sraiw a2, a3, 4
+# CHECK-ALIAS: sraiw a2, a3, 4
+sraw a2,a3,4

test/MC/RISCV/rvi-aliases-valid.s

 csrci 0x140, 0x11
 
 # CHECK-INST: sfence.vma zero, zero
 # CHECK-ALIAS: sfence.vma
 sfence.vma
 # CHECK-INST: sfence.vma a0, zero
 # CHECK-ALIAS: sfence.vma a0
 sfence.vma a0
+
+# The following aliases are accepted as input but the canonical form
+# of the instruction will always be printed.
+# CHECK-INST: addi a2, a3, 4
+# CHECK-ALIAS: addi a2, a3, 4
+add a2,a3,4
+
+# CHECK-INST: andi a2, a3, 4
+# CHECK-ALIAS: andi a2, a3, 4
+and a2,a3,4
+
+# CHECK-INST: xori a2, a3, 4
+# CHECK-ALIAS: xori a2, a3, 4
+xor a2,a3,4
+
+# CHECK-INST: ori a2, a3, 4
+# CHECK-ALIAS: ori a2, a3, 4
+or a2,a3,4
+
+# CHECK-INST: slli a2, a3, 4
+# CHECK-ALIAS: slli a2, a3, 4
+sll a2,a3,4
+
+# CHECK-INST: srli a2, a3, 4
+# CHECK-ALIAS: srli a2, a3, 4
+srl a2,a3,4
+
+# CHECK-INST: srai a2, a3, 4
+# CHECK-ALIAS: srai a2, a3, 4
+sra a2,a3,4
+
+# CHECK-INST: slti a2, a3, 4
+# CHECK-ALIAS: slti a2, a3, 4
+slt a2,a3,4
+
+# CHECK-INST: sltiu a2, a3, 4
+# CHECK-ALIAS: sltiu a2, a3, 4
+sltu a2,a3,4