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Differential D49737

AMDGPU/GlobalISel: Define instruction mapping for G_SELECT
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Authored by tstellar on Jul 24 2018, 8:29 AM.

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arsenm
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rGffc6bd6f3d2c: AMDGPU/GlobalISel: Define instruction mapping for G_SELECT
rL341271: AMDGPU/GlobalISel: Define instruction mapping for G_SELECT

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rL LLVM

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tstellar created this revision.Jul 24 2018, 8:29 AM
Herald added subscribers: t-tye, tpr, dstuttard and 6 others. · View Herald TranscriptJul 24 2018, 8:29 AM
Harbormaster completed remote builds in B20661: Diff 157046.Jul 24 2018, 8:29 AM
arsenm accepted this revision.Jul 24 2018, 8:36 AM

LGTM

This revision is now accepted and ready to land.Jul 24 2018, 8:36 AM
Closed by commit rL341271: AMDGPU/GlobalISel: Define instruction mapping for G_SELECT (authored by tstellar). · Explain WhyAug 31 2018, 7:43 PM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: jvesely. · View Herald TranscriptAug 31 2018, 7:43 PM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
54 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
214 lines

Diff 163615

llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 164 Lines • ▼ Show 20 Lines const InstructionMapping &VVMapping = getInstructionMapping(4, 1,
nullptr, // Predicate operand. nullptr, // Predicate operand.
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}), AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands 4); // Num Operands
AltMappings.push_back(&VVMapping); AltMappings.push_back(&VVMapping);
return AltMappings; return AltMappings;
} }
case TargetOpcode::G_SELECT: {
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
4); // Num Operands
AltMappings.push_back(&SSMapping);
const InstructionMapping &SVMapping = getInstructionMapping(2, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands
AltMappings.push_back(&SVMapping);
const InstructionMapping &VSMapping = getInstructionMapping(2, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
4); // Num Operands
AltMappings.push_back(&VSMapping);
const InstructionMapping &VVMapping = getInstructionMapping(2, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands
AltMappings.push_back(&VVMapping);
return AltMappings;
}
default: default:
break; break;
} }
return RegisterBankInfo::getInstrAlternativeMappings(MI); return RegisterBankInfo::getInstrAlternativeMappings(MI);
} }
void AMDGPURegisterBankInfo::applyMappingImpl( void AMDGPURegisterBankInfo::applyMappingImpl(
const OperandsMapper &OpdMapper) const { const OperandsMapper &OpdMapper) const {
▲ Show 20 Lines • Show All 356 Lines • ▼ Show 20 Lines case Intrinsic::amdgcn_exp:
OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
// FIXME: These are immediate values which can't be read from registers. // FIXME: These are immediate values which can't be read from registers.
OpdsMapping[7] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32); OpdsMapping[7] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
OpdsMapping[8] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32); OpdsMapping[8] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
break; break;
} }
break; break;
} }
case AMDGPU::G_SELECT: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned Op1Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
AMDGPU::SGPRRegBankID);
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
bool SGPRSrcs = Op1Bank == AMDGPU::SCCRegBankID &&
Op2Bank == AMDGPU::SGPRRegBankID &&
Op3Bank == AMDGPU::SGPRRegBankID;
unsigned Bank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
Op1Bank = SGPRSrcs ? AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, Size);
OpdsMapping[1] = AMDGPU::getValueMapping(Op1Bank, 1);
OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size);
break;
}
case AMDGPU::G_LOAD: case AMDGPU::G_LOAD:
return getInstrMappingForLoad(MI); return getInstrMappingForLoad(MI);
} }
return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping), return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
MI.getNumOperands()); MI.getNumOperands());
} }

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=GCN,FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck --check-prefixes=GCN,GREEDY %s
# REQUIRES: global-isel
--- |
define void @select_sss() { ret void }
define void @select_ssv() { ret void }
define void @select_svs() { ret void }
define void @select_svv() { ret void }
define void @select_vss() { ret void }
define void @select_vsv() { ret void }
define void @select_vvs() { ret void }
define void @select_vvv() { ret void }
...
---
name: select_sss
legalized: true
# GCN-LABEL: name: select_sss
# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
# GCN: [[SGPR3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
# GCN: {{%[0-9]+}}:sgpr(s32) = G_SELECT [[SCC]](s1), [[SGPR2]], [[SGPR3]]
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = COPY $sgpr3
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %2, %3
...
---
name: select_ssv
legalized: true
# GCN-LABEL: name: select_ssv
# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
# GCN: [[SCC_S:%[0-9]+]]:sgpr(s1) = COPY [[SCC]]
# FAST: [[SGPR2_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR2]]
# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[SGPR2_V]], [[VGPR0]]
# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[SGPR2]], [[VGPR0]]
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = COPY $vgpr0
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %2, %3
...
---
name: select_svs
legalized: true
# GCN-LABEL: name: select_svs
# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
# GCN: [[SCC_S:%[0-9]+]]:sgpr(s1) = COPY [[SCC]]
# FAST: [[SGPR2_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR2]]
# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[SGPR2_V]]
# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[SGPR2]]
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = COPY $vgpr0
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %3, %2
...
---
name: select_svv
legalized: true
# GCN-LABEL: name: select_svv
# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
# GCN: [[SCC_S:%[0-9]+]]:sgpr(s1) = COPY [[SCC]]
# GCN: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[VGPR1]]
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
%3:_(s32) = COPY $vgpr1
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %2, %3
...
---
name: select_vss
legalized: true
# GCN-LABEL: name: select_vss
# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]
# GCN: [[SGPR1_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR1]]
# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0_V]], [[SGPR1_V]]
# GREDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0]], [[SGPR1_V]]
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
%3:_(s32) = COPY $vgpr1
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(s32) = G_SELECT %4, %0, %1
...
---
name: select_vsv
legalized: true
# GCN-LABEL: name: select_vsv
# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]
# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0_V]], [[VGPR2]]
# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0]], [[VGPR2]]
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(s32) = COPY $vgpr2
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(s32) = G_SELECT %4, %0, %3
...
---
name: select_vvs
legalized: true
# GCN-LABEL: name: select_vvs
# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]
# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[SGPR0_V]]
# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[SGPR0]]
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(s32) = COPY $vgpr2
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(s32) = G_SELECT %4, %3, %0
...
---
name: select_vvv
legalized: true
# GCN-LABEL: name: select_vvv
# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
# GCN: [[VGPR3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
# GCN: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[VGPR3]]
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
%3:_(s32) = COPY $vgpr3
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %2, %3
...