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Differential D49393

[NFC][MCA] ZnVer1: Update RegisterFile to identify false dependencies on partially written registers.
ClosedPublic

Authored by lebedev.ri on Jul 16 2018, 11:48 AM.

Details

Reviewers
andreadb
courbet
RKSimon
craig.topper
GGanesh
Commits
rG52b85377eb60: [NFC][MCA] ZnVer1: Update RegisterFile to identify false dependencies on…
rL337676: [NFC][MCA] ZnVer1: Update RegisterFile to identify false dependencies on…
Summary

Pretty mechanical follow-up for D49196.

As microarchitecture.pdf notes, "20 AMD Ryzen pipeline",
"20.8 Register renaming and out-of-order schedulers":

The integer register file has 168 physical registers of 64 bits each.
The floating point register file has 160 registers of 128 bits each.

"20.14 Partial register access":

The processor always keeps the different parts of an integer register together. 
...
An instruction that writes to part of a register will therefore have a false dependence
on any previous write to the same register or any part of it.

There is one caveat, however:

An instruction that writes to a 32-bit register will not have any false dependence on the
corresponding 64-bit register because the upper part of the 64-bit register is set to zero.

I have added a test (partial-reg-update-7.s), but something seems to be missing,
if i keep GR32 in RegisterFile<>, the test doesn't change.

Diff Detail

Repository
rL LLVM

Event Timeline

lebedev.ri created this revision.Jul 16 2018, 11:48 AM
Herald added a subscriber: gbedwell. · View Herald TranscriptJul 16 2018, 11:48 AM
lebedev.ri added a parent revision: D49392: [NFC][MCA] ZnVer1: add partial-reg-update tests.Jul 16 2018, 11:49 AM
andreadb added a comment.Jul 18 2018, 3:57 AM

I have added a test (partial-reg-update-7.s), but something seems to be missing,
if i keep GR32 in RegisterFile<>, the test doesn't change.

That is because on x86-64, a write to EAX implicitly zeroes the upper half or RAX. So, there is no false dependency with previous values of RAX, and - for the purpose of mca - EAX renames as RAX. See also the definition of X86CInstrAnalysis::clearsSuperRegisters() in the X86 Backend (X86/MCTargetDesc/X86MCTargetDesc.cpp).

lebedev.ri added a comment.Jul 18 2018, 4:10 AM
In D49393#1166251, @andreadb wrote:

I have added a test (partial-reg-update-7.s), but something seems to be missing,
if i keep GR32 in RegisterFile<>, the test doesn't change.

That is because on x86-64, a write to EAX implicitly zeroes the upper half or RAX. So, there is no false dependency with previous values of RAX, and - for the purpose of mca - EAX renames as RAX. See also the definition of X86CInstrAnalysis::clearsSuperRegisters() in the X86 Backend (X86/MCTargetDesc/X86MCTargetDesc.cpp).

Right, thank you, so this already works as-is; Should i keep the test?

andreadb added a comment.Jul 18 2018, 4:15 AM
In D49393#1166284, @lebedev.ri wrote:
In D49393#1166251, @andreadb wrote:

I have added a test (partial-reg-update-7.s), but something seems to be missing,
if i keep GR32 in RegisterFile<>, the test doesn't change.

That is because on x86-64, a write to EAX implicitly zeroes the upper half or RAX. So, there is no false dependency with previous values of RAX, and - for the purpose of mca - EAX renames as RAX. See also the definition of X86CInstrAnalysis::clearsSuperRegisters() in the X86 Backend (X86/MCTargetDesc/X86MCTargetDesc.cpp).

Right, thank you, so this already works as-is; Should i keep the test?

It is fine to keep the test :-)

lebedev.ri added a comment.Jul 23 2018, 2:37 AM

Ping?

GGanesh accepted this revision.Jul 23 2018, 2:47 AM

I am fine!

This revision is now accepted and ready to land.Jul 23 2018, 2:47 AM
lebedev.ri added a comment.Jul 23 2018, 2:49 AM
In D49393#1171343, @GGanesh wrote:

I am fine!

Thank you for the review.

Care to also stamp the tests? :) (D49392)

Closed by commit rL337676: [NFC][MCA] ZnVer1: Update RegisterFile to identify false dependencies on… (authored by lebedevri). · Explain WhyJul 23 2018, 3:10 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
2 lines
test/
tools/
llvm-mca/
X86/
Znver1/
16 lines
55 lines
56 lines
25 lines
40 lines

Diff 156732

llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
def ZnDivider : ProcResource<1>; def ZnDivider : ProcResource<1>;
// 4 Cycles load-to use Latency is captured // 4 Cycles load-to use Latency is captured
def : ReadAdvance<ReadAfterLd, 4>; def : ReadAdvance<ReadAfterLd, 4>;
// The Integer PRF for Zen is 168 entries, and it holds the architectural and // The Integer PRF for Zen is 168 entries, and it holds the architectural and
// speculative version of the 64-bit integer registers. // speculative version of the 64-bit integer registers.
// Reference: "Software Optimization Guide for AMD Family 17h Processors" // Reference: "Software Optimization Guide for AMD Family 17h Processors"
def ZnIntegerPRF : RegisterFile<168, [GR8, GR16, GR32, GR64, CCR]>; def ZnIntegerPRF : RegisterFile<168, [GR64, CCR]>;
// 36 Entry (9x4 entries) floating-point Scheduler // 36 Entry (9x4 entries) floating-point Scheduler
def ZnFPU : ProcResGroup<[ZnFPU0, ZnFPU1, ZnFPU2, ZnFPU3]> { def ZnFPU : ProcResGroup<[ZnFPU0, ZnFPU1, ZnFPU2, ZnFPU3]> {
let BufferSize=36; let BufferSize=36;
} }
// The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit // The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit
// registers. Operations on 256-bit data types are cracked into two COPs. // registers. Operations on 256-bit data types are cracked into two COPs.
▲ Show 20 Lines • Show All 1,434 Lines • Show Last 20 Lines

llvm/trunk/test/tools/llvm-mca/X86/Znver1/partial-reg-update-2.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
imul %rax, %rbx imul %rax, %rbx
lzcnt %ax, %bx lzcnt %ax, %bx
add %ecx, %ebx add %ecx, %ebx
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3 # CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 8 # CHECK-NEXT: Total Cycles: 9
# CHECK-NEXT: Dispatch Width: 4 # CHECK-NEXT: Dispatch Width: 4
# CHECK-NEXT: IPC: 0.38 # CHECK-NEXT: IPC: 0.33
# CHECK-NEXT: Block RThroughput: 1.0 # CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 4 1.00 imulq %rax, %rbx # CHECK-NEXT: 2 4 1.00 imulq %rax, %rbx
# CHECK-NEXT: 1 2 0.25 lzcntw %ax, %bx # CHECK-NEXT: 1 2 0.25 lzcntw %ax, %bx
# CHECK-NEXT: 1 1 0.25 addl %ecx, %ebx # CHECK-NEXT: 1 1 0.25 addl %ecx, %ebx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 01234567 # CHECK-NEXT: Index 012345678
# CHECK: [0,0] DeeeeER. imulq %rax, %rbx # CHECK: [0,0] DeeeeER . imulq %rax, %rbx
# CHECK-NEXT: [0,1] DeeE--R. lzcntw %ax, %bx # CHECK-NEXT: [0,1] D===eeER. lzcntw %ax, %bx
# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx # CHECK-NEXT: [0,2] D=====eER addl %ecx, %ebx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx
# CHECK-NEXT: 1. 1 1.0 1.0 2.0 lzcntw %ax, %bx # CHECK-NEXT: 1. 1 4.0 0.0 0.0 lzcntw %ax, %bx
# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx # CHECK-NEXT: 2. 1 6.0 0.0 0.0 addl %ecx, %ebx

llvm/trunk/test/tools/llvm-mca/X86/Znver1/partial-reg-update-3.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1500 -timeline -timeline-max-iterations=6 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1500 -timeline -timeline-max-iterations=6 < %s | FileCheck %s
# The ILP is limited by the false dependency on %dx. So, the mov cannot execute # The ILP is limited by the false dependency on %dx. So, the mov cannot execute
# in parallel with the add. # in parallel with the add.
add %cx, %dx add %cx, %dx
mov %ax, %dx mov %ax, %dx
xor %bx, %dx xor %bx, %dx
# CHECK: Iterations: 1500 # CHECK: Iterations: 1500
# CHECK-NEXT: Instructions: 4500 # CHECK-NEXT: Instructions: 4500
# CHECK-NEXT: Total Cycles: 1129 # CHECK-NEXT: Total Cycles: 4503
# CHECK-NEXT: Dispatch Width: 4 # CHECK-NEXT: Dispatch Width: 4
# CHECK-NEXT: IPC: 3.99 # CHECK-NEXT: IPC: 1.00
# CHECK-NEXT: Block RThroughput: 0.8 # CHECK-NEXT: Block RThroughput: 0.8
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
Show All 19 Lines
# CHECK-NEXT: [11] - ZnMultiplier # CHECK-NEXT: [11] - ZnMultiplier
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
# CHECK-NEXT: - - 0.75 0.75 0.75 0.75 - - - - - - # CHECK-NEXT: - - 0.75 0.75 0.75 0.75 - - - - - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
# CHECK-NEXT: - - - 0.25 0.75 - - - - - - - addw %cx, %dx # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - addw %cx, %dx
# CHECK-NEXT: - - 0.25 - - 0.75 - - - - - - movw %ax, %dx # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - movw %ax, %dx
# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - xorw %bx, %dx # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - xorw %bx, %dx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 012345678 # CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeER . . addw %cx, %dx # CHECK: [0,0] DeER . . . . addw %cx, %dx
# CHECK-NEXT: [0,1] DeER . . movw %ax, %dx # CHECK-NEXT: [0,1] D=eER. . . . movw %ax, %dx
# CHECK-NEXT: [0,2] D=eER. . xorw %bx, %dx # CHECK-NEXT: [0,2] D==eER . . . xorw %bx, %dx
# CHECK-NEXT: [1,0] D==eER . addw %cx, %dx # CHECK-NEXT: [1,0] D===eER . . . addw %cx, %dx
# CHECK-NEXT: [1,1] .DeE-R . movw %ax, %dx # CHECK-NEXT: [1,1] .D===eER . . . movw %ax, %dx
# CHECK-NEXT: [1,2] .D=eER . xorw %bx, %dx # CHECK-NEXT: [1,2] .D====eER . . . xorw %bx, %dx
# CHECK-NEXT: [2,0] .D==eER . addw %cx, %dx # CHECK-NEXT: [2,0] .D=====eER. . . addw %cx, %dx
# CHECK-NEXT: [2,1] .DeE--R . movw %ax, %dx # CHECK-NEXT: [2,1] .D======eER . . movw %ax, %dx
# CHECK-NEXT: [2,2] . DeE-R . xorw %bx, %dx # CHECK-NEXT: [2,2] . D======eER . . xorw %bx, %dx
# CHECK-NEXT: [3,0] . D=eER . addw %cx, %dx # CHECK-NEXT: [3,0] . D=======eER . . addw %cx, %dx
# CHECK-NEXT: [3,1] . DeE-R . movw %ax, %dx # CHECK-NEXT: [3,1] . D========eER . . movw %ax, %dx
# CHECK-NEXT: [3,2] . D=eER . xorw %bx, %dx # CHECK-NEXT: [3,2] . D=========eER. . xorw %bx, %dx
# CHECK-NEXT: [4,0] . D=eER. addw %cx, %dx # CHECK-NEXT: [4,0] . D=========eER . addw %cx, %dx
# CHECK-NEXT: [4,1] . DeE-R. movw %ax, %dx # CHECK-NEXT: [4,1] . D==========eER . movw %ax, %dx
# CHECK-NEXT: [4,2] . D=eER. xorw %bx, %dx # CHECK-NEXT: [4,2] . D===========eER . xorw %bx, %dx
# CHECK-NEXT: [5,0] . D==eER addw %cx, %dx # CHECK-NEXT: [5,0] . D============eER . addw %cx, %dx
# CHECK-NEXT: [5,1] . DeE-R movw %ax, %dx # CHECK-NEXT: [5,1] . D============eER. movw %ax, %dx
# CHECK-NEXT: [5,2] . D=eER xorw %bx, %dx # CHECK-NEXT: [5,2] . D=============eER xorw %bx, %dx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 6 2.3 0.2 0.0 addw %cx, %dx # CHECK-NEXT: 0. 6 7.0 0.2 0.0 addw %cx, %dx
# CHECK-NEXT: 1. 6 1.0 1.0 1.0 movw %ax, %dx # CHECK-NEXT: 1. 6 7.7 0.0 0.0 movw %ax, %dx
# CHECK-NEXT: 2. 6 1.8 0.0 0.2 xorw %bx, %dx # CHECK-NEXT: 2. 6 8.5 0.0 0.0 xorw %bx, %dx

llvm/trunk/test/tools/llvm-mca/X86/Znver1/partial-reg-update-4.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1500 -timeline -timeline-max-iterations=7 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1500 -timeline -timeline-max-iterations=7 < %s | FileCheck %s
# The lzcnt cannot execute in parallel with the imul because there is a false # The lzcnt cannot execute in parallel with the imul because there is a false
# dependency on %bx. # dependency on %bx.
imul %ax, %bx imul %ax, %bx
lzcnt %ax, %bx lzcnt %ax, %bx
add %cx, %bx add %cx, %bx
# CHECK: Iterations: 1500 # CHECK: Iterations: 1500
# CHECK-NEXT: Instructions: 4500 # CHECK-NEXT: Instructions: 4500
# CHECK-NEXT: Total Cycles: 1507 # CHECK-NEXT: Total Cycles: 7503
# CHECK-NEXT: Dispatch Width: 4 # CHECK-NEXT: Dispatch Width: 4
# CHECK-NEXT: IPC: 2.99 # CHECK-NEXT: IPC: 0.60
# CHECK-NEXT: Block RThroughput: 1.0 # CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
Show All 24 Lines
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - - - - 1.00 imulw %ax, %bx # CHECK-NEXT: - - - 1.00 - - - - - - - 1.00 imulw %ax, %bx
# CHECK-NEXT: - - 0.33 - 0.33 0.33 - - - - - - lzcntw %ax, %bx # CHECK-NEXT: - - 0.33 - 0.33 0.33 - - - - - - lzcntw %ax, %bx
# CHECK-NEXT: - - 0.33 - 0.33 0.33 - - - - - - addw %cx, %bx # CHECK-NEXT: - - 0.33 - 0.33 0.33 - - - - - - addw %cx, %bx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123 # CHECK-NEXT: 0123456789 01234567
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789 0123456789
# CHECK: [0,0] DeeeER . . imulw %ax, %bx # CHECK: [0,0] DeeeER . . . . . . . imulw %ax, %bx
# CHECK-NEXT: [0,1] DeeE-R . . lzcntw %ax, %bx # CHECK-NEXT: [0,1] D==eeER . . . . . . . lzcntw %ax, %bx
# CHECK-NEXT: [0,2] D==eER . . addw %cx, %bx # CHECK-NEXT: [0,2] D====eER . . . . . . . addw %cx, %bx
# CHECK-NEXT: [1,0] D===eeeER . . imulw %ax, %bx # CHECK-NEXT: [1,0] D=====eeeER . . . . . . imulw %ax, %bx
# CHECK-NEXT: [1,1] .DeeE---R . . lzcntw %ax, %bx # CHECK-NEXT: [1,1] .D======eeER . . . . . . lzcntw %ax, %bx
# CHECK-NEXT: [1,2] .D==eE--R . . addw %cx, %bx # CHECK-NEXT: [1,2] .D========eER . . . . . . addw %cx, %bx
# CHECK-NEXT: [2,0] .D===eeeER. . imulw %ax, %bx # CHECK-NEXT: [2,0] .D=========eeeER . . . . . imulw %ax, %bx
# CHECK-NEXT: [2,1] .DeeE----R. . lzcntw %ax, %bx # CHECK-NEXT: [2,1] .D===========eeER . . . . . lzcntw %ax, %bx
# CHECK-NEXT: [2,2] . D=eE---R. . addw %cx, %bx # CHECK-NEXT: [2,2] . D============eER . . . . . addw %cx, %bx
# CHECK-NEXT: [3,0] . D===eeeER . imulw %ax, %bx # CHECK-NEXT: [3,0] . D=============eeeER . . . . imulw %ax, %bx
# CHECK-NEXT: [3,1] . DeeE----R . lzcntw %ax, %bx # CHECK-NEXT: [3,1] . D===============eeER . . . . lzcntw %ax, %bx
# CHECK-NEXT: [3,2] . D==eE---R . addw %cx, %bx # CHECK-NEXT: [3,2] . D=================eER . . . . addw %cx, %bx
# CHECK-NEXT: [4,0] . D===eeeER . imulw %ax, %bx # CHECK-NEXT: [4,0] . D=================eeeER . . . imulw %ax, %bx
# CHECK-NEXT: [4,1] . DeeE----R . lzcntw %ax, %bx # CHECK-NEXT: [4,1] . D===================eeER . . . lzcntw %ax, %bx
# CHECK-NEXT: [4,2] . D==eE---R . addw %cx, %bx # CHECK-NEXT: [4,2] . D=====================eER . . . addw %cx, %bx
# CHECK-NEXT: [5,0] . D====eeeER. imulw %ax, %bx # CHECK-NEXT: [5,0] . D======================eeeER . . imulw %ax, %bx
# CHECK-NEXT: [5,1] . DeeE----R. lzcntw %ax, %bx # CHECK-NEXT: [5,1] . D=======================eeER . . lzcntw %ax, %bx
# CHECK-NEXT: [5,2] . D==eE---R. addw %cx, %bx # CHECK-NEXT: [5,2] . D=========================eER . . addw %cx, %bx
# CHECK-NEXT: [6,0] . D====eeeER imulw %ax, %bx # CHECK-NEXT: [6,0] . D==========================eeeER . imulw %ax, %bx
# CHECK-NEXT: [6,1] . DeeE-----R lzcntw %ax, %bx # CHECK-NEXT: [6,1] . D============================eeER. lzcntw %ax, %bx
# CHECK-NEXT: [6,2] . D=eE----R addw %cx, %bx # CHECK-NEXT: [6,2] . D=============================eER addw %cx, %bx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 7 3.9 0.7 0.0 imulw %ax, %bx # CHECK-NEXT: 0. 7 14.1 0.1 0.0 imulw %ax, %bx
# CHECK-NEXT: 1. 7 1.0 1.0 3.6 lzcntw %ax, %bx # CHECK-NEXT: 1. 7 15.9 0.0 0.0 lzcntw %ax, %bx
# CHECK-NEXT: 2. 7 2.7 0.0 2.6 addw %cx, %bx # CHECK-NEXT: 2. 7 17.6 0.0 0.0 addw %cx, %bx

llvm/trunk/test/tools/llvm-mca/X86/Znver1/partial-reg-update-5.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1500 -timeline -timeline-max-iterations=8 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1500 -timeline -timeline-max-iterations=8 < %s | FileCheck %s
lzcnt %ax, %bx ## partial register stall. lzcnt %ax, %bx ## partial register stall.
# CHECK: Iterations: 1500 # CHECK: Iterations: 1500
# CHECK-NEXT: Instructions: 1500 # CHECK-NEXT: Instructions: 1500
# CHECK-NEXT: Total Cycles: 379 # CHECK-NEXT: Total Cycles: 1504
# CHECK-NEXT: Dispatch Width: 4 # CHECK-NEXT: Dispatch Width: 4
# CHECK-NEXT: IPC: 3.96 # CHECK-NEXT: IPC: 1.00
# CHECK-NEXT: Block RThroughput: 0.3 # CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - lzcntw %ax, %bx # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - lzcntw %ax, %bx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 012345 # CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeER. lzcntw %ax, %bx # CHECK: [0,0] DeeER. .. lzcntw %ax, %bx
# CHECK-NEXT: [1,0] DeeER. lzcntw %ax, %bx # CHECK-NEXT: [1,0] D=eeER .. lzcntw %ax, %bx
# CHECK-NEXT: [2,0] DeeER. lzcntw %ax, %bx # CHECK-NEXT: [2,0] D==eeER .. lzcntw %ax, %bx
# CHECK-NEXT: [3,0] DeeER. lzcntw %ax, %bx # CHECK-NEXT: [3,0] D===eeER .. lzcntw %ax, %bx
# CHECK-NEXT: [4,0] .DeeER lzcntw %ax, %bx # CHECK-NEXT: [4,0] .D===eeER .. lzcntw %ax, %bx
# CHECK-NEXT: [5,0] .DeeER lzcntw %ax, %bx # CHECK-NEXT: [5,0] .D====eeER.. lzcntw %ax, %bx
# CHECK-NEXT: [6,0] .DeeER lzcntw %ax, %bx # CHECK-NEXT: [6,0] .D=====eeER. lzcntw %ax, %bx
# CHECK-NEXT: [7,0] .DeeER lzcntw %ax, %bx # CHECK-NEXT: [7,0] .D======eeER lzcntw %ax, %bx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 8 1.0 1.0 0.0 lzcntw %ax, %bx # CHECK-NEXT: 0. 8 4.0 0.1 0.0 lzcntw %ax, %bx

llvm/trunk/test/tools/llvm-mca/X86/Znver1/partial-reg-update-6.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1500 -timeline -timeline-max-iterations=4 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1500 -timeline -timeline-max-iterations=4 < %s | FileCheck %s
# Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
# imul. However, the folded load can start immediately. # imul. However, the folded load can start immediately.
# The last lzcnt has a false dependency on %cx. However, even in this case, the # The last lzcnt has a false dependency on %cx. However, even in this case, the
# folded load can start immediately. # folded load can start immediately.
imul %edx, %ecx imul %edx, %ecx
lzcnt (%rsp), %cx lzcnt (%rsp), %cx
lzcnt 2(%rsp), %cx lzcnt 2(%rsp), %cx
# CHECK: Iterations: 1500 # CHECK: Iterations: 1500
# CHECK-NEXT: Instructions: 4500 # CHECK-NEXT: Instructions: 4500
# CHECK-NEXT: Total Cycles: 4507 # CHECK-NEXT: Total Cycles: 10503
# CHECK-NEXT: Dispatch Width: 4 # CHECK-NEXT: Dispatch Width: 4
# CHECK-NEXT: IPC: 1.00 # CHECK-NEXT: IPC: 0.43
# CHECK-NEXT: Block RThroughput: 1.3 # CHECK-NEXT: Block RThroughput: 1.3
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [7] - ZnFPU0 # CHECK-NEXT: [7] - ZnFPU0
# CHECK-NEXT: [8] - ZnFPU1 # CHECK-NEXT: [8] - ZnFPU1
# CHECK-NEXT: [9] - ZnFPU2 # CHECK-NEXT: [9] - ZnFPU2
# CHECK-NEXT: [10] - ZnFPU3 # CHECK-NEXT: [10] - ZnFPU3
# CHECK-NEXT: [11] - ZnMultiplier # CHECK-NEXT: [11] - ZnMultiplier
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
# CHECK-NEXT: 1.00 1.00 0.66 1.00 0.67 0.67 - - - - - 1.00 # CHECK-NEXT: 1.00 1.00 0.67 1.00 0.67 0.67 - - - - - 1.00
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - - - - 1.00 imull %edx, %ecx # CHECK-NEXT: - - - 1.00 - - - - - - - 1.00 imull %edx, %ecx
# CHECK-NEXT: - 1.00 0.33 - 0.33 0.33 - - - - - - lzcntw (%rsp), %cx # CHECK-NEXT: - 1.00 0.33 - 0.33 0.33 - - - - - - lzcntw (%rsp), %cx
# CHECK-NEXT: 1.00 - 0.33 - 0.33 0.33 - - - - - - lzcntw 2(%rsp), %cx # CHECK-NEXT: 1.00 - 0.33 - 0.33 0.33 - - - - - - lzcntw 2(%rsp), %cx
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 012345678 # CHECK-NEXT: 0123456789 0
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789 0123456789
# CHECK: [0,0] DeeeER . . . imull %edx, %ecx # CHECK: [0,0] DeeeER . . . . . imull %edx, %ecx
# CHECK-NEXT: [0,1] DeeeeeeER . . . lzcntw (%rsp), %cx # CHECK-NEXT: [0,1] DeeeeeeER . . . . . lzcntw (%rsp), %cx
# CHECK-NEXT: [0,2] .DeeeeeeER. . . lzcntw 2(%rsp), %cx # CHECK-NEXT: [0,2] .DeeeeeeER. . . . . lzcntw 2(%rsp), %cx
# CHECK-NEXT: [1,0] .D======eeeER . . imull %edx, %ecx # CHECK-NEXT: [1,0] .D======eeeER . . . . imull %edx, %ecx
# CHECK-NEXT: [1,1] . DeeeeeeE--R . . lzcntw (%rsp), %cx # CHECK-NEXT: [1,1] . D=====eeeeeeER . . . lzcntw (%rsp), %cx
# CHECK-NEXT: [1,2] . DeeeeeeE--R . . lzcntw 2(%rsp), %cx # CHECK-NEXT: [1,2] . D======eeeeeeER . . . lzcntw 2(%rsp), %cx
# CHECK-NEXT: [2,0] . D=======eeeER . imull %edx, %ecx # CHECK-NEXT: [2,0] . D===========eeeER. . . imull %edx, %ecx
# CHECK-NEXT: [2,1] . DeeeeeeE----R . lzcntw (%rsp), %cx # CHECK-NEXT: [2,1] . D===========eeeeeeER . . lzcntw (%rsp), %cx
# CHECK-NEXT: [2,2] . DeeeeeeE---R . lzcntw 2(%rsp), %cx # CHECK-NEXT: [2,2] . D===========eeeeeeER . . lzcntw 2(%rsp), %cx
# CHECK-NEXT: [3,0] . D=========eeeER imull %edx, %ecx # CHECK-NEXT: [3,0] . D=================eeeER . imull %edx, %ecx
# CHECK-NEXT: [3,1] . DeeeeeeE-----R lzcntw (%rsp), %cx # CHECK-NEXT: [3,1] . D================eeeeeeER. lzcntw (%rsp), %cx
# CHECK-NEXT: [3,2] . DeeeeeeE-----R lzcntw 2(%rsp), %cx # CHECK-NEXT: [3,2] . D=================eeeeeeER lzcntw 2(%rsp), %cx
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 6.5 0.3 0.0 imull %edx, %ecx # CHECK-NEXT: 0. 4 9.5 0.3 0.0 imull %edx, %ecx
# CHECK-NEXT: 1. 4 1.0 1.0 2.8 lzcntw (%rsp), %cx # CHECK-NEXT: 1. 4 9.0 0.0 0.0 lzcntw (%rsp), %cx
# CHECK-NEXT: 2. 4 1.0 1.0 2.5 lzcntw 2(%rsp), %cx # CHECK-NEXT: 2. 4 9.5 0.0 0.0 lzcntw 2(%rsp), %cx