AMDGPU: Properly handle shader inputs with split arguments

[arsenm]

Summary

This needs to refer to arguments by their original argument
index, not the argument split index which depends on what
the type splitting decides to do.

Also avoid increment PSInputNum for each split piece.

[mareko]

This is a no-op change, right? Because the previous code also works.

[arsenm]

In D49128#1159099, @mareko wrote:

This is a no-op change, right? Because the previous code also works.

As-is I think this is a no-op. In D49065 the input argument registers start getting split, so there's no longer a 1:1 correspondence.

[arsenm]

Complete change needed to handle other code doing the vector argument splitting

[arsenm]

r337022

lib/Target/AMDGPU/SIISelLowering.cpp

for (unsigned I = 0, E = Ins.size(), PSInputNum = 0; I != E; ++I) {
     const ISD::InputArg &Arg = Ins[I];
 
     // First check if it's a PS input addr.
     if (CallConv == CallingConv::AMDGPU_PS && !Arg.Flags.isInReg() &&
         !Arg.Flags.isByVal() && PSInputNum <= 15) {
 
       if (!Arg.Used && !Info->isPSInputAllocated(PSInputNum)) {
         // We can safely skip PS inputs.
-        Skipped.set(I);
+        Skipped.set(Arg.getOrigArgIndex());
         ++PSInputNum;
         continue;
       }
 
       Info->markPSInputAllocated(PSInputNum);
       if (Arg.Used)
         Info->markPSInputEnabled(PSInputNum);
 
SDValue SITargetLowering::LowerFormalArguments(
   // this to the maximum alignment of the arguments.
   //
   // FIXME: Alignment of explicit arguments totally broken with non-0 explicit
   // kern arg offset.
   const unsigned KernelArgBaseAlign = 16;
 
    for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
     const ISD::InputArg &Arg = Ins[i];
-    if (Skipped[i]) {
+    if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
       InVals.push_back(DAG.getUNDEF(Arg.VT));
       continue;
     }
 
     CCValAssign &VA = ArgLocs[ArgIdx++];
     MVT VT = VA.getLocVT();
 
     if (IsEntryFunc && VA.isMemLoc()) {