[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

[spatel]

Summary

This is almost the same as an existing IR canonicalization in instcombine, so I'm assuming this is a good early generic DAG combine too.

The motivation comes from reduced bit-hacking for select-of-constants in IR after rL331486. We want to restore that functionality in the DAG as noted in the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html

The PPC and AArch tests show that those targets are already doing something similar. x86 will be neutral in the minimal case and generally better when this pattern is extended with other ops as shown in the signbit-shift.ll tests.

Note the asymmetry: I didn't include the (extend (ifneg X)) transform because it already exists in SimplifySelectCC(), and that is verified in the later unchanged tests in the signbit-shift.ll files. Without the 'not' op, the general transform to use a shift is always a win because that's a single instruction.

I don't know if the XCore test diff is a regression, but given that we canonicalize IR to this form, I'd think that could be changed independently if needed.

Alive proofs:
https://rise4fun.com/Alive/ysli

Name: if pos, get -1
  %c = icmp sgt i16 %x, -1
  %r = sext i1 %c to i16
=>
  %n = xor i16 %x, -1
  %r = ashr i16 %n, 15

Name: if pos, get 1
  %c = icmp sgt i16 %x, -1
  %r = zext i1 %c to i16
=>
  %n = xor i16 %x, -1
  %r = lshr i16 %n, 15

[craig.topper]

test/CodeGen/X86/signbit-shift.ll

74 ↗

(On Diff #154229)

Do you have a longer term plan here?

This looks like it could be something like:

shrl $31, %edi
add $41, %edi
mov %edi, %eax

[spatel]

test/CodeGen/X86/signbit-shift.ll

74 ↗

(On Diff #154229)

Right. I think the same problem is visible for the 'ifneg' variant below. I have another patch drafted that would have included the trailing add/sub op, but I saw this minimal pattern, so decided we should squash this first. If this works, then I can follow-up by matching this new pattern that includes a shift.

[spatel]

test/CodeGen/X86/signbit-shift.ll

74 ↗

(On Diff #154229)

I think these are the ideal results for the select tests (for x86 at least, but hopefully all targets):
https://rise4fun.com/Alive/Avq

[lebedev.ri]

Code looks good, but i can't comment on the test changes.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8006 ↗

(On Diff #154229)

We are assuming that we won't get setge <>, 0, because some dagcombine already canonicalizes that?

[spatel]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

8006 ↗

(On Diff #154229)

Correct - that transform is done both in instcombine and TargetLowering::SimplifySetCC():

// Canonicalize GE/LE comparisons to use GT/LT comparisons.

I'll add a comment to make that clear.

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

static SDValue tryToFoldExtOfLoad(SelectionDAG &DAG, DAGCombiner &Combiner,
   } else {
     SDValue Trunc =
         DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), ExtLoad);
     Combiner.CombineTo(LN0, Trunc, ExtLoad.getValue(1));
   }
   return SDValue(N, 0); // Return N so it doesn't get rechecked!
 }
 
+static SDValue foldExtendedSignBitTest(SDNode *N, SelectionDAG &DAG,
+                                       bool LegalOperations) {
+  assert((N->getOpcode() == ISD::SIGN_EXTEND ||
+          N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext");
+
+  SDValue SetCC = N->getOperand(0);
+  if (LegalOperations || SetCC.getOpcode() != ISD::SETCC ||
+      !SetCC.hasOneUse() || SetCC.getValueType() != MVT::i1)
+    return SDValue();
+
+  SDValue X = SetCC.getOperand(0);
+  SDValue Ones = SetCC.getOperand(1);
+  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
+  EVT VT = N->getValueType(0);
+  EVT XVT = X.getValueType();
+  // setge X, C is canonicalized to setgt, so we do not need to match that
+  // pattern. The setlt sibling is folded in SimplifySelectCC() becaus it does
+  // not require the 'not' op.
+  if (CC == ISD::SETGT && isAllOnesConstant(Ones) && VT == XVT) {
+    // Invert and smear/shift the sign bit:
+    // sext i1 (setgt iN X, -1) --> sra (not X), (N - 1)
+    // zext i1 (setgt iN X, -1) --> srl (not X), (N - 1)
+    SDLoc DL(N);
+    SDValue NotX = DAG.getNOT(DL, X, VT);
+    SDValue ShiftAmount = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
+    auto ShiftOpcode = N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
+    return DAG.getNode(ShiftOpcode, DL, VT, NotX, ShiftAmount);
+  }
+  return SDValue();
+}
+
 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
 
   if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
                                               LegalOperations))
     return SDValue(Res, 0);
if (TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT) &&
                                       LN00->getValueType(0), ExtLoad);
           CombineTo(LN00, Trunc, ExtLoad.getValue(1));
         }
         return SDValue(N,0); // Return N so it doesn't get rechecked!
       }
     }
   }
 
+  if (SDValue V = foldExtendedSignBitTest(N, DAG, LegalOperations))
+    return V;
+
   if (N0.getOpcode() == ISD::SETCC) {
     SDValue N00 = N0.getOperand(0);
     SDValue N01 = N0.getOperand(1);
     ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
     EVT N00VT = N0.getOperand(0).getValueType();
 
     // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
     // Only do this before legalize for now.
SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
   if (SDValue ZExtLoad = CombineZExtLogicopShiftLoad(N))
     return ZExtLoad;
 
   // Try to simplify (zext (zextload x)).
   if (SDValue foldedExt = tryToFoldExtOfExtload(
           DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::ZEXTLOAD))
     return foldedExt;
 
+  if (SDValue V = foldExtendedSignBitTest(N, DAG, LegalOperations))
+    return V;
+
   if (N0.getOpcode() == ISD::SETCC) {
     // Only do this before legalize for now.
     if (!LegalOperations && VT.isVector() &&
         N0.getValueType().getVectorElementType() == MVT::i1) {
       EVT N00VT = N0.getOperand(0).getValueType();
       if (getSetCCResultType(N00VT) == N0.getValueType())
         return SDValue();
 

llvm/trunk/test/CodeGen/AArch64/signbit-shift.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
 
 ; If positive...
 
 define i32 @zext_ifpos(i32 %x) {
 ; CHECK-LABEL: zext_ifpos:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #31
-; CHECK-NEXT:    eor w0, w8, #0x1
+; CHECK-NEXT:    mvn w8, w0
+; CHECK-NEXT:    lsr w0, w8, #31
 ; CHECK-NEXT:    ret
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_zext_ifpos(i32 %x) {
 ; CHECK-LABEL: add_zext_ifpos:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #31
-; CHECK-NEXT:    eor w8, w8, #0x1
+; CHECK-NEXT:    mvn w8, w0
+; CHECK-NEXT:    lsr w8, w8, #31
 ; CHECK-NEXT:    add w0, w8, #41 // =41
 ; CHECK-NEXT:    ret
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
   %r = add i32 %e, 41
   ret i32 %r
 }
 
 define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmp w0, #0 // =0
 ; CHECK-NEXT:    mov w8, #41
 ; CHECK-NEXT:    cinc w0, w8, ge
 ; CHECK-NEXT:    ret
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 42, i32 41
   ret i32 %r
 }
 
 define i32 @sext_ifpos(i32 %x) {
 ; CHECK-LABEL: sext_ifpos:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-1
-; CHECK-NEXT:    eor w0, w8, w0, asr #31
+; CHECK-NEXT:    mvn w8, w0
+; CHECK-NEXT:    asr w0, w8, #31
 ; CHECK-NEXT:    ret
   %c = icmp sgt i32 %x, -1
   %e = sext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_sext_ifpos(i32 %x) {
 ; CHECK-LABEL: add_sext_ifpos:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #31
-; CHECK-NEXT:    eor w8, w8, #0x1
+; CHECK-NEXT:    mvn w8, w0
 ; CHECK-NEXT:    mov w9, #42
-; CHECK-NEXT:    sub w0, w9, w8
+; CHECK-NEXT:    sub w0, w9, w8, lsr #31
 ; CHECK-NEXT:    ret
   %c = icmp sgt i32 %x, -1
   %e = sext i1 %c to i32
   %r = add i32 %e, 42
   ret i32 %r
 }
 
 define i32 @sel_ifpos_fval_bigger(i32 %x) {

llvm/trunk/test/CodeGen/AMDGPU/commute-compares.ll

define amdgpu_kernel void @commute_ule_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
   %val = load i32, i32 addrspace(1)* %gep.in
   %cmp = icmp ule i32 %val, 64
   %ext = sext i1 %cmp to i32
   store i32 %ext, i32 addrspace(1)* %gep.out
   ret void
 }
 
 ; GCN-LABEL: {{^}}commute_sgt_neg1_i32:
-; GCN: v_cmp_lt_i32_e32 vcc, -1, v{{[0-9]+}}
+; GCN: v_ashrrev_i32_e32 v2, 31, v2
 define amdgpu_kernel void @commute_sgt_neg1_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
   %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
   %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
   %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
   %val = load i32, i32 addrspace(1)* %gep.in
   %cmp = icmp sgt i32 %val, -1
   %ext = sext i1 %cmp to i32
   store i32 %ext, i32 addrspace(1)* %gep.out

llvm/trunk/test/CodeGen/PowerPC/signbit-shift.ll

; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_zext_ifpos(i32 %x) {
 ; CHECK-LABEL: add_zext_ifpos:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    nor 3, 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
-; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    addi 3, 3, 41
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
   %r = add i32 %e, 41
   ret i32 %r
 }
 
; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %e = sext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_sext_ifpos(i32 %x) {
 ; CHECK-LABEL: add_sext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    srawi 3, 3, 31
 ; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    srawi 3, 3, 31
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %e = sext i1 %c to i32
   %r = add i32 %e, 42
   ret i32 %r
 }
 

llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll

entry:
   store i64 %conv1, i64* @glob, align 8
   ret void
 }
 
 define void @test_igesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_igesll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob, align 8
   ret void
 }
 
 define void @test_igesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_igesll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    sradi r3, r3, 63
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    std r3,
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   %conv1 = sext i1 %cmp to i64
   store i64 %conv1, i64* @glob, align 8
   ret void
 }

llvm/trunk/test/CodeGen/PowerPC/testComparesllgesll.ll

entry:
   %cmp = icmp sge i64 %a, %b
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
 }
 
 define i64 @test_llgesll_z(i64 %a) {
 ; CHECK-LABEL: test_llgesll_z:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
 }
 
 define i64 @test_llgesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_llgesll_sext_z:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
 }
 
 define void @test_llgesll_store(i64 %a, i64 %b) {
entry:
   store i64 %conv1, i64* @glob, align 8
   ret void
 }
 
 define void @test_llgesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgesll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob, align 8
   ret void
 }
 
 define void @test_llgesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgesll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    sradi r3, r3, 63
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   %conv1 = sext i1 %cmp to i64
   store i64 %conv1, i64* @glob, align 8
   ret void
 }

llvm/trunk/test/CodeGen/X86/select.ll

 ; ATOM-NEXT:    testl %edi, %edi
 ; ATOM-NEXT:    setns %al
 ; ATOM-NEXT:    shlq $4, %rax
 ; ATOM-NEXT:    fldt (%rax,%rcx)
 ; ATOM-NEXT:    retq
 ;
 ; MCU-LABEL: test7:
 ; MCU:       # %bb.0:
-; MCU-NEXT:    xorl %ecx, %ecx
-; MCU-NEXT:    testl %eax, %eax
-; MCU-NEXT:    setns %cl
-; MCU-NEXT:    shll $4, %ecx
-; MCU-NEXT:    fldt {{\.LCPI.*}}(%ecx)
+; MCU-NEXT:    notl %eax
+; MCU-NEXT:    shrl $27, %eax
+; MCU-NEXT:    andl $-16, %eax
+; MCU-NEXT:    fldt {{\.LCPI.*}}(%eax)
 ; MCU-NEXT:    retl
   %tmp9 = icmp sgt i32 %tmp8, -1
   %retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000
   ret x86_fp80 %retval
 }
 
 ; widening select v6i32 and then a sub
 define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwind {

llvm/trunk/test/CodeGen/X86/selectcc-to-shiftand.ll

 
 ; Flipping the comparison condition can be handled by getting the bitwise not of the sign mask.
 
 ; Compare if positive and select of constants where one constant is zero.
 
 define i32 @pos_sel_constants(i32 %a) {
 ; CHECK-NOBMI-LABEL: pos_sel_constants:
 ; CHECK-NOBMI:       # %bb.0:
-; CHECK-NOBMI-NEXT:    xorl %eax, %eax
-; CHECK-NOBMI-NEXT:    testl %edi, %edi
-; CHECK-NOBMI-NEXT:    setns %al
-; CHECK-NOBMI-NEXT:    leal (%rax,%rax,4), %eax
+; CHECK-NOBMI-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NOBMI-NEXT:    notl %edi
+; CHECK-NOBMI-NEXT:    shrl $31, %edi
+; CHECK-NOBMI-NEXT:    leal (%rdi,%rdi,4), %eax
 ; CHECK-NOBMI-NEXT:    retq
 ;
 ; CHECK-BMI-LABEL: pos_sel_constants:
 ; CHECK-BMI:       # %bb.0:
-; CHECK-BMI-NEXT:    xorl %eax, %eax
-; CHECK-BMI-NEXT:    testl %edi, %edi
-; CHECK-BMI-NEXT:    setns %al
-; CHECK-BMI-NEXT:    leal (%rax,%rax,4), %eax
+; CHECK-BMI-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-BMI-NEXT:    notl %edi
+; CHECK-BMI-NEXT:    shrl $31, %edi
+; CHECK-BMI-NEXT:    leal (%rdi,%rdi,4), %eax
 ; CHECK-BMI-NEXT:    retq
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 5, i32 0
   ret i32 %retval
 }
 
 ; Compare if positive and select of constants where one constant is zero and the other is a single bit.
 
 define i32 @pos_sel_special_constant(i32 %a) {
 ; CHECK-NOBMI-LABEL: pos_sel_special_constant:
 ; CHECK-NOBMI:       # %bb.0:
-; CHECK-NOBMI-NEXT:    xorl %eax, %eax
-; CHECK-NOBMI-NEXT:    testl %edi, %edi
-; CHECK-NOBMI-NEXT:    setns %al
-; CHECK-NOBMI-NEXT:    shll $9, %eax
+; CHECK-NOBMI-NEXT:    notl %edi
+; CHECK-NOBMI-NEXT:    shrl $22, %edi
+; CHECK-NOBMI-NEXT:    andl $512, %edi # imm = 0x200
+; CHECK-NOBMI-NEXT:    movl %edi, %eax
 ; CHECK-NOBMI-NEXT:    retq
 ;
 ; CHECK-BMI-LABEL: pos_sel_special_constant:
 ; CHECK-BMI:       # %bb.0:
-; CHECK-BMI-NEXT:    xorl %eax, %eax
-; CHECK-BMI-NEXT:    testl %edi, %edi
-; CHECK-BMI-NEXT:    setns %al
-; CHECK-BMI-NEXT:    shll $9, %eax
+; CHECK-BMI-NEXT:    notl %edi
+; CHECK-BMI-NEXT:    shrl $22, %edi
+; CHECK-BMI-NEXT:    andl $512, %edi # imm = 0x200
+; CHECK-BMI-NEXT:    movl %edi, %eax
 ; CHECK-BMI-NEXT:    retq
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 512, i32 0
   ret i32 %retval
 }
 
 ; Compare if positive and select variable or zero.
 

llvm/trunk/test/CodeGen/X86/signbit-shift.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 ; If positive...
 
 define i32 @zext_ifpos(i32 %x) {
 ; CHECK-LABEL: zext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    testl %edi, %edi
-; CHECK-NEXT:    setns %al
+; CHECK-NEXT:    notl %edi
+; CHECK-NEXT:    shrl $31, %edi
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_zext_ifpos(i32 %x) {
 ; CHECK-LABEL: add_zext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    testl %edi, %edi
-; CHECK-NEXT:    setns %al
-; CHECK-NEXT:    addl $41, %eax
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    notl %edi
+; CHECK-NEXT:    shrl $31, %edi
+; CHECK-NEXT:    leal 41(%rdi), %eax
 ; CHECK-NEXT:    retq
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
   %r = add i32 %e, 41
   ret i32 %r
 }
 
 define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    testl %edi, %edi
-; CHECK-NEXT:    setns %al
-; CHECK-NEXT:    addl $41, %eax
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    notl %edi
+; CHECK-NEXT:    shrl $31, %edi
+; CHECK-NEXT:    leal 41(%rdi), %eax
 ; CHECK-NEXT:    retq
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 42, i32 41
   ret i32 %r
 }
 
 define i32 @sext_ifpos(i32 %x) {
 ; CHECK-LABEL: sext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    testl %edi, %edi
-; CHECK-NEXT:    setns %al
-; CHECK-NEXT:    negl %eax
+; CHECK-NEXT:    notl %edi
+; CHECK-NEXT:    sarl $31, %edi
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %c = icmp sgt i32 %x, -1
   %e = sext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_sext_ifpos(i32 %x) {
 ; CHECK-LABEL: add_sext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    testl %edi, %edi
-; CHECK-NEXT:    setns %cl
+; CHECK-NEXT:    notl %edi
+; CHECK-NEXT:    shrl $31, %edi
 ; CHECK-NEXT:    movl $42, %eax
-; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    subl %edi, %eax
 ; CHECK-NEXT:    retq
   %c = icmp sgt i32 %x, -1
   %e = sext i1 %c to i32
   %r = add i32 %e, 42
   ret i32 %r
 }
 
 define i32 @sel_ifpos_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_fval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    testl %edi, %edi
-; CHECK-NEXT:    setns %cl
+; CHECK-NEXT:    notl %edi
+; CHECK-NEXT:    shrl $31, %edi
 ; CHECK-NEXT:    movl $42, %eax
-; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    subl %edi, %eax
 ; CHECK-NEXT:    retq
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 41, i32 42
   ret i32 %r
 }
 
 ; If negative...
 

llvm/trunk/test/CodeGen/XCore/ashr.ll

 ; CHECK: ldc r0, 17
 
 define i32 @f5(i32 %a) nounwind {
         %1 = icmp sge i32 %a, 0
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 ; CHECK-LABEL: f5:
-; CHECK-NEXT: ashr r0, r0, 32
-; CHECK-NEXT: eq r0, r0, 0
+; CHECK-NEXT: not r0, r0
+; CHECK-NEXT: mkmsk r1, 5
+; CHECK-NEXT: shr r0, r0, r1