[WebAssembly] Update comments for non-splat pow2 vector test case

[aheejin]

Summary

After rL335727, (sdiv X, 1) is treated as a special case, so we can
safely transform 'sdiv's in non-splat pow vectors into 'shr's even when
some of its entries are '1'. The test expectations have been already
fixed in rL335771, but the comments were out of date.

Also changed the filename from vector_sdiv.ll to vector-sdiv.ll to
be consistent with other test file names.

[RKSimon]

As divisor = 1 is a special case, I think it's be better to keep the test and modify the comment + checks to ensure its doing what it should.

[aheejin]

Thanks. I'm little not sure if you remember the history, so FYI, this test case was added in D46161 (rL329525) to make sure the case with 1's in a vector should NOT be converted to 'shr's and remain as 'sdiv's, in which case shifting a value by the number of its bit widths becomes undef. But after rL335727, you fixed it so now even vectors with 1's in there can be correctly treated as pow2 non-splat vectors, so this test started failing. So in rL335771 someone else (not me) fixed the expectation to 'shr's, so the purpose this case was added is now unnecessary.

Do you mean, even if the original purpose of this case is not there anymore, it's still better to keep this case after modifying the comments?

[RKSimon]

In D48692#1146943, @aheejin wrote:

Thanks. I'm little not sure if you remember the history, so FYI, this test case was added in D46161 (rL329525) to make sure the case with 1's in a vector should NOT be converted to 'shr's and remain as 'sdiv's, in which case shifting a value by the number of its bit widths becomes undef. But after rL335727, you fixed it so now even vectors with 1's in there can be correctly treated as pow2 non-splat vectors, so this test started failing. So in rL335771 someone else (not me) fixed the expectation to 'shr's, so the purpose this case was added is now unnecessary.

Do you mean, even if the original purpose of this case is not there anymore, it's still better to keep this case after modifying the comments?

I think I've fixed the test for you now at rL335884 - the test now passes again, so you can probably safely keep it. I'd recommend updating the checks to check the (immediate) shift amounts if that is possible - to ensure they match the 3 'real' divisors.

[aheejin]

Oh, what I meant by the test started failing is not about rL335821 but rL335727. I wasn't even aware of getSetCCResultType thing when I posted the previous comment.. Anyway then I'll update the comment.

[aheejin]

• Revive vector_sdiv.ll and changed its name to vector-sdiv.ll
• Update comments

[aheejin]

• Remove -elf triple which is not needed anymore

[aheejin]

• Revive -elf.. this is getting removed in D48744

[RKSimon]

LGTM

test/CodeGen/WebAssembly/vector-sdiv.ll

 ; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
-target triple = "wasm32-unknown-unknown-elf"
+target triple = "wasm32-unknown-unknown"
 
-; Because there is a 1 in the vector, sdiv should not be reduced to shifts.
+; This should be treated as a non-splat vector of pow2 divisor, so sdivs will be
+; transformed to shrs in DAGCombiner. There will be 4 stores and 3 shrs (For '1'
+; entry we don't need a shr).
 
 ; CHECK-LABEL: vector_sdiv:
 ; CHECK-DAG:  i32.store
 ; CHECK-DAG:  i32.shr_u
 ; CHECK-DAG:  i32.store
 ; CHECK-DAG:  i32.shr_u
 ; CHECK-DAG:  i32.store
 ; CHECK-DAG:  i32.shr_u
 ; CHECK-DAG:  i32.store
 define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) {
 entry:
   %0 = load <4 x i32>, <4 x i32>* %y, align 16
   %div = sdiv <4 x i32> %0, <i32 1, i32 4, i32 2, i32 8>
   store <4 x i32> %div, <4 x i32>* %x, align 16
   ret void
 }