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[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor
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Authored by aheejin on Apr 26 2018, 5:19 PM.

Details

Summary

D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined.

Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.

(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)

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Repository
rL LLVM

Event Timeline

aheejin created this revision.Apr 26 2018, 5:19 PM
aheejin edited the summary of this revision. (Show Details)Apr 26 2018, 5:20 PM
RKSimon accepted this revision.Apr 27 2018, 6:00 AM

LGTM

This revision is now accepted and ready to land.Apr 27 2018, 6:00 AM
jgravelle-google accepted this revision.Apr 27 2018, 2:42 PM
This revision was automatically updated to reflect the committed changes.