[RegisterCoalescer] Improve handling of COPY instructions with identical value numbers

[tpr]

Summary

This subsumes Krzysztof's D48102, which itself was an alternative to D48032.

It does not include Krzysztof's 'Fix the "cannot join subranges" issue
caused by redefining an undef value' part of D48102, on the basis that
there is a different fix for that on D35073 that we need to refine and
upstream.

Change-Id: I73363db649916046eff58854c957d41a06157b3b

[kparzysz]

I don't want to be spending time reviewing more alternatives at this point. I'm familiar with what I've started and I fixed all known problems. I still need to analyze the problems in detail either way and reviewing additional patches is just more work for me.

lib/CodeGen/RegisterCoalescer.cpp

1647

I have fixed this differently in the previous review.

2830

This is an overkill.

[tpr]

OK, I'll kill this one.

lib/CodeGen/RegisterCoalescer.cpp

for (const LiveInterval::SubRange &SR : SrcLI.subranges()) {
       if ((SR.LaneMask & SrcMask).none())
         continue;
       if (SR.liveAt(Idx))
         return false;
     }
   } else if (SrcLI.liveAt(Idx))
     return false;
 
-  LLVM_DEBUG(dbgs() << "\tEliminating copy of <undef> value\n");
-
-  // Remove any DstReg segments starting at the instruction.
+  // If the undef copy defines a live-out value (i.e. an input to a PHI def),
+  // then replace it with an IMPLICIT_DEF.
   LiveInterval &DstLI = LIS->getInterval(DstReg);
   SlotIndex RegIndex = Idx.getRegSlot();
+  LiveRange::Segment *Seg = DstLI.getSegmentContaining(RegIndex);
+  assert(Seg != nullptr && "No segment for defining instruction");
+  if (VNInfo *V = DstLI.getVNInfoAt(Seg->end)) {
+    if (V->isPHIDef()) {
+      CopyMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
+      for (unsigned i = CopyMI->getNumOperands(); i != 0; --i) {
+        MachineOperand &MO = CopyMI->getOperand(i-1);
+        if (MO.isReg() && MO.isUse())
+          CopyMI->RemoveOperand(i-1);
+      }
+      LLVM_DEBUG(dbgs() << "\tReplaced copy of <undef> value with an "
+                           "implicit def\n");
+      return false;
+    }
+  }
+
+  // Remove any DstReg segments starting at the instruction.
+  LLVM_DEBUG(dbgs() << "\tEliminating copy of <undef> value\n");
+
   // Remove value or merge with previous one in case of a subregister def.
   if (VNInfo *PrevVNI = DstLI.getVNInfoAt(Idx)) {
     VNInfo *VNI = DstLI.getVNInfoAt(RegIndex);
     DstLI.MergeValueNumberInto(VNI, PrevVNI);
 
     // The affected subregister segments can be removed.
     LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx);
     for (LiveInterval::SubRange &SR : DstLI.subranges()) {
if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
     return true;
   }
 
   // Eliminate undefs.
   if (!CP.isPhys() && eliminateUndefCopy(CopyMI)) {
     deleteInstr(CopyMI);
     return false;  // Not coalescable.
   }
+  if (CopyMI->isImplicitDef()) {
+    // Not coalesceable; eliminateUndefCopy turned it into implicit_def.
+    return false;
+  }
 
   // Coalesced copies are normally removed immediately, but transformations
   // like removeCopyByCommutingDef() can inadvertently create identity copies.
   // When that happens, just join the values and remove the copy.
   if (CP.getSrcReg() == CP.getDstReg()) {
     LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
     LLVM_DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
     const SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
struct Val {
 
     /// True when the live range of this value will be pruned because of an
     /// overlapping CR_Replace value in the other live range.
     bool Pruned = false;
 
     /// True once Pruned above has been computed.
     bool PrunedComputed = false;
 
+    /// True if this value is determined to be identical to OtherVNI
+    /// (in valuesIdentical). This is used with CR_Erase where the erased
+    /// copy is redundant, i.e. the source value is already the same as
+    /// the destination. In such cases the subranges need to be updated
+    /// properly. See comment at pruneSubRegValues for more info.
+    bool Identical = false;
+
     Val() = default;
 
     bool isAnalyzed() const { return WriteLanes.any(); }
   };
 
   /// One entry per value number in LI.
   SmallVector<Val, 8> Vals;
 
std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
   return std::make_pair(VNI, Reg);
 }
 
 bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
                                const JoinVals &Other) const {
   const VNInfo *Orig0;
   unsigned Reg0;
   std::tie(Orig0, Reg0) = followCopyChain(Value0);
-  if (Orig0 == Value1)
+  if (Orig0 == Value1 && Reg0 == Other.Reg)
     return true;
 
   const VNInfo *Orig1;
   unsigned Reg1;
   std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
 
   // The values are equal if they are defined at the same place and use the
   // same register. Note that we cannot compare VNInfos directly as some of
if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
     return CR_Keep;
 
   // Handle the case where VNI and OtherVNI can be proven to be identical:
   //
   //   %other = COPY %ext
   //   %this  = COPY %ext <-- Erase this copy
   //
   if (DefMI->isFullCopy() && !CP.isPartial()
-      && valuesIdentical(VNI, V.OtherVNI, Other))
+      && valuesIdentical(VNI, V.OtherVNI, Other)) {
+    V.Identical = true;
     return CR_Erase;
+  }
 
   // If the lanes written by this instruction were all undef in OtherVNI, it is
   // still safe to join the live ranges. This can't be done with a simple value
   // mapping, though - OtherVNI will map to multiple values:
   //
   //   1 %dst:ssub0 = FOO                <-- OtherVNI
   //   2 %src = BAR                      <-- VNI
   //   3 %dst:ssub1 = COPY killed %src    <-- Eliminate this copy.
case CR_Merge:
       break;
     case CR_Unresolved:
     case CR_Impossible:
       llvm_unreachable("Unresolved conflicts");
     }
   }
 }
 
+/// Consider the following situation when coalescing the copy between
+/// %31 and %45 at 800. (The vertical lines represent live range segments.)
+///
+///                              Main range         Subrange 0004 (sub2)
+///                              %31    %45           %31    %45
+///  544    %45 = COPY %28               +                    +
+///                                      | v1                 | v1
+///  560B bb.1:                          +                    +
+///  624        = %45.sub2               | v2                 | v2
+///  800    %31 = COPY %45        +      +             +      +
+///                               | v0                 | v0
+///  816    %31.sub1 = ...        +                    |
+///  880    %30 = COPY %31        | v1                 +
+///  928    %45 = COPY %30        |      +                    +
+///                               |      | v0                 | v0  <--+
+///  992B   ; backedge -> bb.1    |      +                    +        |
+/// 1040        = %31.sub0        +                                    |
+///                                                 This value must remain
+///                                                 live-out!
+///
+/// Assuming that %31 is coalesced into %45, the copy at 928 becomes
+/// redundant, since it copies the value from %45 back into it. The
+/// conflict resolution for the main range determines that %45.v0 is
+/// to be erased, which is ok since %31.v1 is identical to it.
+/// The problem happens with the subrange for sub2: it has to be live
+/// on exit from the block, but since 928 was actually a point of
+/// definition of %45.sub2, %45.sub2 was not live immediately prior
+/// to that definition. As a result, when 928 was erased, the value v0
+/// for %45.sub2 was pruned in pruneSubRegValues. Consequently, an
+/// IMPLICIT_DEF was inserted as a "backedge" definition for %45.sub2,
+/// providing an incorrect value to the use at 624.
+///
+/// Since the main-range values %31.v1 and %45.v0 were proved to be
+/// identical, the corresponding values in subranges must also be the
+/// same. A redundant copy is removed because it's not needed, and not
+/// because it copied an undefined value, so any liveness that originated
+/// from that copy cannot disappear. When pruning a value that started
+/// at the removed copy, the corresponding identical value must be
+/// extended to replace it.
+///
+/// There are cases where there is another value "in the way" that is also being
+/// pruned here. To avoid that causing liveness to be extended incorrectly, we
+/// do all the pruning first and then the extensions afterwards.
+//
 void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
-  // Look for values being erased.
   bool DidPrune = false;
+  // For each subrange in turn...
+  for (LiveInterval::SubRange &S : LI.subranges()) {
+    // Remember end points from pruned values that need liveness extending to
+    // them.
+    SmallVector<SlotIndex, 8> EndPoints;
+    // Also remember pruned defs that required extension, so we can assert that
+    // liveness was extended as we expected.
+    SmallVector<std::pair<SlotIndex, SlotIndex>, 8> PrunedDefs;
+
+    // Look for values being erased.
     for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
+      Val &V = Vals[i];
       // We should trigger in all cases in which eraseInstrs() does something.
-    // match what eraseInstrs() is doing, print a message so
-    if (Vals[i].Resolution != CR_Erase &&
-        (Vals[i].Resolution != CR_Keep || !Vals[i].ErasableImplicitDef ||
-         !Vals[i].Pruned))
+      if (V.Resolution != CR_Erase &&
+          (V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned))
         continue;
 
-    // Check subranges at the point where the copy will be removed.
+      // Check this subrange at the point where the copy will be removed.
       SlotIndex Def = LR.getValNumInfo(i)->def;
+      SlotIndex OtherDef;
+      if (V.Identical)
+        OtherDef = V.OtherVNI->def;
+
       // Print message so mismatches with eraseInstrs() can be diagnosed.
-    LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def
-                      << '\n');
-    for (LiveInterval::SubRange &S : LI.subranges()) {
+      LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def << '\n');
+
       LiveQueryResult Q = S.Query(Def);
 
       // If a subrange starts at the copy then an undefined value has been
       // copied and we must remove that subrange value as well.
       VNInfo *ValueOut = Q.valueOutOrDead();
       if (ValueOut != nullptr && Q.valueIn() == nullptr) {
         LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
                           << " at " << Def << "\n");
+        if (V.Identical && S.Query(OtherDef).valueOut()) {
+          // If V is identical to V.OtherVNI (and S was live at OtherDef),
+          // then we can't simply prune V from S. V needs to be replaced
+          // with V.OtherVNI. Remember the end points for later extension.
+          LLVM_DEBUG(dbgs() << "\t\t  (will extend to end points)\n");
+          auto SizeBefore = EndPoints.size();
+          LIS->pruneValue(S, Def, &EndPoints);
+          if (SizeBefore != EndPoints.size())
+            PrunedDefs.push_back(std::pair<SlotIndex, SlotIndex>(Def, OtherDef));
+        } else
           LIS->pruneValue(S, Def, nullptr);
         DidPrune = true;
         // Mark value number as unused.
         ValueOut->markUnused();
         continue;
       }
       // If a subrange ends at the copy, then a value was copied but only
       // partially used later. Shrink the subregister range appropriately.
       if (Q.valueIn() != nullptr && Q.valueOut() == nullptr) {
         LLVM_DEBUG(dbgs() << "\t\tDead uses at sublane "
                           << PrintLaneMask(S.LaneMask) << " at " << Def
                           << "\n");
         ShrinkMask |= S.LaneMask;
       }
     }
+    // Now re-extend liveness to end points.
+    if (!EndPoints.empty()) {
+      LLVM_DEBUG(dbgs() << "\t\tExtending to EndPoints:";
+            for (auto &EP : EndPoints)
+              dbgs() << " " << EP;
+            dbgs() << "\n");
+      LIS->extendToIndices(S, EndPoints);
+      LLVM_DEBUG(dbgs() << "\t\t  after extendToIndices:  " << S << "\n");
+#ifndef NDEBUG
+      // Assert that liveness has been extended as expected.
+      for (auto DefPair : PrunedDefs) {
+        SlotIndex Def = DefPair.first;
+        SlotIndex OtherDef = DefPair.second;
+        // Make sure that the value at Def is really V.OtherVNI.
+        LiveRange::iterator Id = S.find(OtherDef);
+        LiveRange::iterator T = S.find(Def);
+        assert(Id != S.end() && T != S.end() && T->valno == Id->valno);
+      }
+#endif
+    }
   }
   if (DidPrune)
     LI.removeEmptySubRanges();
 }
 
 /// Check if any of the subranges of @p LI contain a definition at @p Def.
 static bool isDefInSubRange(LiveInterval &LI, SlotIndex Def) {
   for (LiveInterval::SubRange &SR : LI.subranges()) {

test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir

+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+
+# GCN: {{^body}}
+
+---
+name: foo
+tracksRegLiveness: true
+body: |
+  bb.0:
+    successors: %bb.2
+
+    %0:sreg_32_xm0 = S_MOV_B32 1
+    %1:vgpr_32 = COPY %0
+    INLINEASM &"; %1", 1, 327690, def %1, 2147483657, %1(tied-def 3)
+    %2:sreg_64 = V_CMP_NE_U32_e64 0, %1, implicit $exec
+    undef %3.sub0:sreg_128 = COPY %0
+    %3.sub1:sreg_128 = COPY %0
+    %3.sub2:sreg_128 = COPY %0
+    %4:sreg_128 = COPY %3
+    %5:vgpr_32 = V_MOV_B32_e32 -64, implicit $exec
+    %6:vreg_128 = COPY %4
+    %7:sreg_32_xm0 = S_AND_B32 target-flags(amdgpu-gotprel) 1, %2.sub0, implicit-def dead $scc
+    %8:sreg_32_xm0 = S_MOV_B32 0
+    %9:vgpr_32 = COPY %5
+    %10:vreg_128 = COPY %6
+    S_BRANCH %bb.2
+
+  bb.1:
+    %11:vgpr_32 = V_OR_B32_e32 %12.sub0, %12.sub1, implicit $exec
+    %13:vgpr_32 = V_OR_B32_e32 %11, %12.sub2, implicit $exec
+    %14:vgpr_32 = V_AND_B32_e32 1, %13, implicit $exec
+    %15:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %14, implicit $exec
+    %16:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %15, implicit $exec
+    BUFFER_STORE_DWORD_OFFEN_exact %16, undef %17:vgpr_32, undef %18:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into constant-pool, align 1, addrspace 4)
+    S_ENDPGM
+
+  bb.2:
+    successors: %bb.3, %bb.4
+
+    %19:sreg_64 = V_CMP_EQ_U32_e64 1, %7, implicit $exec
+    %20:sreg_64 = COPY $exec, implicit-def $exec
+    %21:sreg_64 = S_AND_B64 %20, %19, implicit-def dead $scc
+    $exec = S_MOV_B64_term %21
+    SI_MASK_BRANCH %bb.4, implicit $exec
+    S_BRANCH %bb.3
+
+  bb.3:
+    successors: %bb.4
+
+    undef %22.sub0:sreg_128 = COPY %8
+    %22.sub1:sreg_128 = COPY %8
+    %22.sub2:sreg_128 = COPY %8
+    %23:sreg_128 = COPY %22
+    %24:vreg_128 = COPY %23
+    %10:vreg_128 = COPY %24
+
+  bb.4:
+    successors: %bb.5
+
+    $exec = S_OR_B64 $exec, %20, implicit-def $scc
+
+  bb.5:
+    successors: %bb.7, %bb.6
+
+    S_CBRANCH_SCC0 %bb.7, implicit undef $scc
+
+  bb.6:
+    successors: %bb.9
+
+    %12:vreg_128 = COPY %10
+    S_BRANCH %bb.9
+
+  bb.7:
+    successors: %bb.8, %bb.10
+
+    %25:vgpr_32 = V_AND_B32_e32 target-flags(amdgpu-gotprel32-hi) 1, %10.sub2, implicit $exec
+    %26:sreg_64 = V_CMP_EQ_U32_e64 1, %25, implicit $exec
+    %27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %28:vreg_1 = COPY %27
+    %29:sreg_64 = COPY $exec, implicit-def $exec
+    %30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc
+    $exec = S_MOV_B64_term %30
+    SI_MASK_BRANCH %bb.10, implicit $exec
+    S_BRANCH %bb.8
+
+  bb.8:
+    successors: %bb.10
+
+    %31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
+    %34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec
+    %35:vgpr_32 = V_CNDMASK_B32_e64 0, -1, %34, implicit $exec
+    %28:vreg_1 = COPY %35
+    S_BRANCH %bb.10
+
+  bb.9:
+    successors: %bb.11
+
+    S_BRANCH %bb.11
+
+  bb.10:
+    successors: %bb.9
+
+    $exec = S_OR_B64 $exec, %29, implicit-def $scc
+    %36:vreg_1 = COPY %28
+    %37:sreg_64_xexec = V_CMP_NE_U32_e64 0, %36, implicit $exec
+    %38:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %37, implicit $exec
+    %39:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    undef %40.sub0:vreg_128 = COPY %39
+    %40.sub1:vreg_128 = COPY %39
+    %40.sub2:vreg_128 = COPY %38
+    %41:vreg_128 = COPY %40
+    %12:vreg_128 = COPY %41
+    S_BRANCH %bb.9
+
+  bb.11:
+    successors: %bb.2, %bb.1
+
+    %42:vgpr_32 = V_ADD_I32_e32 32, %9, implicit-def dead $vcc, implicit $exec
+    V_CMP_EQ_U32_e32 0, %42, implicit-def $vcc, implicit $exec
+    %43:vgpr_32 = COPY %42
+    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
+    %44:vreg_128 = COPY %12
+    %9:vgpr_32 = COPY %43
+    %10:vreg_128 = COPY %44
+    S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
+    S_BRANCH %bb.2
+
+...

test/CodeGen/AMDGPU/coalescing-subranges-another-copymi-not-live.mir

+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+
+# With one version of the D48102 fix, this test failed with
+# Assertion failed: (ValNo && "CopyMI input register not live"), function reMaterializeTrivialDef, file ../lib/CodeGen/RegisterCoalescer.cpp, line 1107.
+
+# GCN: {{^body}}
+
+--- |
+  ; ModuleID = 'bugpoint-reduced-simplified.bc'
+  target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+  target triple = "amdgcn--amdpal"
+  
+  ; Function Attrs: nounwind readnone speculatable
+  declare float @llvm.minnum.f32(float, float) #0
+  
+  ; Function Attrs: nounwind
+  define dllexport amdgpu_cs void @_amdgpu_cs_main(<3 x i32>) local_unnamed_addr #1 !spirv.ExecutionModel !1 {
+  .entry:
+    br i1 undef, label %4, label %1, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:1:                                      ; preds = %.entry
+    br i1 undef, label %3, label %2, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:2:                                      ; preds = %1
+    br label %3, !structurizecfg.uniform !2
+  
+  ; <label>:3:                                      ; preds = %2, %1
+    br i1 undef, label %.lr.ph2597, label %4, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  .lr.ph2597:                                       ; preds = %3
+    br label %4, !structurizecfg.uniform !2
+  
+  ; <label>:4:                                      ; preds = %.lr.ph2597, %3, %.entry
+    %5 = shufflevector <3 x i32> %0, <3 x i32> undef, <2 x i32> <i32 0, i32 1>
+    %6 = uitofp <2 x i32> %5 to <2 x float>
+    %7 = fadd reassoc nnan arcp contract <2 x float> %6, <float 5.000000e-01, float 5.000000e-01>
+    %8 = fmul reassoc nnan arcp contract <2 x float> zeroinitializer, %7
+    %x1.i = extractelement <2 x float> %8, i32 1
+    %9 = call float @llvm.amdgcn.fmed3.f32(float %x1.i, float 0.000000e+00, float 1.000000e+00) #5
+    %10 = insertelement <2 x float> undef, float %9, i32 1
+    %11 = fmul reassoc nnan arcp contract <2 x float> %10, zeroinitializer
+    %12 = fptoui <2 x float> %11 to <2 x i32>
+    %13 = sitofp <2 x i32> %12 to <2 x float>
+    %14 = fptoui <2 x float> %13 to <2 x i32>
+    %15 = lshr <2 x i32> %14, <i32 4, i32 4>
+    %16 = extractelement <2 x i32> %15, i32 0
+    %__llpc_global_proxy_r0.4.vec.insert = insertelement <4 x i32> undef, i32 %16, i32 1
+    br i1 undef, label %22, label %17, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:17:                                     ; preds = %4
+    br i1 undef, label %22, label %.lr.ph2577, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  .lr.ph2577:                                       ; preds = %17
+    br i1 undef, label %18, label %._crit_edge2563, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:18:                                     ; preds = %.lr.ph2577
+    br i1 undef, label %19, label %21, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:19:                                     ; preds = %18
+    br i1 undef, label %21, label %20, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:20:                                     ; preds = %19
+    br label %21, !structurizecfg.uniform !2
+  
+  ; <label>:21:                                     ; preds = %20, %19, %18
+    br label %._crit_edge2563, !structurizecfg.uniform !2
+  
+  ._crit_edge2563:                                  ; preds = %21, %.lr.ph2577
+    br label %22, !structurizecfg.uniform !2
+  
+  ; <label>:22:                                     ; preds = %._crit_edge2563, %17, %4
+    %__llpc_global_proxy_r0.0 = phi <4 x i32> [ %__llpc_global_proxy_r0.4.vec.insert, %4 ], [ zeroinitializer, %._crit_edge2563 ], [ zeroinitializer, %17 ]
+    br i1 undef, label %23, label %Flow2, !amdgpu.uniform !2
+  
+  ; <label>:23:                                     ; preds = %22
+    br i1 undef, label %24, label %._crit_edge2538, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:24:                                     ; preds = %23
+    br i1 undef, label %._crit_edge2515, label %25, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:25:                                     ; preds = %24
+    br i1 undef, label %26, label %28, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:26:                                     ; preds = %25
+    br i1 undef, label %27, label %28, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:27:                                     ; preds = %26
+    br label %28, !structurizecfg.uniform !2
+  
+  ; <label>:28:                                     ; preds = %27, %26, %25
+    br label %._crit_edge2515, !structurizecfg.uniform !2
+  
+  ._crit_edge2515:                                  ; preds = %28, %24
+    br label %._crit_edge2538, !structurizecfg.uniform !2
+  
+  Flow2:                                            ; preds = %._crit_edge2499, %22
+    %29 = phi <4 x i32> [ %50, %._crit_edge2499 ], [ undef, %22 ]
+    %30 = phi <4 x i32> [ %__llpc_global_proxy_r0.0.vec.insert326, %._crit_edge2499 ], [ %__llpc_global_proxy_r0.0, %22 ]
+    br label %51
+  
+  ._crit_edge2538:                                  ; preds = %._crit_edge2515, %23
+    %__llpc_global_proxy_r0.4.vec.extract349 = extractelement <4 x i32> %__llpc_global_proxy_r0.0, i32 1
+    %31 = mul i32 %__llpc_global_proxy_r0.4.vec.extract349, 7
+    br i1 undef, label %32, label %Flow1, !amdgpu.uniform !2
+  
+  ; <label>:32:                                     ; preds = %._crit_edge2538
+    %33 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %31, i32 0, i1 false, i1 false) #5
+    %bc2345 = bitcast <4 x float> %33 to <4 x i32>
+    %__llpc_global_proxy_r8.12.vec.extract17052472 = extractelement <4 x i32> %bc2345, i32 0
+    %34 = icmp eq i32 %__llpc_global_proxy_r8.12.vec.extract17052472, 0
+    %35 = xor i1 %34, true
+    %36 = call { i1, i64 } @llvm.amdgcn.if(i1 %35)
+    %37 = extractvalue { i1, i64 } %36, 0
+    %38 = extractvalue { i1, i64 } %36, 1
+    br i1 %37, label %39, label %Flow
+  
+  ; <label>:39:                                     ; preds = %32
+    br i1 undef, label %40, label %42, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:40:                                     ; preds = %39
+    br i1 undef, label %41, label %42, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:41:                                     ; preds = %40
+    br label %42, !structurizecfg.uniform !2
+  
+  Flow:                                             ; preds = %42, %32
+    call void @llvm.amdgcn.end.cf(i64 %38)
+    br label %._crit_edge2480
+  
+  ; <label>:42:                                     ; preds = %41, %40, %39
+    br label %Flow
+  
+  Flow1:                                            ; preds = %._crit_edge2480, %._crit_edge2538
+    %43 = phi <4 x i32> [ <i32 0, i32 0, i32 0, i32 undef>, %._crit_edge2480 ], [ zeroinitializer, %._crit_edge2538 ]
+    %__llpc_global_proxy_r0.0.vec.insert326 = insertelement <4 x i32> %__llpc_global_proxy_r0.0, i32 %31, i32 0
+    br label %._crit_edge2499
+  
+  ._crit_edge2480:                                  ; preds = %Flow
+    br label %Flow1
+  
+  ._crit_edge2499:                                  ; preds = %Flow1
+    %__llpc_global_proxy_r5.8.lcssa = phi <4 x i32> [ %43, %Flow1 ]
+    %44 = shufflevector <4 x i32> %__llpc_global_proxy_r5.8.lcssa, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
+    %45 = bitcast <3 x i32> %44 to <3 x float>
+    %46 = fadd reassoc nnan arcp contract <3 x float> %45, zeroinitializer
+    %47 = bitcast <3 x float> %46 to <3 x i32>
+    %48 = shufflevector <3 x i32> %47, <3 x i32> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef>
+    %49 = shufflevector <4 x i32> undef, <4 x i32> %48, <4 x i32> <i32 0, i32 5, i32 undef, i32 3>
+    %50 = shufflevector <4 x i32> %49, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+    br label %Flow2
+  
+  ; <label>:51:                                     ; preds = %Flow2
+    %__llpc_global_proxy_r0.1 = phi <4 x i32> [ %30, %Flow2 ]
+    %__llpc_global_proxy_r6.9 = phi <4 x i32> [ %29, %Flow2 ]
+    br i1 undef, label %55, label %52, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:52:                                     ; preds = %51
+    br i1 undef, label %.lr.ph2463, label %._crit_edge2464, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  .lr.ph2463:                                       ; preds = %52
+    br i1 undef, label %._crit_edge2446, label %53, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:53:                                     ; preds = %.lr.ph2463
+    br label %._crit_edge2446, !structurizecfg.uniform !2
+  
+  ._crit_edge2446:                                  ; preds = %53, %.lr.ph2463
+    br label %._crit_edge2464, !structurizecfg.uniform !2
+  
+  ._crit_edge2464:                                  ; preds = %._crit_edge2446, %52
+    br i1 undef, label %55, label %.lr.ph2434, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  .lr.ph2434:                                       ; preds = %._crit_edge2464
+    br i1 undef, label %._crit_edge, label %54, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  ; <label>:54:                                     ; preds = %.lr.ph2434
+    br label %._crit_edge, !structurizecfg.uniform !2
+  
+  ._crit_edge:                                      ; preds = %54, %.lr.ph2434
+    br label %55, !structurizecfg.uniform !2
+  
+  ; <label>:55:                                     ; preds = %51, %._crit_edge2464, %._crit_edge
+    %__llpc_global_proxy_r0.8.vec.extract369 = extractelement <4 x i32> %__llpc_global_proxy_r0.1, i32 2
+    %56 = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 15, i32 undef, i32 undef, i32 %__llpc_global_proxy_r0.8.vec.extract369, <8 x i32> undef, i32 0, i32 0) #5
+    %57 = shufflevector <4 x float> %56, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+    %58 = fadd reassoc nnan arcp contract <3 x float> %57, zeroinitializer
+    %59 = bitcast <3 x float> %58 to <3 x i32>
+    %60 = extractelement <3 x i32> %59, i32 1
+    store i32 %60, i32 addrspace(3)* undef, align 4
+    ret void
+  }
+  
+  ; Function Attrs: nounwind readonly
+  declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #2
+  
+  ; Function Attrs: nounwind readonly
+  declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
+  
+  ; Function Attrs: nounwind readnone speculatable
+  declare float @llvm.amdgcn.fmed3.f32(float, float, float) #0
+  
+  ; Function Attrs: convergent nounwind
+  declare { i1, i64 } @llvm.amdgcn.if(i1) #3
+  
+  ; Function Attrs: convergent nounwind
+  declare { i1, i64 } @llvm.amdgcn.else(i64) #3
+  
+  ; Function Attrs: convergent nounwind readnone
+  declare i64 @llvm.amdgcn.break(i64) #4
+  
+  ; Function Attrs: convergent nounwind readnone
+  declare i64 @llvm.amdgcn.if.break(i1, i64) #4
+  
+  ; Function Attrs: convergent nounwind readnone
+  declare i64 @llvm.amdgcn.else.break(i64, i64) #4
+  
+  ; Function Attrs: convergent nounwind
+  declare i1 @llvm.amdgcn.loop(i64) #3
+  
+  ; Function Attrs: convergent nounwind
+  declare void @llvm.amdgcn.end.cf(i64) #3
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #5
+  
+  attributes #0 = { nounwind readnone speculatable "target-cpu"="gfx803" }
+  attributes #1 = { nounwind "target-cpu"="gfx803" }
+  attributes #2 = { nounwind readonly "target-cpu"="gfx803" }
+  attributes #3 = { convergent nounwind }
+  attributes #4 = { convergent nounwind readnone }
+  attributes #5 = { nounwind }
+  
+  !amdgpu.pal.metadata = !{!0}
+  
+  !0 = !{i32 268435482, i32 1, i32 268435488, i32 -1, i32 268435480, i32 -449952542, i32 268435481, i32 -841033859, i32 268435538, i32 64, i32 268435539, i32 0, i32 11794, i32 2883584, i32 11795, i32 6022, i32 11783, i32 3, i32 11784, i32 2, i32 11785, i32 12, i32 268435530, i32 0, i32 268435495, i32 0, i32 268435502, i32 0, i32 268435509, i32 256, i32 268435516, i32 104, i32 268435456, i32 -1023767305, i32 268435457, i32 1054862382, i32 11840, i32 268435456, i32 11842, i32 0}
+  !1 = !{i32 5}
+  !2 = !{}
+
+...
+---
+name:            _amdgpu_cs_main
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: sreg_128, preferred-register: '' }
+  - { id: 1, class: sreg_128, preferred-register: '' }
+  - { id: 2, class: sreg_128, preferred-register: '' }
+  - { id: 3, class: sreg_128, preferred-register: '' }
+  - { id: 4, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 5, class: sreg_64, preferred-register: '' }
+  - { id: 6, class: sreg_128, preferred-register: '' }
+  - { id: 7, class: sreg_128, preferred-register: '' }
+  - { id: 8, class: sreg_128, preferred-register: '' }
+  - { id: 9, class: sreg_128, preferred-register: '' }
+  - { id: 10, class: sreg_128, preferred-register: '' }
+  - { id: 11, class: vgpr_32, preferred-register: '' }
+  - { id: 12, class: vgpr_32, preferred-register: '' }
+  - { id: 13, class: vgpr_32, preferred-register: '' }
+  - { id: 14, class: sreg_128, preferred-register: '' }
+  - { id: 15, class: sreg_128, preferred-register: '' }
+  - { id: 16, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 17, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 18, class: vgpr_32, preferred-register: '' }
+  - { id: 19, class: vgpr_32, preferred-register: '' }
+  - { id: 20, class: vgpr_32, preferred-register: '' }
+  - { id: 21, class: vgpr_32, preferred-register: '' }
+  - { id: 22, class: vgpr_32, preferred-register: '' }
+  - { id: 23, class: vgpr_32, preferred-register: '' }
+  - { id: 24, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 25, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 26, class: sreg_32, preferred-register: '' }
+  - { id: 27, class: sreg_128, preferred-register: '' }
+  - { id: 28, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 29, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 30, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 31, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 32, class: sreg_128, preferred-register: '' }
+  - { id: 33, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 34, class: sreg_128, preferred-register: '' }
+  - { id: 35, class: sreg_128, preferred-register: '' }
+  - { id: 36, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 37, class: sreg_128, preferred-register: '' }
+  - { id: 38, class: sreg_128, preferred-register: '' }
+  - { id: 39, class: sreg_128, preferred-register: '' }
+  - { id: 40, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 41, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 42, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 43, class: sreg_128, preferred-register: '' }
+  - { id: 44, class: vreg_128, preferred-register: '' }
+  - { id: 45, class: vgpr_32, preferred-register: '' }
+  - { id: 46, class: sreg_128, preferred-register: '' }
+  - { id: 47, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 48, class: vgpr_32, preferred-register: '' }
+  - { id: 49, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 50, class: sreg_128, preferred-register: '' }
+  - { id: 51, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 52, class: sreg_128, preferred-register: '' }
+  - { id: 53, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 54, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 55, class: vgpr_32, preferred-register: '' }
+  - { id: 56, class: vgpr_32, preferred-register: '' }
+  - { id: 57, class: vgpr_32, preferred-register: '' }
+  - { id: 58, class: vgpr_32, preferred-register: '' }
+  - { id: 59, class: vgpr_32, preferred-register: '' }
+  - { id: 60, class: vgpr_32, preferred-register: '' }
+  - { id: 61, class: vgpr_32, preferred-register: '' }
+  - { id: 62, class: vgpr_32, preferred-register: '' }
+  - { id: 63, class: vgpr_32, preferred-register: '' }
+  - { id: 64, class: vgpr_32, preferred-register: '' }
+  - { id: 65, class: sreg_128, preferred-register: '' }
+  - { id: 66, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 67, class: vreg_128, preferred-register: '' }
+  - { id: 68, class: vreg_128, preferred-register: '' }
+  - { id: 69, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 70, class: vreg_128, preferred-register: '' }
+  - { id: 71, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 72, class: vreg_128, preferred-register: '' }
+  - { id: 73, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 74, class: sreg_256, preferred-register: '' }
+  - { id: 75, class: vgpr_32, preferred-register: '' }
+  - { id: 76, class: vgpr_32, preferred-register: '' }
+  - { id: 77, class: vgpr_32, preferred-register: '' }
+  - { id: 78, class: vgpr_32, preferred-register: '' }
+  - { id: 79, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 80, class: vgpr_32, preferred-register: '' }
+  - { id: 81, class: vreg_128, preferred-register: '' }
+  - { id: 82, class: vgpr_32, preferred-register: '' }
+  - { id: 83, class: vgpr_32, preferred-register: '' }
+  - { id: 84, class: vreg_128, preferred-register: '' }
+  - { id: 85, class: vgpr_32, preferred-register: '' }
+  - { id: 86, class: vgpr_32, preferred-register: '' }
+  - { id: 87, class: vreg_128, preferred-register: '' }
+  - { id: 88, class: vreg_128, preferred-register: '' }
+  - { id: 89, class: vreg_128, preferred-register: '' }
+  - { id: 90, class: vreg_128, preferred-register: '' }
+  - { id: 91, class: vgpr_32, preferred-register: '' }
+  - { id: 92, class: vgpr_32, preferred-register: '' }
+  - { id: 93, class: vreg_128, preferred-register: '' }
+  - { id: 94, class: vreg_128, preferred-register: '' }
+  - { id: 95, class: vgpr_32, preferred-register: '' }
+  - { id: 96, class: vreg_128, preferred-register: '' }
+  - { id: 97, class: vreg_128, preferred-register: '' }
+  - { id: 98, class: vreg_128, preferred-register: '' }
+  - { id: 99, class: vgpr_32, preferred-register: '' }
+  - { id: 100, class: vreg_128, preferred-register: '' }
+  - { id: 101, class: vreg_128, preferred-register: '' }
+  - { id: 102, class: vreg_128, preferred-register: '' }
+  - { id: 103, class: vreg_128, preferred-register: '' }
+  - { id: 104, class: vreg_128, preferred-register: '' }
+  - { id: 105, class: vreg_128, preferred-register: '' }
+  - { id: 106, class: vreg_128, preferred-register: '' }
+  - { id: 107, class: sreg_64, preferred-register: '' }
+liveins:         
+  - { reg: '$vgpr0', virtual-reg: '%11' }
+  - { reg: '$vgpr1', virtual-reg: '%12' }
+  - { reg: '$vgpr2', virtual-reg: '%13' }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+constants:       
+body:             |
+  bb.0..entry:
+    successors: %bb.5(0x40000000), %bb.1(0x40000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2
+  
+    S_CBRANCH_SCC1 %bb.5, implicit undef $scc
+    S_BRANCH %bb.1
+  
+  bb.1 (%ir-block.1):
+    successors: %bb.3(0x40000000), %bb.2(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.3, implicit undef $scc
+    S_BRANCH %bb.2
+  
+  bb.2 (%ir-block.2):
+    successors: %bb.3(0x80000000)
+  
+  
+  bb.3 (%ir-block.3):
+    successors: %bb.4(0x40000000), %bb.5(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.5, implicit undef $scc
+    S_BRANCH %bb.4
+  
+  bb.4..lr.ph2597:
+    successors: %bb.5(0x80000000)
+  
+  
+  bb.5 (%ir-block.4):
+    successors: %bb.6(0x40000000), %bb.7(0x40000000)
+  
+    %19:vgpr_32 = V_MUL_F32_e32 0, undef %20:vgpr_32, implicit $exec
+    %21:vgpr_32 = V_CVT_U32_F32_e32 killed %19, implicit $exec
+    %22:vgpr_32 = V_CVT_F32_I32_e32 killed %21, implicit $exec
+    %23:vgpr_32 = V_CVT_U32_F32_e32 killed %22, implicit $exec
+    %83:vgpr_32 = V_LSHRREV_B32_e32 4, killed %23, implicit $exec
+    S_CBRANCH_SCC0 %bb.7, implicit undef $scc
+  
+  bb.6:
+    successors: %bb.15(0x80000000)
+  
+    undef %84.sub1:vreg_128 = COPY killed %83
+    %105:vreg_128 = COPY killed %84
+    S_BRANCH %bb.15
+  
+  bb.7 (%ir-block.17):
+    successors: %bb.8(0x40000000), %bb.9(0x40000000)
+  
+    S_CBRANCH_SCC0 %bb.9, implicit undef $scc
+  
+  bb.8:
+    successors: %bb.15(0x80000000)
+  
+    %33:sreg_32_xm0 = S_MOV_B32 0
+    undef %34.sub0:sreg_128 = COPY %33
+    %34.sub1:sreg_128 = COPY %33
+    %34.sub2:sreg_128 = COPY %33
+    %34.sub3:sreg_128 = COPY killed %33
+    %88:vreg_128 = COPY killed %34
+    %105:vreg_128 = COPY killed %88
+    S_BRANCH %bb.15
+  
+  bb.9..lr.ph2577:
+    successors: %bb.10(0x40000000), %bb.14(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.14, implicit undef $scc
+    S_BRANCH %bb.10
+  
+  bb.10 (%ir-block.18):
+    successors: %bb.11(0x40000000), %bb.13(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.13, implicit undef $scc
+    S_BRANCH %bb.11
+  
+  bb.11 (%ir-block.19):
+    successors: %bb.13(0x40000000), %bb.12(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.13, implicit undef $scc
+    S_BRANCH %bb.12
+  
+  bb.12 (%ir-block.20):
+    successors: %bb.13(0x80000000)
+  
+  
+  bb.13 (%ir-block.21):
+    successors: %bb.14(0x80000000)
+  
+  
+  bb.14.._crit_edge2563:
+    successors: %bb.15(0x80000000)
+  
+    %36:sreg_32_xm0 = S_MOV_B32 0
+    undef %37.sub0:sreg_128 = COPY %36
+    %37.sub1:sreg_128 = COPY %36
+    %37.sub2:sreg_128 = COPY %36
+    %37.sub3:sreg_128 = COPY killed %36
+    %35:sreg_128 = COPY killed %37
+    %89:vreg_128 = COPY killed %35
+    %105:vreg_128 = COPY killed %89
+  
+  bb.15 (%ir-block.22):
+    successors: %bb.17(0x40000000), %bb.35(0x40000000)
+  
+    %87:vreg_128 = COPY killed %105
+    S_CBRANCH_SCC0 %bb.17, implicit undef $scc
+  
+  bb.35:
+    successors: %bb.16(0x80000000)
+  
+    %106:vreg_128 = COPY killed %87
+  
+  bb.16.Flow2:
+    successors: %bb.25(0x80000000)
+  
+    %93:vreg_128 = COPY killed %106
+    S_BRANCH %bb.25
+  
+  bb.17.._crit_edge2538:
+    successors: %bb.18(0x40000000), %bb.22(0x40000000)
+  
+    %92:vgpr_32 = V_MUL_LO_I32 %87.sub1, target-flags(amdgpu-gotprel32-lo) 7, implicit $exec
+    S_CBRANCH_SCC1 %bb.22, implicit undef $scc
+    S_BRANCH %bb.18
+  
+  bb.18 (%ir-block.32):
+    successors: %bb.19(0x40000000), %bb.21(0x40000000)
+  
+    %44:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %92, undef %46:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
+    %49:sreg_64 = V_CMP_NE_U32_e64 target-flags(amdgpu-gotprel) 0, killed %44.sub0, implicit $exec
+    %5:sreg_64 = COPY $exec, implicit-def $exec
+    %107:sreg_64 = S_AND_B64 %5, %49, implicit-def dead $scc
+    $exec = S_MOV_B64_term killed %107
+    SI_MASK_BRANCH %bb.21, implicit $exec
+    S_BRANCH %bb.19
+  
+  bb.19 (%ir-block.39):
+    successors: %bb.20(0x40000000), %bb.21(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.21, implicit undef $scc
+  
+  bb.20 (%ir-block.40):
+    successors: %bb.21(0x80000000)
+  
+  
+  bb.21.Flow:
+    successors: %bb.23(0x80000000)
+  
+    $exec = S_OR_B64 $exec, killed %5, implicit-def $scc
+    S_BRANCH %bb.23
+  
+  bb.22.Flow1:
+    successors: %bb.24(0x80000000)
+  
+    %90:vreg_128 = COPY killed %87
+    %90.sub0:vreg_128 = COPY undef %92
+    S_BRANCH %bb.24
+  
+  bb.23.._crit_edge2480:
+    successors: %bb.22(0x80000000)
+  
+    S_BRANCH %bb.22
+  
+  bb.24.._crit_edge2499:
+    successors: %bb.16(0x80000000)
+  
+    %106:vreg_128 = COPY killed %90
+    S_BRANCH %bb.16
+  
+  bb.25 (%ir-block.51):
+    successors: %bb.34(0x40000000), %bb.26(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.34, implicit undef $scc
+    S_BRANCH %bb.26
+  
+  bb.26 (%ir-block.52):
+    successors: %bb.27(0x40000000), %bb.30(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.30, implicit undef $scc
+    S_BRANCH %bb.27
+  
+  bb.27..lr.ph2463:
+    successors: %bb.29(0x40000000), %bb.28(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.29, implicit undef $scc
+    S_BRANCH %bb.28
+  
+  bb.28 (%ir-block.53):
+    successors: %bb.29(0x80000000)
+  
+  
+  bb.29.._crit_edge2446:
+    successors: %bb.30(0x80000000)
+  
+  
+  bb.30.._crit_edge2464:
+    successors: %bb.34(0x40000000), %bb.31(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.34, implicit undef $scc
+    S_BRANCH %bb.31
+  
+  bb.31..lr.ph2434:
+    successors: %bb.33(0x40000000), %bb.32(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.33, implicit undef $scc
+    S_BRANCH %bb.32
+  
+  bb.32 (%ir-block.54):
+    successors: %bb.33(0x80000000)
+  
+  
+  bb.33.._crit_edge:
+    successors: %bb.34(0x80000000)
+  
+  
+  bb.34 (%ir-block.55):
+    undef %72.sub2:vreg_128 = COPY killed %93.sub2
+    %73:sreg_32_xm0 = S_MOV_B32 0
+    undef %74.sub0:sreg_256 = COPY %73
+    %74.sub1:sreg_256 = COPY %73
+    %74.sub2:sreg_256 = COPY %73
+    %74.sub3:sreg_256 = COPY %73
+    %74.sub4:sreg_256 = COPY %73
+    %74.sub5:sreg_256 = COPY %73
+    %74.sub6:sreg_256 = COPY %73
+    %74.sub7:sreg_256 = COPY killed %73
+    %75:vgpr_32 = IMAGE_LOAD_V1_V4 killed %72, killed %74, 2, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
+    %78:vgpr_32 = V_ADD_F32_e32 0, killed %75, implicit $exec
+    $m0 = S_MOV_B32 -1
+    DS_WRITE_B32 undef %80:vgpr_32, killed %78, 0, 0, implicit $m0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`, addrspace 3)
+    S_ENDPGM
+
+...

test/CodeGen/AMDGPU/coalescing-subranges-another-prune-error.mir

+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+
+# With one version of the D48102 fix, this test failed with
+# Assertion failed: (Id != S.end() && T != S.end() && T->valno == Id->valno), function pruneSubRegValues, file ../lib/CodeGen/RegisterCoalescer.cpp, line 2875.
+
+# GCN: {{^body}}
+
+--- |
+  ; ModuleID = 'cutdown.bc'
+  source_filename = "llpcPipeline"
+  target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+  target triple = "amdgcn--amdpal"
+  
+  ; Function Attrs: nounwind
+  define dllexport amdgpu_ps void @_amdgpu_ps_main(float %arg) local_unnamed_addr #0 !spirv.ExecutionModel !1 {
+  bb8:
+    br i1 undef, label %bb9, label %Flow5, !amdgpu.uniform !2
+  
+  bb9:                                              ; preds = %bb8
+    %tmp = insertelement <2 x float> undef, float %arg, i32 1
+    %tmp10 = fmul reassoc nnan arcp contract <2 x float> %tmp, <float 6.250000e-02, float 6.250000e-02>
+    %x0.i955 = extractelement <2 x float> %tmp10, i32 0
+    %tmp11 = tail call float @llvm.floor.f32(float %x0.i955) #7
+    %tmp12 = fadd reassoc nnan arcp contract float %tmp11, 0.000000e+00
+    %tmp13 = fptoui float %tmp12 to i32
+    %tmp14 = shl i32 %tmp13, 1
+    %tmp15 = tail call float @llvm.sqrt.f32(float undef) #7
+    %tmp16 = bitcast float %tmp15 to i32
+    %tmp17 = insertelement <4 x i32> undef, i32 %tmp16, i32 0
+    %tmp18 = shufflevector <4 x i32> %tmp17, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
+    br label %bb19
+  
+  Flow5:                                            ; preds = %Flow4, %bb8
+    %0 = phi <4 x i32> [ %36, %Flow4 ], [ zeroinitializer, %bb8 ]
+    br label %bb47
+  
+  bb19:                                             ; preds = %bb9, %Flow
+    %phi.broken6 = phi i64 [ 0, %bb9 ], [ %22, %Flow ]
+    %1 = phi <4 x i32> [ %15, %Flow ], [ undef, %bb9 ]
+    %__llpc_global_proxy_r8.12.vec.insert23224382 = phi <4 x i32> [ %19, %Flow ], [ undef, %bb9 ]
+    %__llpc_global_proxy_r7.12.vec.extract4381 = phi i32 [ %18, %Flow ], [ 0, %bb9 ]
+    %__llpc_global_proxy_r9.34359 = phi <4 x i32> [ %17, %Flow ], [ zeroinitializer, %bb9 ]
+    %tmp20 = or i32 %__llpc_global_proxy_r7.12.vec.extract4381, %tmp14
+    %tmp21 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %tmp20, i32 0, i1 false, i1 false) #7
+    %tmp22 = bitcast <4 x float> %tmp21 to <4 x i32>
+    %tmp23 = lshr <4 x i32> %tmp22, <i32 30, i32 30, i32 30, i32 30>
+    %tmp24 = extractelement <4 x i32> %tmp23, i32 0
+    %__llpc_global_proxy_r9.0.vec.insert2411 = insertelement <4 x i32> %__llpc_global_proxy_r9.34359, i32 0, i32 0
+    %tmp25 = icmp eq i32 %tmp24, 0
+    %tmp26 = sext i1 %tmp25 to i32
+    %__llpc_global_proxy_r9.4.vec.insert24484304 = insertelement <4 x i32> %__llpc_global_proxy_r9.0.vec.insert2411, i32 %tmp26, i32 1
+    %2 = xor i1 %tmp25, true
+    %3 = call { i1, i64 } @llvm.amdgcn.if(i1 %2)
+    %4 = extractvalue { i1, i64 } %3, 0
+    %5 = extractvalue { i1, i64 } %3, 1
+    br i1 %4, label %.lr.ph4331, label %Flow
+  
+  Flow1:                                            ; preds = %bb44, %._crit_edge4332
+    %loop.phi7 = phi i64 [ %35, %bb44 ], [ %phi.broken6, %._crit_edge4332 ]
+    %6 = phi <4 x i32> [ %__llpc_global_proxy_r9.4.vec.insert2448, %bb44 ], [ %1, %._crit_edge4332 ]
+    %7 = phi <4 x i32> [ %__llpc_global_proxy_r9.4.vec.insert2448, %bb44 ], [ undef, %._crit_edge4332 ]
+    %8 = phi i32 [ 1, %bb44 ], [ undef, %._crit_edge4332 ]
+    %9 = phi <4 x i32> [ %__llpc_global_proxy_r8.12.vec.insert2322, %bb44 ], [ undef, %._crit_edge4332 ]
+    %10 = phi i1 [ false, %bb44 ], [ true, %._crit_edge4332 ]
+    %11 = call i64 @llvm.amdgcn.else.break(i64 %29, i64 %loop.phi7)
+    call void @llvm.amdgcn.end.cf(i64 %29)
+    br label %Flow
+  
+  Flow2:                                            ; preds = %Flow
+    call void @llvm.amdgcn.end.cf(i64 %22)
+    %12 = call { i1, i64 } @llvm.amdgcn.if(i1 %21)
+    %13 = extractvalue { i1, i64 } %12, 0
+    %14 = extractvalue { i1, i64 } %12, 1
+    br i1 %13, label %._crit_edge4332.thread, label %Flow3
+  
+  ._crit_edge4332.thread:                           ; preds = %Flow2
+    %__llpc_global_proxy_r8.12.vec.insert23644434 = insertelement <4 x i32> %__llpc_global_proxy_r8.12.vec.insert23224382, i32 -1, i32 3
+    br label %Flow3
+  
+  .lr.ph4331:                                       ; preds = %bb19
+    br label %bb27
+  
+  Flow:                                             ; preds = %Flow1, %bb19
+    %loop.phi = phi i64 [ %11, %Flow1 ], [ %phi.broken6, %bb19 ]
+    %15 = phi <4 x i32> [ %6, %Flow1 ], [ %1, %bb19 ]
+    %16 = phi <4 x i32> [ %__llpc_global_proxy_r9.4.vec.insert2448, %Flow1 ], [ undef, %bb19 ]
+    %17 = phi <4 x i32> [ %7, %Flow1 ], [ undef, %bb19 ]
+    %18 = phi i32 [ %8, %Flow1 ], [ undef, %bb19 ]
+    %19 = phi <4 x i32> [ %9, %Flow1 ], [ undef, %bb19 ]
+    %20 = phi i1 [ %10, %Flow1 ], [ false, %bb19 ]
+    %21 = phi i1 [ false, %Flow1 ], [ true, %bb19 ]
+    %22 = call i64 @llvm.amdgcn.else.break(i64 %5, i64 %loop.phi)
+    call void @llvm.amdgcn.end.cf(i64 %5)
+    %23 = call i1 @llvm.amdgcn.loop(i64 %22)
+    br i1 %23, label %Flow2, label %bb19
+  
+  bb27:                                             ; preds = %.lr.ph4331, %._crit_edge4286
+    %phi.broken = phi i64 [ 0, %.lr.ph4331 ], [ %24, %._crit_edge4286 ]
+    %__llpc_global_proxy_r9.4.vec.insert24484329 = phi <4 x i32> [ %__llpc_global_proxy_r9.4.vec.insert2448, %._crit_edge4286 ], [ %__llpc_global_proxy_r9.4.vec.insert24484304, %.lr.ph4331 ]
+    %__llpc_global_proxy_r9.44305 = phi <4 x i32> [ %__llpc_global_proxy_r9.0.vec.insert, %._crit_edge4286 ], [ %__llpc_global_proxy_r9.0.vec.insert2411, %.lr.ph4331 ]
+    br i1 undef, label %._crit_edge, label %bb30, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  bb30:                                             ; preds = %bb27
+    br label %._crit_edge, !structurizecfg.uniform !2
+  
+  ._crit_edge:                                      ; preds = %bb30, %bb27
+    br i1 undef, label %._crit_edge4245, label %bb38, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  bb38:                                             ; preds = %._crit_edge
+    br label %._crit_edge4245, !structurizecfg.uniform !2
+  
+  ._crit_edge4245:                                  ; preds = %bb38, %._crit_edge
+    br i1 undef, label %.lr.ph4285, label %._crit_edge4286, !amdgpu.uniform !2, !structurizecfg.uniform !2
+  
+  .lr.ph4285:                                       ; preds = %._crit_edge4245
+    br label %._crit_edge4286, !structurizecfg.uniform !2
+  
+  ._crit_edge4286:                                  ; preds = %.lr.ph4285, %._crit_edge4245
+    %__llpc_global_proxy_r11.12.vec.insert2682 = shufflevector <4 x i32> undef, <4 x i32> %__llpc_global_proxy_r9.44305, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
+    %__llpc_global_proxy_r9.4.vec.insert2492 = shufflevector <4 x i32> %__llpc_global_proxy_r9.4.vec.insert24484329, <4 x i32> %__llpc_global_proxy_r11.12.vec.insert2682, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
+    %__llpc_global_proxy_r15.12.vec.extract30424267 = extractelement <4 x i32> %__llpc_global_proxy_r9.4.vec.insert2492, i32 1
+    %__llpc_global_proxy_r9.0.vec.insert = insertelement <4 x i32> %__llpc_global_proxy_r9.4.vec.insert2492, i32 %__llpc_global_proxy_r15.12.vec.extract30424267, i32 0
+    %tmp41 = icmp uge i32 %__llpc_global_proxy_r15.12.vec.extract30424267, %tmp24
+    %__llpc_global_proxy_r9.4.vec.insert2448 = insertelement <4 x i32> %__llpc_global_proxy_r9.0.vec.insert, i32 undef, i32 1
+    %24 = call i64 @llvm.amdgcn.if.break(i1 %tmp41, i64 %phi.broken)
+    %25 = call i1 @llvm.amdgcn.loop(i64 %24)
+    br i1 %25, label %._crit_edge4332, label %bb27
+  
+  ._crit_edge4332:                                  ; preds = %._crit_edge4286
+    call void @llvm.amdgcn.end.cf(i64 %24)
+    %tmp42 = icmp ult i32 %tmp24, 12
+    %26 = xor i1 %tmp42, true
+    %27 = call { i1, i64 } @llvm.amdgcn.if(i1 %26)
+    %28 = extractvalue { i1, i64 } %27, 0
+    %29 = extractvalue { i1, i64 } %27, 1
+    br i1 %28, label %bb44, label %Flow1
+  
+  Flow3:                                            ; preds = %._crit_edge4332.thread, %Flow2
+    %30 = phi <4 x i32> [ %__llpc_global_proxy_r9.4.vec.insert24484304, %._crit_edge4332.thread ], [ %16, %Flow2 ]
+    %31 = phi i1 [ true, %._crit_edge4332.thread ], [ %20, %Flow2 ]
+    call void @llvm.amdgcn.end.cf(i64 %14)
+    %32 = call { i1, i64 } @llvm.amdgcn.if(i1 %31)
+    %33 = extractvalue { i1, i64 } %32, 0
+    %34 = extractvalue { i1, i64 } %32, 1
+    br i1 %33, label %.loopexit4453, label %Flow4
+  
+  .loopexit4453:                                    ; preds = %Flow3
+    %__llpc_global_proxy_r9.4.vec.insert2448.lcssa4450 = phi <4 x i32> [ %30, %Flow3 ]
+    %tmp43 = shufflevector <4 x i32> %tmp18, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
+    br label %Flow4
+  
+  bb44:                                             ; preds = %._crit_edge4332
+    %__llpc_global_proxy_r8.12.vec.insert2364 = insertelement <4 x i32> %__llpc_global_proxy_r8.12.vec.insert23224382, i32 undef, i32 3
+    %tmp45 = icmp ne i32 %__llpc_global_proxy_r7.12.vec.extract4381, 0
+    %__llpc_global_proxy_r8.12.vec.insert2322 = insertelement <4 x i32> %__llpc_global_proxy_r8.12.vec.insert2364, i32 undef, i32 3
+    %35 = call i64 @llvm.amdgcn.if.break(i1 %tmp45, i64 %phi.broken6)
+    br label %Flow1
+  
+  Flow4:                                            ; preds = %.loopexit4453, %Flow3
+    %36 = phi <4 x i32> [ %__llpc_global_proxy_r9.4.vec.insert2448.lcssa4450, %.loopexit4453 ], [ %15, %Flow3 ]
+    call void @llvm.amdgcn.end.cf(i64 %34)
+    br label %Flow5
+  
+  bb47:                                             ; preds = %Flow5
+    %__llpc_global_proxy_r9.7 = phi <4 x i32> [ %0, %Flow5 ]
+    %tmp50 = shufflevector <4 x i32> %__llpc_global_proxy_r9.7, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+    %tmp51 = bitcast <2 x i32> %tmp50 to <2 x float>
+    %tmp52 = fadd reassoc nnan arcp contract <2 x float> zeroinitializer, %tmp51
+    %tmp53 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %tmp52, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #7
+    %tmp54 = fmul reassoc nnan arcp contract <4 x float> %tmp53, zeroinitializer
+    %tmp55 = extractelement <4 x float> %tmp54, i32 3
+    %tmp56 = fmul reassoc nnan arcp contract float 0.000000e+00, %tmp55
+    %tmp57 = bitcast float %tmp56 to i32
+    %tmp58 = insertelement <3 x i32> undef, i32 %tmp57, i32 0
+    %tmp59 = shufflevector <3 x i32> %tmp58, <3 x i32> undef, <3 x i32> zeroinitializer
+    %tmp60 = bitcast <3 x i32> %tmp59 to <3 x float>
+    %tmp61 = fmul reassoc nnan arcp contract <3 x float> zeroinitializer, %tmp60
+    %tmp62 = fadd reassoc nnan arcp contract <3 x float> zeroinitializer, %tmp61
+    %x2.i = extractelement <3 x float> %tmp62, i32 2
+    %tmp63 = tail call float @llvm.maxnum.f32(float %x2.i, float 0.000000e+00) #7
+    %tmp64 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp63, float 1.000000e+00) #8
+    call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> undef, <2 x half> %tmp64, i1 false, i1 true) #7
+    ret void
+  }
+  
+  ; Function Attrs: nounwind readnone speculatable
+  declare float @llvm.sqrt.f32(float) #1
+  
+  ; Function Attrs: nounwind readnone
+  declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i1) #2
+  
+  ; Function Attrs: nounwind readonly
+  declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #3
+  
+  ; Function Attrs: nounwind readnone speculatable
+  declare float @llvm.maxnum.f32(float, float) #1
+  
+  ; Function Attrs: nounwind readnone speculatable
+  declare float @llvm.floor.f32(float) #1
+  
+  ; Function Attrs: nounwind readonly
+  declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #3
+  
+  ; Function Attrs: nounwind readnone speculatable
+  declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #4
+  
+  ; Function Attrs: convergent nounwind
+  declare { i1, i64 } @llvm.amdgcn.if(i1) #5
+  
+  ; Function Attrs: convergent nounwind
+  declare { i1, i64 } @llvm.amdgcn.else(i64) #5
+  
+  ; Function Attrs: convergent nounwind readnone
+  declare i64 @llvm.amdgcn.break(i64) #6
+  
+  ; Function Attrs: convergent nounwind readnone
+  declare i64 @llvm.amdgcn.if.break(i1, i64) #6
+  
+  ; Function Attrs: convergent nounwind readnone
+  declare i64 @llvm.amdgcn.else.break(i64, i64) #6
+  
+  ; Function Attrs: convergent nounwind
+  declare i1 @llvm.amdgcn.loop(i64) #5
+  
+  ; Function Attrs: convergent nounwind
+  declare void @llvm.amdgcn.end.cf(i64) #5
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #7
+  
+  attributes #0 = { nounwind "InitialPSInputAddr"="3842" "target-cpu"="gfx803" }
+  attributes #1 = { nounwind readnone speculatable "target-cpu"="gfx803" }
+  attributes #2 = { nounwind readnone "target-cpu"="gfx803" }
+  attributes #3 = { nounwind readonly "target-cpu"="gfx803" }
+  attributes #4 = { nounwind "target-cpu"="gfx803" }
+  attributes #5 = { convergent nounwind }
+  attributes #6 = { convergent nounwind readnone }
+  attributes #7 = { nounwind }
+  attributes #8 = { nounwind readnone speculatable }
+  
+  !amdgpu.pal.metadata = !{!0}
+  
+  !0 = !{i32 268435482, i32 5, i32 268435488, i32 -1, i32 268435480, i32 -540785387, i32 268435481, i32 -1758319860, i32 268435538, i32 4096, i32 268435539, i32 8192, i32 11338, i32 53215232, i32 11339, i32 16, i32 41411, i32 4, i32 41393, i32 2, i32 41479, i32 0, i32 41476, i32 17301504, i32 41478, i32 1087, i32 41721, i32 45, i32 41633, i32 0, i32 41702, i32 0, i32 41653, i32 0, i32 41657, i32 0, i32 41661, i32 0, i32 41665, i32 0, i32 41645, i32 0, i32 41750, i32 14, i32 268435528, i32 0, i32 268435493, i32 0, i32 268435500, i32 0, i32 268435507, i32 256, i32 268435514, i32 104, i32 268435536, i32 0, i32 11274, i32 2883584, i32 11275, i32 6, i32 41412, i32 0, i32 41413, i32 20, i32 41400, i32 16777216, i32 41398, i32 2, i32 41395, i32 0, i32 41396, i32 0, i32 41397, i32 0, i32 41619, i32 100794764, i32 41475, i32 16, i32 41103, i32 255, i32 268435485, i32 0, i32 268435529, i32 0, i32 268435494, i32 0, i32 268435501, i32 0, i32 268435508, i32 256, i32 268435515, i32 104, i32 41685, i32 0, i32 268435460, i32 -434521603, i32 268435461, i32 1719750426, i32 268435476, i32 738696316, i32 268435477, i32 218380994, i32 268435532, i32 5, i32 41642, i32 127, i32 11346, i32 268435459, i32 11347, i32 268435460, i32 11340, i32 268435456, i32 11342, i32 0, i32 11343, i32 1, i32 11344, i32 2, i32 11345, i32 4, i32 41361, i32 0, i32 41362, i32 1, i32 11276, i32 268435456, i32 11278, i32 3}
+  !1 = !{i32 4}
+  !2 = !{}
+
+...
+---
+name:            _amdgpu_ps_main
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 1, class: sreg_128, preferred-register: '' }
+  - { id: 2, class: sreg_128, preferred-register: '' }
+  - { id: 3, class: sreg_64, preferred-register: '' }
+  - { id: 4, class: sreg_128, preferred-register: '' }
+  - { id: 5, class: sreg_128, preferred-register: '' }
+  - { id: 6, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 7, class: sreg_128, preferred-register: '' }
+  - { id: 8, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 9, class: sreg_128, preferred-register: '' }
+  - { id: 10, class: sreg_128, preferred-register: '' }
+  - { id: 11, class: sreg_64, preferred-register: '' }
+  - { id: 12, class: sreg_64, preferred-register: '' }
+  - { id: 13, class: sreg_128, preferred-register: '' }
+  - { id: 14, class: sreg_128, preferred-register: '' }
+  - { id: 15, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 16, class: sreg_128, preferred-register: '' }
+  - { id: 17, class: vreg_1, preferred-register: '' }
+  - { id: 18, class: sreg_64, preferred-register: '' }
+  - { id: 19, class: sreg_64, preferred-register: '' }
+  - { id: 20, class: sreg_64, preferred-register: '' }
+  - { id: 21, class: sreg_128, preferred-register: '' }
+  - { id: 22, class: sreg_128, preferred-register: '' }
+  - { id: 23, class: sreg_128, preferred-register: '' }
+  - { id: 24, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 25, class: sreg_128, preferred-register: '' }
+  - { id: 26, class: vreg_1, preferred-register: '' }
+  - { id: 27, class: vreg_1, preferred-register: '' }
+  - { id: 28, class: sreg_64, preferred-register: '' }
+  - { id: 29, class: sreg_64, preferred-register: '' }
+  - { id: 30, class: sreg_128, preferred-register: '' }
+  - { id: 31, class: sreg_128, preferred-register: '' }
+  - { id: 32, class: sreg_128, preferred-register: '' }
+  - { id: 33, class: sreg_128, preferred-register: '' }
+  - { id: 34, class: sreg_64, preferred-register: '' }
+  - { id: 35, class: sreg_64, preferred-register: '' }
+  - { id: 36, class: sreg_128, preferred-register: '' }
+  - { id: 37, class: vreg_1, preferred-register: '' }
+  - { id: 38, class: sreg_64, preferred-register: '' }
+  - { id: 39, class: sreg_128, preferred-register: '' }
+  - { id: 40, class: sreg_128, preferred-register: '' }
+  - { id: 41, class: sreg_64, preferred-register: '' }
+  - { id: 42, class: sreg_128, preferred-register: '' }
+  - { id: 43, class: sreg_128, preferred-register: '' }
+  - { id: 44, class: vgpr_32, preferred-register: '' }
+  - { id: 45, class: sreg_128, preferred-register: '' }
+  - { id: 46, class: sgpr_32, preferred-register: '' }
+  - { id: 47, class: sreg_128, preferred-register: '' }
+  - { id: 48, class: sreg_64, preferred-register: '' }
+  - { id: 49, class: sreg_128, preferred-register: '' }
+  - { id: 50, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 51, class: sreg_128, preferred-register: '' }
+  - { id: 52, class: vgpr_32, preferred-register: '' }
+  - { id: 53, class: vgpr_32, preferred-register: '' }
+  - { id: 54, class: vgpr_32, preferred-register: '' }
+  - { id: 55, class: vgpr_32, preferred-register: '' }
+  - { id: 56, class: vgpr_32, preferred-register: '' }
+  - { id: 57, class: vgpr_32, preferred-register: '' }
+  - { id: 58, class: vgpr_32, preferred-register: '' }
+  - { id: 59, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 60, class: sreg_32, preferred-register: '' }
+  - { id: 61, class: vgpr_32, preferred-register: '' }
+  - { id: 62, class: vgpr_32, preferred-register: '' }
+  - { id: 63, class: sreg_128, preferred-register: '' }
+  - { id: 64, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 65, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 66, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 67, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 68, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 69, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 70, class: sreg_128, preferred-register: '' }
+  - { id: 71, class: sreg_128, preferred-register: '' }
+  - { id: 72, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 73, class: vgpr_32, preferred-register: '' }
+  - { id: 74, class: vgpr_32, preferred-register: '' }
+  - { id: 75, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 76, class: vreg_128, preferred-register: '' }
+  - { id: 77, class: vgpr_32, preferred-register: '' }
+  - { id: 78, class: sreg_128, preferred-register: '' }
+  - { id: 79, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 80, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 81, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 82, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 83, class: sgpr_32, preferred-register: '' }
+  - { id: 84, class: sreg_64_xexec, preferred-register: '$vcc' }
+  - { id: 85, class: sgpr_32, preferred-register: '' }
+  - { id: 86, class: vgpr_32, preferred-register: '' }
+  - { id: 87, class: sreg_64, preferred-register: '' }
+  - { id: 88, class: sreg_64, preferred-register: '' }
+  - { id: 89, class: sreg_128, preferred-register: '' }
+  - { id: 90, class: sreg_64, preferred-register: '' }
+  - { id: 91, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 92, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 93, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 94, class: sreg_128, preferred-register: '' }
+  - { id: 95, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 96, class: vgpr_32, preferred-register: '' }
+  - { id: 97, class: sreg_128, preferred-register: '' }
+  - { id: 98, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 99, class: vgpr_32, preferred-register: '' }
+  - { id: 100, class: vgpr_32, preferred-register: '' }
+  - { id: 101, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 102, class: sreg_64, preferred-register: '' }
+  - { id: 103, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 104, class: vgpr_32, preferred-register: '' }
+  - { id: 105, class: vgpr_32, preferred-register: '' }
+  - { id: 106, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 107, class: sreg_64, preferred-register: '' }
+  - { id: 108, class: vgpr_32, preferred-register: '' }
+  - { id: 109, class: sreg_64, preferred-register: '' }
+  - { id: 110, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 111, class: vgpr_32, preferred-register: '' }
+  - { id: 112, class: sreg_64, preferred-register: '' }
+  - { id: 113, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 114, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 115, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 116, class: vgpr_32, preferred-register: '' }
+  - { id: 117, class: vgpr_32, preferred-register: '' }
+  - { id: 118, class: vgpr_32, preferred-register: '' }
+  - { id: 119, class: sreg_64, preferred-register: '' }
+  - { id: 120, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 121, class: sreg_256, preferred-register: '' }
+  - { id: 122, class: vgpr_32, preferred-register: '' }
+  - { id: 123, class: vreg_64, preferred-register: '' }
+  - { id: 124, class: sreg_128, preferred-register: '' }
+  - { id: 125, class: vgpr_32, preferred-register: '' }
+  - { id: 126, class: vgpr_32, preferred-register: '' }
+  - { id: 127, class: vgpr_32, preferred-register: '' }
+  - { id: 128, class: vgpr_32, preferred-register: '' }
+  - { id: 129, class: vgpr_32, preferred-register: '' }
+  - { id: 130, class: vgpr_32, preferred-register: '' }
+  - { id: 131, class: vgpr_32, preferred-register: '' }
+  - { id: 132, class: vgpr_32, preferred-register: '' }
+  - { id: 133, class: vgpr_32, preferred-register: '' }
+  - { id: 134, class: vgpr_32, preferred-register: '' }
+  - { id: 135, class: vgpr_32, preferred-register: '' }
+  - { id: 136, class: vgpr_32, preferred-register: '' }
+  - { id: 137, class: vreg_128, preferred-register: '' }
+  - { id: 138, class: vgpr_32, preferred-register: '' }
+  - { id: 139, class: vgpr_32, preferred-register: '' }
+  - { id: 140, class: vgpr_32, preferred-register: '' }
+  - { id: 141, class: vreg_128, preferred-register: '' }
+  - { id: 142, class: vreg_128, preferred-register: '' }
+  - { id: 143, class: vreg_128, preferred-register: '' }
+  - { id: 144, class: vreg_128, preferred-register: '' }
+  - { id: 145, class: vgpr_32, preferred-register: '' }
+  - { id: 146, class: vgpr_32, preferred-register: '' }
+  - { id: 147, class: vreg_128, preferred-register: '' }
+  - { id: 148, class: vreg_128, preferred-register: '' }
+  - { id: 149, class: vreg_128, preferred-register: '' }
+  - { id: 150, class: vreg_128, preferred-register: '' }
+  - { id: 151, class: vreg_128, preferred-register: '' }
+  - { id: 152, class: vreg_128, preferred-register: '' }
+  - { id: 153, class: vreg_128, preferred-register: '' }
+  - { id: 154, class: vreg_128, preferred-register: '' }
+  - { id: 155, class: vreg_128, preferred-register: '' }
+  - { id: 156, class: vreg_128, preferred-register: '' }
+  - { id: 157, class: vreg_128, preferred-register: '' }
+  - { id: 158, class: vreg_128, preferred-register: '' }
+  - { id: 159, class: vreg_128, preferred-register: '' }
+  - { id: 160, class: vreg_128, preferred-register: '' }
+  - { id: 161, class: vreg_128, preferred-register: '' }
+  - { id: 162, class: vgpr_32, preferred-register: '' }
+  - { id: 163, class: vgpr_32, preferred-register: '' }
+  - { id: 164, class: vgpr_32, preferred-register: '' }
+  - { id: 165, class: vreg_128, preferred-register: '' }
+  - { id: 166, class: vreg_128, preferred-register: '' }
+  - { id: 167, class: vreg_128, preferred-register: '' }
+  - { id: 168, class: vreg_128, preferred-register: '' }
+  - { id: 169, class: vreg_128, preferred-register: '' }
+  - { id: 170, class: vreg_128, preferred-register: '' }
+  - { id: 171, class: vgpr_32, preferred-register: '' }
+  - { id: 172, class: vreg_128, preferred-register: '' }
+  - { id: 173, class: vgpr_32, preferred-register: '' }
+  - { id: 174, class: vgpr_32, preferred-register: '' }
+  - { id: 175, class: vreg_128, preferred-register: '' }
+  - { id: 176, class: vreg_128, preferred-register: '' }
+  - { id: 177, class: vreg_128, preferred-register: '' }
+  - { id: 178, class: vreg_128, preferred-register: '' }
+  - { id: 179, class: vreg_128, preferred-register: '' }
+  - { id: 180, class: vreg_128, preferred-register: '' }
+  - { id: 181, class: vreg_128, preferred-register: '' }
+  - { id: 182, class: vreg_128, preferred-register: '' }
+  - { id: 183, class: vreg_128, preferred-register: '' }
+  - { id: 184, class: vreg_128, preferred-register: '' }
+  - { id: 185, class: vreg_128, preferred-register: '' }
+  - { id: 186, class: vgpr_32, preferred-register: '' }
+  - { id: 187, class: vgpr_32, preferred-register: '' }
+  - { id: 188, class: vreg_128, preferred-register: '' }
+  - { id: 189, class: vgpr_32, preferred-register: '' }
+  - { id: 190, class: vgpr_32, preferred-register: '' }
+  - { id: 191, class: vgpr_32, preferred-register: '' }
+  - { id: 192, class: vgpr_32, preferred-register: '' }
+  - { id: 193, class: vgpr_32, preferred-register: '' }
+  - { id: 194, class: vgpr_32, preferred-register: '' }
+  - { id: 195, class: vgpr_32, preferred-register: '' }
+  - { id: 196, class: vreg_64, preferred-register: '' }
+  - { id: 197, class: sreg_64, preferred-register: '' }
+  - { id: 198, class: vreg_128, preferred-register: '' }
+  - { id: 199, class: sreg_64, preferred-register: '' }
+  - { id: 200, class: vreg_128, preferred-register: '' }
+  - { id: 201, class: vgpr_32, preferred-register: '' }
+  - { id: 202, class: vreg_128, preferred-register: '' }
+  - { id: 203, class: sreg_64, preferred-register: '' }
+  - { id: 204, class: vreg_128, preferred-register: '' }
+  - { id: 205, class: vreg_128, preferred-register: '' }
+  - { id: 206, class: vgpr_32, preferred-register: '' }
+  - { id: 207, class: vreg_1, preferred-register: '' }
+  - { id: 208, class: sreg_64, preferred-register: '' }
+  - { id: 209, class: vreg_128, preferred-register: '' }
+  - { id: 210, class: vreg_128, preferred-register: '' }
+  - { id: 211, class: vreg_128, preferred-register: '' }
+  - { id: 212, class: vgpr_32, preferred-register: '' }
+  - { id: 213, class: vreg_1, preferred-register: '' }
+  - { id: 214, class: vreg_1, preferred-register: '' }
+  - { id: 215, class: sreg_64, preferred-register: '' }
+  - { id: 216, class: vreg_128, preferred-register: '' }
+  - { id: 217, class: vreg_128, preferred-register: '' }
+  - { id: 218, class: vreg_128, preferred-register: '' }
+  - { id: 219, class: vreg_1, preferred-register: '' }
+  - { id: 220, class: vreg_128, preferred-register: '' }
+  - { id: 221, class: sreg_64, preferred-register: '' }
+  - { id: 222, class: sreg_64, preferred-register: '' }
+  - { id: 223, class: sreg_64, preferred-register: '' }
+  - { id: 224, class: sreg_64, preferred-register: '' }
+  - { id: 225, class: sreg_64, preferred-register: '' }
+  - { id: 226, class: sreg_64, preferred-register: '' }
+liveins:         
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+constants:       
+body:             |
+  bb.0.bb8:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  
+    %197:sreg_64 = COPY $exec
+    %46:sgpr_32 = S_MOV_B32 0
+    undef %47.sub0:sreg_128 = COPY %46
+    %47.sub1:sreg_128 = COPY %46
+    %47.sub2:sreg_128 = COPY %46
+    %47.sub3:sreg_128 = COPY %46
+    $exec = S_WQM_B64 $exec, implicit-def dead $scc
+    S_CBRANCH_SCC0 %bb.2, implicit undef $scc
+  
+  bb.1:
+    successors: %bb.3(0x80000000)
+  
+    %45:sreg_128 = COPY killed %47
+    %142:vreg_128 = COPY killed %45
+    %198:vreg_128 = COPY killed %142
+    S_BRANCH %bb.3
+  
+  bb.2.bb9:
+    successors: %bb.4(0x80000000)
+  
+    %53:vgpr_32 = V_MUL_F32_e32 1031798784, undef %54:vgpr_32, implicit $exec
+    %55:vgpr_32 = V_FLOOR_F32_e32 killed %53, implicit $exec
+    %57:vgpr_32 = V_ADD_F32_e32 0, killed %55, implicit $exec
+    %58:vgpr_32 = V_CVT_U32_F32_e32 killed %57, implicit $exec
+    %135:vgpr_32 = V_LSHLREV_B32_e32 1, killed %58, implicit $exec
+    %48:sreg_64 = S_MOV_B64 0
+    %51:sreg_128 = COPY killed %47
+    %163:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %166:vreg_128 = COPY killed %51
+    %199:sreg_64 = COPY killed %48
+    %200:vreg_128 = IMPLICIT_DEF
+    %201:vgpr_32 = COPY killed %163
+    %202:vreg_128 = COPY killed %166
+    S_BRANCH %bb.4
+  
+  bb.3.Flow5:
+    successors: %bb.22(0x80000000)
+  
+    %141:vreg_128 = COPY killed %198
+    S_BRANCH %bb.22
+  
+  bb.4.bb19:
+    successors: %bb.8(0x40000000), %bb.9(0x40000000)
+  
+    %165:vreg_128 = COPY killed %202
+    %162:vgpr_32 = COPY killed %201
+    %147:vreg_128 = COPY killed %200
+    %3:sreg_64 = COPY killed %199
+    %136:vgpr_32 = V_OR_B32_e32 %162, %135, implicit $exec
+    %76:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %136, undef %78:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
+    %190:vgpr_32 = V_LSHRREV_B32_e32 30, killed %76.sub0, implicit $exec
+    %168:vreg_128 = COPY killed %165
+    %168.sub0:vreg_128 = COPY %46
+    %82:sreg_64 = V_CMP_NE_U32_e64 0, %190, implicit $exec
+    %84:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %190, implicit $exec
+    dead %86:vgpr_32 = V_CNDMASK_B32_e64 0, -1, killed %84, implicit $exec
+    %188:vreg_128 = COPY %168
+    %188.sub1:vreg_128 = COPY undef %86
+    %74:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
+    %73:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %208:sreg_64 = COPY %3
+    %209:vreg_128 = COPY %147
+    %210:vreg_128 = IMPLICIT_DEF
+    %211:vreg_128 = IMPLICIT_DEF
+    %212:vgpr_32 = IMPLICIT_DEF
+    %213:vreg_1 = COPY killed %73
+    %214:vreg_1 = COPY killed %74
+    %221:sreg_64 = COPY $exec, implicit-def $exec
+    %222:sreg_64 = S_AND_B64 %221, %82, implicit-def dead $scc
+    %11:sreg_64 = S_XOR_B64 %222, %221, implicit-def dead $scc
+    $exec = S_MOV_B64_term killed %222
+    SI_MASK_BRANCH %bb.9, implicit $exec
+    S_BRANCH %bb.8
+  
+  bb.5.Flow1:
+    successors: %bb.9(0x80000000)
+  
+    $exec = S_OR_B64 $exec, %35, implicit-def $scc
+    %17:vreg_1 = COPY killed %207
+    %191:vgpr_32 = COPY killed %206
+    %180:vreg_128 = COPY killed %205
+    %150:vreg_128 = COPY killed %204
+    %12:sreg_64 = COPY killed %203
+    %18:sreg_64 = S_AND_B64 $exec, %35, implicit-def $scc
+    %18:sreg_64 = S_OR_B64 %18, killed %12, implicit-def $scc
+    %108:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %208:sreg_64 = COPY killed %18
+    %209:vreg_128 = COPY killed %150
+    %210:vreg_128 = COPY killed %172
+    %211:vreg_128 = COPY killed %180
+    %212:vgpr_32 = COPY killed %191
+    %213:vreg_1 = COPY killed %17
+    %214:vreg_1 = COPY killed %108
+    S_BRANCH %bb.9
+  
+  bb.6.Flow2:
+    successors: %bb.7(0x40000000), %bb.18(0x40000000)
+  
+    $exec = S_OR_B64 $exec, killed %28, implicit-def $scc
+    %110:sreg_64 = V_CMP_NE_U32_e64 0, killed %27, implicit $exec
+    %218:vreg_128 = COPY killed %175
+    %219:vreg_1 = COPY killed %26
+    %19:sreg_64 = COPY $exec, implicit-def $exec
+    %223:sreg_64 = S_AND_B64 %19, %110, implicit-def dead $scc
+    $exec = S_MOV_B64_term killed %223
+    SI_MASK_BRANCH %bb.18, implicit $exec
+    S_BRANCH %bb.7
+  
+  bb.7.._crit_edge4332.thread:
+    successors: %bb.18(0x80000000)
+  
+    %111:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
+    %178:vreg_128 = COPY killed %188
+    %218:vreg_128 = COPY killed %178
+    %219:vreg_1 = COPY killed %111
+    S_BRANCH %bb.18
+  
+  bb.8..lr.ph4331:
+    successors: %bb.10(0x80000000)
+  
+    %90:sreg_64 = S_MOV_B64 0
+    %185:vreg_128 = COPY %188
+    %215:sreg_64 = COPY killed %90
+    %216:vreg_128 = COPY killed %185
+    %217:vreg_128 = COPY killed %168
+    S_BRANCH %bb.10
+  
+  bb.9.Flow:
+    successors: %bb.6(0x04000000), %bb.4(0x7c000000)
+  
+    $exec = S_OR_B64 $exec, %11, implicit-def $scc
+    %27:vreg_1 = COPY killed %214
+    %26:vreg_1 = COPY killed %213
+    %194:vgpr_32 = COPY killed %212
+    %182:vreg_128 = COPY killed %211
+    %175:vreg_128 = COPY killed %210
+    %152:vreg_128 = COPY killed %209
+    %20:sreg_64 = COPY killed %208
+    %28:sreg_64 = S_AND_B64 $exec, %11, implicit-def $scc
+    %28:sreg_64 = S_OR_B64 %28, killed %20, implicit-def $scc
+    %149:vreg_128 = COPY %152
+    %199:sreg_64 = COPY %28
+    %200:vreg_128 = COPY killed %149
+    %201:vgpr_32 = COPY killed %194
+    %202:vreg_128 = COPY killed %182
+    $exec = S_ANDN2_B64_term $exec, %28
+    S_CBRANCH_EXECNZ %bb.4, implicit $exec
+    S_BRANCH %bb.6
+  
+  bb.10.bb27:
+    successors: %bb.12(0x40000000), %bb.11(0x40000000)
+  
+    %169:vreg_128 = COPY killed %217
+    %184:vreg_128 = COPY killed %216
+    %29:sreg_64 = COPY killed %215
+    S_CBRANCH_SCC1 %bb.12, implicit undef $scc
+    S_BRANCH %bb.11
+  
+  bb.11.bb30:
+    successors: %bb.12(0x80000000)
+  
+  
+  bb.12.._crit_edge:
+    successors: %bb.14(0x40000000), %bb.13(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.14, implicit undef $scc
+    S_BRANCH %bb.13
+  
+  bb.13.bb38:
+    successors: %bb.14(0x80000000)
+  
+  
+  bb.14.._crit_edge4245:
+    successors: %bb.15(0x40000000), %bb.16(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.16, implicit undef $scc
+    S_BRANCH %bb.15
+  
+  bb.15..lr.ph4285:
+    successors: %bb.16(0x80000000)
+  
+  
+  bb.16.._crit_edge4286:
+    successors: %bb.17(0x04000000), %bb.10(0x7c000000)
+  
+    undef %172.sub0:vreg_128 = COPY %169.sub0
+    %172.sub2:vreg_128 = COPY %184.sub2
+    %172.sub3:vreg_128 = COPY killed %184.sub3
+    %95:sreg_64 = V_CMP_GE_U32_e64 killed %169.sub0, %190, implicit $exec
+    %34:sreg_64 = S_OR_B64 killed %95, killed %29, implicit-def $scc
+    %170:vreg_128 = COPY %172
+    %215:sreg_64 = COPY %34
+    %216:vreg_128 = COPY %172
+    %217:vreg_128 = COPY killed %170
+    $exec = S_ANDN2_B64_term $exec, %34
+    S_CBRANCH_EXECNZ %bb.10, implicit $exec
+    S_BRANCH %bb.17
+  
+  bb.17.._crit_edge4332:
+    successors: %bb.20(0x40000000), %bb.5(0x40000000)
+  
+    $exec = S_OR_B64 $exec, killed %34, implicit-def $scc
+    %101:sreg_64 = V_CMP_LT_U32_e64 11, killed %190, implicit $exec
+    %99:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
+    %203:sreg_64 = COPY %3
+    %204:vreg_128 = COPY killed %147
+    %205:vreg_128 = IMPLICIT_DEF
+    %206:vgpr_32 = IMPLICIT_DEF
+    %207:vreg_1 = COPY killed %99
+    %224:sreg_64 = COPY $exec, implicit-def $exec
+    %225:sreg_64 = S_AND_B64 %224, %101, implicit-def dead $scc
+    %35:sreg_64 = S_XOR_B64 %225, %224, implicit-def dead $scc
+    $exec = S_MOV_B64_term killed %225
+    SI_MASK_BRANCH %bb.5, implicit $exec
+    S_BRANCH %bb.20
+  
+  bb.18.Flow3:
+    successors: %bb.19(0x40000000), %bb.21(0x40000000)
+  
+    $exec = S_OR_B64 $exec, killed %19, implicit-def $scc
+    %37:vreg_1 = COPY killed %219
+    %177:vreg_128 = COPY killed %218
+    %113:sreg_64 = V_CMP_NE_U32_e64 0, killed %37, implicit $exec
+    %220:vreg_128 = COPY killed %152
+    %38:sreg_64 = COPY $exec, implicit-def $exec
+    %226:sreg_64 = S_AND_B64 %38, %113, implicit-def dead $scc
+    $exec = S_MOV_B64_term killed %226
+    SI_MASK_BRANCH %bb.21, implicit $exec
+    S_BRANCH %bb.19
+  
+  bb.19..loopexit4453:
+    successors: %bb.21(0x80000000)
+  
+    %154:vreg_128 = COPY killed %177
+    %220:vreg_128 = COPY killed %154
+    S_BRANCH %bb.21
+  
+  bb.20.bb44:
+    successors: %bb.5(0x80000000)
+  
+    %105:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %106:sreg_64 = V_CMP_NE_U32_e64 0, killed %162, implicit $exec
+    %41:sreg_64 = S_OR_B64 killed %106, killed %3, implicit-def $scc
+    %151:vreg_128 = COPY %172
+    %193:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    %203:sreg_64 = COPY killed %41
+    %204:vreg_128 = COPY killed %151
+    %205:vreg_128 = COPY %172
+    %206:vgpr_32 = COPY killed %193
+    %207:vreg_1 = COPY killed %105
+    S_BRANCH %bb.5
+  
+  bb.21.Flow4:
+    successors: %bb.3(0x80000000)
+  
+    $exec = S_OR_B64 $exec, killed %38, implicit-def $scc
+    %153:vreg_128 = COPY killed %220
+    %143:vreg_128 = COPY killed %153
+    %198:vreg_128 = COPY killed %143
+    S_BRANCH %bb.3
+  
+  bb.22.bb47:
+    %117:vgpr_32 = V_ADD_F32_e32 target-flags(amdgpu-rel32-lo) 0, %141.sub3, implicit $exec
+    %118:vgpr_32 = V_ADD_F32_e32 target-flags(amdgpu-gotprel32-hi) 0, killed %141.sub2, implicit $exec
+    undef %196.sub0:vreg_64 = COPY killed %118
+    %196.sub1:vreg_64 = COPY killed %117
+    $exec = S_AND_B64 $exec, killed %197, implicit-def dead $scc
+    %120:sreg_32_xm0 = S_MOV_B32 0
+    undef %121.sub0:sreg_256 = COPY %120
+    %121.sub1:sreg_256 = COPY %120
+    %121.sub2:sreg_256 = COPY %120
+    %121.sub3:sreg_256 = COPY %120
+    %121.sub4:sreg_256 = COPY %120
+    %121.sub5:sreg_256 = COPY %120
+    %121.sub6:sreg_256 = COPY %120
+    %121.sub7:sreg_256 = COPY killed %120
+    %122:vgpr_32 = IMAGE_SAMPLE_V1_V2 killed %196, killed %121, undef %124:sreg_128, 8, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
+    %126:vgpr_32 = V_MUL_F32_e32 0, killed %122, implicit $exec
+    %127:vgpr_32 = V_MUL_F32_e32 0, killed %126, implicit $exec
+    %128:vgpr_32 = V_MAD_F32 0, killed %127, 0, 0, 0, 0, 0, 0, implicit $exec
+    %129:vgpr_32 = V_MAX_F32_e32 0, killed %128, implicit $exec
+    %131:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, killed %129, 0, 1065353216, 0, implicit $exec
+    EXP 0, undef %132:vgpr_32, killed %131, undef %133:vgpr_32, undef %134:vgpr_32, -1, -1, 15, implicit $exec
+    S_ENDPGM
+
+...

test/CodeGen/AMDGPU/coalescing-with-subregs-bad-identical.mir

+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+
+# With one version of the D48102 fix, this test failed with
+# Assertion failed: (Id != S.end() && T != S.end() && T->valno == Id->valno), function pruneSubRegValues, file ../lib/CodeGen/RegisterCoalescer.cpp, line 2870.
+
+# GCN: {{^body}}
+
+--- |
+  ; ModuleID = 'cutdown.ll'
+  source_filename = "cutdown.ll"
+  target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+  target triple = "amdgcn--amdpal"
+  
+  ; Function Attrs: nounwind readnone speculatable
+  declare float @llvm.minnum.f32(float, float) #0
+  
+  ; Function Attrs: nounwind
+  define dllexport amdgpu_cs void @_amdgpu_cs_main(<3 x i32> %arg) local_unnamed_addr #1 !spirv.ExecutionModel !1 {
+  .entry:
+    br i1 undef, label %bb, label %Flow3, !amdgpu.uniform !2
+  
+  bb:                                               ; preds = %.entry
+    br i1 undef, label %bb7, label %Flow2, !amdgpu.uniform !2
+  
+  bb7:                                              ; preds = %bb
+    %tmp1 = extractelement <3 x i32> %arg, i32 0
+    %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 0, i32 undef>, i32 %tmp1, i32 0
+    %tmp3 = insertelement <4 x i32> %tmp2, i32 undef, i32 1
+    %tmp4 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v4i32.v8i32(<4 x i32> %tmp3, <8 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false) #6
+    %tmp5 = extractelement <4 x float> %tmp4, i32 0
+    %tmp6 = bitcast float %tmp5 to i32
+    %tmp8 = insertelement <4 x i32> undef, i32 %tmp6, i32 0
+    %tmp9 = shufflevector <4 x i32> %tmp8, <4 x i32> undef, <4 x i32> zeroinitializer
+    %tmp10 = bitcast <4 x i32> %tmp9 to <4 x float>
+    %tmp11 = fmul reassoc nnan arcp contract <4 x float> %tmp10, zeroinitializer
+    %tmp12 = fadd reassoc nnan arcp contract <4 x float> %tmp11, zeroinitializer
+    %tmp15 = bitcast <4 x float> %tmp12 to <4 x i32>
+    %tmp16 = shufflevector <4 x i32> %tmp15, <4 x i32> undef, <3 x i32> <i32 3, i32 3, i32 3>
+    %tmp17 = bitcast <3 x i32> %tmp16 to <3 x float>
+    %x2.i = extractelement <3 x float> %tmp17, i32 2
+    %tmp18 = fdiv float 1.000000e+00, %x2.i
+    %tmp19 = fmul float 0.000000e+00, %tmp18
+    %tmp20 = bitcast float %tmp19 to i32
+    %tmp21 = insertelement <3 x i32> undef, i32 %tmp20, i32 0
+    %tmp22 = shufflevector <3 x i32> %tmp21, <3 x i32> undef, <3 x i32> zeroinitializer
+    %tmp23 = bitcast <3 x i32> %tmp22 to <3 x float>
+    %tmp24 = fmul reassoc nnan arcp contract <3 x float> zeroinitializer, %tmp23
+    %tmp25 = fadd reassoc nnan arcp contract <3 x float> %tmp24, zeroinitializer
+    %tmp26 = bitcast <3 x float> %tmp25 to <3 x i32>
+    %tmp27 = shufflevector <3 x i32> %tmp26, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
+    br i1 undef, label %.lr.ph5605, label %Flow, !amdgpu.uniform !2
+  
+  .lr.ph5605:                                       ; preds = %bb7
+    %bc5216 = bitcast <4 x i32> %tmp27 to <4 x float>
+    %tmp28 = extractelement <4 x float> %bc5216, i32 0
+    %tmp29 = fmul reassoc nnan arcp contract float %tmp28, 0.000000e+00
+    %tmp30 = fadd reassoc nnan arcp contract float %tmp29, 0.000000e+00
+    %tmp32 = tail call float @llvm.minnum.f32(float %tmp30, float 1.000000e+00) #6
+    %tmp33 = fcmp une float %tmp32, 1.000000e+00
+    %tmp36 = select i1 %tmp33, i32 2143289344, i32 0
+    %tmp37 = bitcast i32 %tmp36 to float
+    %tmp38 = fcmp ogt float %tmp37, 0.000000e+00
+    %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %tmp38)
+    %1 = extractvalue { i1, i64 } %0, 0
+    %2 = extractvalue { i1, i64 } %0, 1
+    br i1 %1, label %bb39, label %._crit_edge5606
+  
+  bb39:                                             ; preds = %.lr.ph5605
+    br i1 undef, label %bb40, label %._crit_edge5606, !structurizecfg.uniform !2, !amdgpu.uniform !2
+  
+  bb40:                                             ; preds = %bb39
+    br label %._crit_edge5606, !structurizecfg.uniform !2
+  
+  Flow:                                             ; preds = %._crit_edge5606, %bb7
+    %3 = phi <4 x i32> [ %__llpc_global_proxy_r4.12.vec.insert3549, %._crit_edge5606 ], [ undef, %bb7 ]
+    %4 = phi i1 [ false, %._crit_edge5606 ], [ true, %bb7 ]
+    br i1 %4, label %.lr.ph5583, label %Flow1, !amdgpu.uniform !2
+  
+  ._crit_edge5606:                                  ; preds = %.lr.ph5605, %bb39, %bb40
+    call void @llvm.amdgcn.end.cf(i64 %2)
+    %__llpc_global_proxy_r4.12.vec.insert3549 = insertelement <4 x i32> %tmp27, i32 undef, i32 3
+    br label %Flow
+  
+  .lr.ph5583:                                       ; preds = %Flow
+    %__llpc_global_proxy_r4.12.vec.insert3399 = insertelement <4 x i32> %tmp27, i32 undef, i32 3
+    br i1 undef, label %bb48, label %._crit_edge5584, !structurizecfg.uniform !2, !amdgpu.uniform !2
+  
+  bb48:                                             ; preds = %.lr.ph5583
+    br label %._crit_edge5584, !structurizecfg.uniform !2
+  
+  Flow1:                                            ; preds = %bb50, %._crit_edge5584, %Flow
+    %5 = phi <4 x i32> [ %__llpc_global_proxy_r4.3, %bb50 ], [ %__llpc_global_proxy_r4.3, %._crit_edge5584 ], [ %3, %Flow ]
+    br label %bb56
+  
+  ._crit_edge5584:                                  ; preds = %.lr.ph5583, %bb48
+    %__llpc_global_proxy_r4.3 = phi <4 x i32> [ %__llpc_global_proxy_r4.12.vec.insert3399, %.lr.ph5583 ], [ zeroinitializer, %bb48 ]
+    br i1 undef, label %bb50, label %Flow1, !structurizecfg.uniform !2, !amdgpu.uniform !2
+  
+  bb50:                                             ; preds = %._crit_edge5584
+    %tmp51 = load <4 x i32>, <4 x i32> addrspace(4)* undef, align 16
+    br label %Flow1, !structurizecfg.uniform !2
+  
+  Flow2:                                            ; preds = %bb89, %bb
+    br label %bb94
+  
+  bb56:                                             ; preds = %Flow1
+    %__llpc_global_proxy_r4.4 = phi <4 x i32> [ %5, %Flow1 ]
+    %bc5178 = bitcast <4 x i32> %__llpc_global_proxy_r4.4 to <4 x float>
+    %tmp57 = extractelement <4 x float> %bc5178, i32 0
+    %tmp58 = fmul reassoc nnan arcp contract float %tmp57, 0.000000e+00
+    %tmp59 = fadd reassoc nnan arcp contract float %tmp58, 0.000000e+00
+    %tmp60 = bitcast float %tmp59 to i32
+    %tmp61 = insertelement <2 x i32> undef, i32 %tmp60, i32 1
+    %tmp62 = bitcast <2 x i32> %tmp61 to <2 x float>
+    %tmp63 = fmul reassoc nnan arcp contract <2 x float> zeroinitializer, %tmp62
+    %tmp64 = fadd reassoc nnan arcp contract <2 x float> zeroinitializer, %tmp63
+    %tmp65 = fmul reassoc nnan arcp contract <2 x float> %tmp64, <float 5.000000e-01, float -5.000000e-01>
+    %tmp66 = fadd reassoc nnan arcp contract <2 x float> %tmp65, <float 5.000000e-01, float 5.000000e-01>
+    %tmp67 = fmul reassoc nnan arcp contract <2 x float> %tmp66, zeroinitializer
+    %tmp68 = fadd reassoc nnan arcp contract <2 x float> %tmp67, <float -5.000000e-01, float -5.000000e-01>
+    %tmp69 = fptosi <2 x float> %tmp68 to <2 x i32>
+    %tmp70 = extractelement <2 x i32> %tmp69, i32 1
+    %tmp71 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 12, i1 false) #6
+    %tmp72 = mul i32 %tmp70, %tmp71
+    %tmp74 = shl i32 %tmp72, 2
+    %tmp75 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> undef, i32 %tmp74, i32 0, i1 false, i1 false)
+    %tmp76 = insertelement <4 x float> undef, float %tmp75, i64 0
+    %bc5181 = bitcast <4 x float> %tmp76 to <4 x i32>
+    %tmp77 = shufflevector <4 x i32> %bc5181, <4 x i32> zeroinitializer, <2 x i32> <i32 0, i32 4>
+    %tmp78 = icmp ne <2 x i32> %tmp77, zeroinitializer
+    %tmp79 = sext <2 x i1> %tmp78 to <2 x i32>
+    %tmp80 = extractelement <2 x i32> %tmp79, i32 0
+    %tmp82 = icmp eq i32 %tmp80, 0
+    %6 = xor i1 %tmp82, true
+    %7 = call { i1, i64 } @llvm.amdgcn.if(i1 %6)
+    %8 = extractvalue { i1, i64 } %7, 0
+    %9 = extractvalue { i1, i64 } %7, 1
+    br i1 %8, label %bb83, label %bb89
+  
+  bb83:                                             ; preds = %bb56
+    %tmp84 = call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> undef, i32 0, i1 false) #6
+    br label %bb89
+  
+  bb89:                                             ; preds = %bb83, %bb56
+    call void @llvm.amdgcn.end.cf(i64 %9)
+    br label %Flow2
+  
+  Flow3:                                            ; preds = %bb94, %bb115, %.entry
+    br label %bb121
+  
+  bb94:                                             ; preds = %Flow2
+    br i1 undef, label %Flow3, label %bb95, !structurizecfg.uniform !2, !amdgpu.uniform !2
+  
+  bb95:                                             ; preds = %bb94
+    br i1 undef, label %bb109, label %bb96, !structurizecfg.uniform !2, !amdgpu.uniform !2
+  
+  bb96:                                             ; preds = %bb95
+    br i1 undef, label %._crit_edge, label %bb97, !structurizecfg.uniform !2, !amdgpu.uniform !2
+  
+  bb97:                                             ; preds = %bb96
+    br i1 undef, label %bb98, label %._crit_edge, !structurizecfg.uniform !2, !amdgpu.uniform !2
+  
+  bb98:                                             ; preds = %bb97
+    br label %._crit_edge, !structurizecfg.uniform !2
+  
+  ._crit_edge:                                      ; preds = %bb96, %bb97, %bb98
+    br label %bb115, !structurizecfg.uniform !2
+  
+  bb109:                                            ; preds = %bb95
+    br label %bb115, !structurizecfg.uniform !2
+  
+  bb115:                                            ; preds = %._crit_edge, %bb109
+    br label %Flow3, !structurizecfg.uniform !2
+  
+  bb121:                                            ; preds = %Flow3
+    ret void
+  }
+  
+  ; Function Attrs: nounwind readonly
+  declare <4 x float> @llvm.amdgcn.image.load.v4f32.v4i32.v8i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
+  
+  ; Function Attrs: nounwind readnone
+  declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i1) #3
+  
+  ; Function Attrs: nounwind readnone
+  declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i1) #3
+  
+  ; Function Attrs: nounwind readonly
+  declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #2
+  
+  ; Function Attrs: convergent nounwind
+  declare { i1, i64 } @llvm.amdgcn.if(i1) #4
+  
+  ; Function Attrs: convergent nounwind
+  declare { i1, i64 } @llvm.amdgcn.else(i64) #4
+  
+  ; Function Attrs: convergent nounwind readnone
+  declare i64 @llvm.amdgcn.break(i64) #5
+  
+  ; Function Attrs: convergent nounwind readnone
+  declare i64 @llvm.amdgcn.if.break(i1, i64) #5
+  
+  ; Function Attrs: convergent nounwind readnone
+  declare i64 @llvm.amdgcn.else.break(i64, i64) #5
+  
+  ; Function Attrs: convergent nounwind
+  declare i1 @llvm.amdgcn.loop(i64) #4
+  
+  ; Function Attrs: convergent nounwind
+  declare void @llvm.amdgcn.end.cf(i64) #4
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #6
+  
+  attributes #0 = { nounwind readnone speculatable "target-cpu"="gfx803" }
+  attributes #1 = { nounwind "target-cpu"="gfx803" }
+  attributes #2 = { nounwind readonly "target-cpu"="gfx803" }
+  attributes #3 = { nounwind readnone "target-cpu"="gfx803" }
+  attributes #4 = { convergent nounwind }
+  attributes #5 = { convergent nounwind readnone }
+  attributes #6 = { nounwind }
+  
+  !amdgpu.pal.metadata = !{!0}
+  
+  !0 = !{i32 268435482, i32 1, i32 268435488, i32 -1, i32 268435480, i32 411087283, i32 268435481, i32 425383423, i32 268435538, i32 64, i32 268435539, i32 0, i32 11794, i32 2883584, i32 11795, i32 6022, i32 11783, i32 16, i32 11784, i32 16, i32 11785, i32 1, i32 268435530, i32 0, i32 268435495, i32 0, i32 268435502, i32 0, i32 268435509, i32 256, i32 268435516, i32 104, i32 268435456, i32 1246098527, i32 268435457, i32 -1710647087, i32 11840, i32 268435456, i32 11842, i32 0}
+  !1 = !{i32 5}
+  !2 = !{}
+
+...
+---
+name:            _amdgpu_cs_main
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: sreg_128, preferred-register: '' }
+  - { id: 1, class: sreg_64, preferred-register: '' }
+  - { id: 2, class: sreg_128, preferred-register: '' }
+  - { id: 3, class: vreg_1, preferred-register: '' }
+  - { id: 4, class: sreg_128, preferred-register: '' }
+  - { id: 5, class: sreg_128, preferred-register: '' }
+  - { id: 6, class: sreg_128, preferred-register: '' }
+  - { id: 7, class: sreg_128, preferred-register: '' }
+  - { id: 8, class: sreg_128, preferred-register: '' }
+  - { id: 9, class: sreg_64, preferred-register: '' }
+  - { id: 10, class: vgpr_32, preferred-register: '' }
+  - { id: 11, class: vgpr_32, preferred-register: '' }
+  - { id: 12, class: vgpr_32, preferred-register: '' }
+  - { id: 13, class: sreg_128, preferred-register: '' }
+  - { id: 14, class: sreg_128, preferred-register: '' }
+  - { id: 15, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 16, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 17, class: sreg_128, preferred-register: '' }
+  - { id: 18, class: vgpr_32, preferred-register: '' }
+  - { id: 19, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 20, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 21, class: sreg_128, preferred-register: '' }
+  - { id: 22, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 23, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 24, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 25, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 26, class: sreg_256, preferred-register: '' }
+  - { id: 27, class: vgpr_32, preferred-register: '' }
+  - { id: 28, class: vreg_128, preferred-register: '' }
+  - { id: 29, class: vgpr_32, preferred-register: '' }
+  - { id: 30, class: vgpr_32, preferred-register: '' }
+  - { id: 31, class: vgpr_32, preferred-register: '' }
+  - { id: 32, class: vgpr_32, preferred-register: '' }
+  - { id: 33, class: vgpr_32, preferred-register: '' }
+  - { id: 34, class: vgpr_32, preferred-register: '' }
+  - { id: 35, class: vgpr_32, preferred-register: '' }
+  - { id: 36, class: vgpr_32, preferred-register: '' }
+  - { id: 37, class: vgpr_32, preferred-register: '' }
+  - { id: 38, class: vgpr_32, preferred-register: '' }
+  - { id: 39, class: sreg_128, preferred-register: '' }
+  - { id: 40, class: sreg_64, preferred-register: '' }
+  - { id: 41, class: vgpr_32, preferred-register: '' }
+  - { id: 42, class: vgpr_32, preferred-register: '' }
+  - { id: 43, class: vgpr_32, preferred-register: '' }
+  - { id: 44, class: vgpr_32, preferred-register: '' }
+  - { id: 45, class: vgpr_32, preferred-register: '' }
+  - { id: 46, class: sreg_64_xexec, preferred-register: '$vcc' }
+  - { id: 47, class: vgpr_32, preferred-register: '' }
+  - { id: 48, class: vgpr_32, preferred-register: '' }
+  - { id: 49, class: vgpr_32, preferred-register: '' }
+  - { id: 50, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 51, class: vgpr_32, preferred-register: '' }
+  - { id: 52, class: sreg_64, preferred-register: '' }
+  - { id: 53, class: sreg_64, preferred-register: '' }
+  - { id: 54, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 55, class: sreg_128, preferred-register: '' }
+  - { id: 56, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 57, class: sreg_128, preferred-register: '' }
+  - { id: 58, class: vgpr_32, preferred-register: '' }
+  - { id: 59, class: vgpr_32, preferred-register: '' }
+  - { id: 60, class: vgpr_32, preferred-register: '' }
+  - { id: 61, class: vgpr_32, preferred-register: '' }
+  - { id: 62, class: vgpr_32, preferred-register: '' }
+  - { id: 63, class: vgpr_32, preferred-register: '' }
+  - { id: 64, class: vgpr_32, preferred-register: '' }
+  - { id: 65, class: vgpr_32, preferred-register: '' }
+  - { id: 66, class: vgpr_32, preferred-register: '' }
+  - { id: 67, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 68, class: sreg_128, preferred-register: '' }
+  - { id: 69, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 70, class: sreg_32, preferred-register: '' }
+  - { id: 71, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 72, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 73, class: vgpr_32, preferred-register: '' }
+  - { id: 74, class: vgpr_32, preferred-register: '' }
+  - { id: 75, class: sreg_128, preferred-register: '' }
+  - { id: 76, class: vgpr_32, preferred-register: '' }
+  - { id: 77, class: sreg_64, preferred-register: '$vcc' }
+  - { id: 78, class: vreg_128, preferred-register: '' }
+  - { id: 79, class: vgpr_32, preferred-register: '' }
+  - { id: 80, class: vgpr_32, preferred-register: '' }
+  - { id: 81, class: vreg_128, preferred-register: '' }
+  - { id: 82, class: vgpr_32, preferred-register: '' }
+  - { id: 83, class: vgpr_32, preferred-register: '' }
+  - { id: 84, class: vgpr_32, preferred-register: '' }
+  - { id: 85, class: vreg_128, preferred-register: '' }
+  - { id: 86, class: vreg_128, preferred-register: '' }
+  - { id: 87, class: vreg_128, preferred-register: '' }
+  - { id: 88, class: vreg_128, preferred-register: '' }
+  - { id: 89, class: vreg_128, preferred-register: '' }
+  - { id: 90, class: vreg_128, preferred-register: '' }
+  - { id: 91, class: vreg_128, preferred-register: '' }
+  - { id: 92, class: vreg_128, preferred-register: '' }
+  - { id: 93, class: vgpr_32, preferred-register: '' }
+  - { id: 94, class: vgpr_32, preferred-register: '' }
+  - { id: 95, class: vreg_128, preferred-register: '' }
+  - { id: 96, class: vreg_1, preferred-register: '' }
+  - { id: 97, class: vreg_128, preferred-register: '' }
+  - { id: 98, class: vreg_128, preferred-register: '' }
+  - { id: 99, class: sreg_64, preferred-register: '' }
+  - { id: 100, class: sreg_64, preferred-register: '' }
+liveins:         
+  - { reg: '$vgpr0', virtual-reg: '%10' }
+  - { reg: '$vgpr1', virtual-reg: '%11' }
+  - { reg: '$vgpr2', virtual-reg: '%12' }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+constants:       
+body:             |
+  bb.0..entry:
+    successors: %bb.1(0x40000000), %bb.20(0x40000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2
+  
+    %10:vgpr_32 = COPY killed $vgpr0
+    S_CBRANCH_SCC1 %bb.20, implicit undef $scc
+  
+  bb.1.bb:
+    successors: %bb.2(0x40000000), %bb.16(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.16, implicit undef $scc
+  
+  bb.2.bb7:
+    successors: %bb.4(0x40000000), %bb.3(0x40000000)
+  
+    %20:sreg_32_xm0 = S_MOV_B32 0
+    %83:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    undef %81.sub0:vreg_128 = COPY killed %10
+    %81.sub2:vreg_128 = COPY killed %83
+    undef %26.sub0:sreg_256 = COPY %20
+    %26.sub1:sreg_256 = COPY %20
+    %26.sub2:sreg_256 = COPY %20
+    %26.sub3:sreg_256 = COPY %20
+    %26.sub4:sreg_256 = COPY %20
+    %26.sub5:sreg_256 = COPY %20
+    %26.sub6:sreg_256 = COPY %20
+    %26.sub7:sreg_256 = COPY killed %20
+    %27:vgpr_32 = IMAGE_LOAD_V1_V4 killed %81, killed %26, 1, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
+    %31:vgpr_32 = V_MAD_F32 0, killed %27, 0, 0, 0, 0, 0, 0, implicit $exec
+    %32:vgpr_32 = V_RCP_F32_e32 killed %31, implicit $exec
+    %33:vgpr_32 = V_MUL_F32_e32 0, killed %32, implicit $exec
+    %34:vgpr_32 = V_MAD_F32 0, killed %33, 0, 0, 0, 0, 0, 0, implicit $exec
+    dead %35:vgpr_32 = V_MAC_F32_e32 undef %36:vgpr_32, undef %37:vgpr_32, undef %35, implicit $exec
+    undef %85.sub0:vreg_128 = COPY %34
+    %18:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
+    S_CBRANCH_SCC0 %bb.4, implicit undef $scc
+  
+  bb.3:
+    successors: %bb.6(0x80000000)
+  
+    %95:vreg_128 = IMPLICIT_DEF
+    %96:vreg_1 = COPY killed %18
+    S_BRANCH %bb.6
+  
+  bb.4..lr.ph5605:
+    successors: %bb.5(0x40000000), %bb.7(0x40000000)
+  
+    %43:vgpr_32 = V_MAD_F32 0, killed %34, 0, 0, 0, 0, 0, 0, implicit $exec
+    %45:vgpr_32 = V_MIN_F32_e32 1065353216, killed %43, implicit $exec
+    %46:sreg_64_xexec = V_CMP_NEQ_F32_e64 0, 1065353216, 0, killed %45, 0, implicit $exec
+    %47:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
+    %49:vgpr_32 = V_CNDMASK_B32_e64 0, killed %47, killed %46, implicit $exec
+    %50:sreg_64 = V_CMP_LT_F32_e64 0, 0, 0, killed %49, 0, implicit $exec
+    %1:sreg_64 = COPY $exec, implicit-def $exec
+    %99:sreg_64 = S_AND_B64 %1, %50, implicit-def dead $scc
+    $exec = S_MOV_B64_term killed %99
+    SI_MASK_BRANCH %bb.7, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.5.bb39:
+    successors: %bb.7(0x80000000)
+  
+    S_BRANCH %bb.7
+  
+  bb.6.Flow:
+    successors: %bb.8(0x40000000), %bb.10(0x40000000)
+  
+    %3:vreg_1 = COPY killed %96
+    %91:vreg_128 = COPY killed %95
+    %54:sreg_64 = V_CMP_NE_U32_e64 0, killed %3, implicit $exec
+    %53:sreg_64 = S_AND_B64 $exec, killed %54, implicit-def dead $scc
+    $vcc = COPY killed %53
+    %97:vreg_128 = COPY killed %91
+    S_CBRANCH_VCCNZ %bb.8, implicit killed $vcc
+    S_BRANCH %bb.10
+  
+  bb.7.._crit_edge5606:
+    successors: %bb.6(0x80000000)
+  
+    $exec = S_OR_B64 $exec, killed %1, implicit-def $scc
+    %51:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %95:vreg_128 = COPY %85
+    %96:vreg_1 = COPY killed %51
+    S_BRANCH %bb.6
+  
+  bb.8..lr.ph5583:
+    successors: %bb.9(0x40000000), %bb.11(0x40000000)
+  
+    %98:vreg_128 = COPY killed %85
+    S_CBRANCH_SCC1 %bb.11, implicit undef $scc
+    S_BRANCH %bb.9
+  
+  bb.9.bb48:
+    successors: %bb.11(0x80000000)
+  
+    %56:sreg_32_xm0 = S_MOV_B32 0
+    undef %57.sub0:sreg_128 = COPY %56
+    %57.sub1:sreg_128 = COPY %56
+    %57.sub2:sreg_128 = COPY %56
+    %57.sub3:sreg_128 = COPY killed %56
+    %55:sreg_128 = COPY killed %57
+    %87:vreg_128 = COPY killed %55
+    %98:vreg_128 = COPY killed %87
+    S_BRANCH %bb.11
+  
+  bb.10.Flow1:
+    successors: %bb.13(0x80000000)
+  
+    %88:vreg_128 = COPY killed %97
+    S_BRANCH %bb.13
+  
+  bb.11.._crit_edge5584:
+    successors: %bb.12(0x40000000), %bb.21(0x40000000)
+  
+    %86:vreg_128 = COPY killed %98
+    S_CBRANCH_SCC0 %bb.12, implicit undef $scc
+  
+  bb.21:
+    successors: %bb.10(0x80000000)
+  
+    %97:vreg_128 = COPY killed %86
+    S_BRANCH %bb.10
+  
+  bb.12.bb50:
+    successors: %bb.10(0x80000000)
+  
+    %97:vreg_128 = COPY killed %86
+    S_BRANCH %bb.10
+  
+  bb.13.bb56:
+    successors: %bb.14(0x40000000), %bb.15(0x40000000)
+  
+    %60:vgpr_32 = V_MAD_F32 0, killed %88.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec
+    %61:vgpr_32 = V_MAD_F32 0, killed %60, 0, 0, 0, 0, 0, 0, implicit $exec
+    %64:vgpr_32 = V_MAD_F32 0, killed %61, 0, -1090519040, 0, 1056964608, 0, 0, implicit $exec
+    %65:vgpr_32 = V_MAD_F32 0, killed %64, 0, 0, 0, -1090519040, 0, 0, implicit $exec
+    %66:vgpr_32 = V_CVT_I32_F32_e32 killed %65, implicit $exec
+    %67:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %68:sreg_128, 12, 0 :: (dereferenceable invariant load 4)
+    %93:vgpr_32 = V_MUL_LO_I32 killed %66, killed %67, implicit $exec
+    %94:vgpr_32 = V_LSHLREV_B32_e32 2, killed %93, implicit $exec
+    %73:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %94, undef %75:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
+    %77:sreg_64 = V_CMP_NE_U32_e64 0, killed %73, implicit $exec
+    %9:sreg_64 = COPY $exec, implicit-def $exec
+    %100:sreg_64 = S_AND_B64 %9, %77, implicit-def dead $scc
+    $exec = S_MOV_B64_term killed %100
+    SI_MASK_BRANCH %bb.15, implicit $exec
+    S_BRANCH %bb.14
+  
+  bb.14.bb83:
+    successors: %bb.15(0x80000000)
+  
+  
+  bb.15.bb89:
+    successors: %bb.16(0x80000000)
+  
+    $exec = S_OR_B64 $exec, killed %9, implicit-def $scc
+    S_BRANCH %bb.16
+  
+  bb.16.bb94:
+    successors: %bb.20(0x40000000), %bb.17(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.20, implicit undef $scc
+  
+  bb.17.bb95:
+    successors: %bb.18(0x40000000), %bb.19(0x40000000)
+  
+    S_CBRANCH_SCC1 %bb.18, implicit undef $scc
+    S_BRANCH %bb.19
+  
+  bb.18.bb109:
+    successors: %bb.19(0x80000000)
+  
+  
+  bb.19.bb115:
+    successors: %bb.20(0x80000000)
+  
+  
+  bb.20.bb121:
+    S_ENDPGM
+
+...

test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir

+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing,rename-independent-subregs %s -o - | FileCheck -check-prefix=GCN %s
+
+# This test is for a bug where the following happens:
+#
+# Inside the loop, %29.sub2 is used in a V_LSHLREV whose result is then used
+# in an LDS read. %29 is a 128 bit value that is linked by copies to
+# %45 (from phi elimination), %28 (the value in the loop pre-header),
+# %31 (defined and subreg-modified in the loop, and used after the loop)
+# and %30:
+#
+#     %45:vreg_128 = COPY killed %28
+# bb.1:
+#     %29:vreg_128 = COPY killed %45
+#     %39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec
+#     %31:vreg_128 = COPY killed %29
+#     %31.sub1:vreg_128 = COPY %34
+#     %30:vreg_128 = COPY %31
+#     %45:vreg_128 = COPY killed %30
+#     S_CBRANCH_EXECNZ %bb.39, implicit $exec
+#     S_BRANCH %bb.40
+# bb.2:
+#     undef %32.sub0:vreg_128 = COPY killed %31.sub0
+#
+# So this coalesces together into a single 128 bit value whose sub1 is modified
+# in the loop, but the sub2 used in the V_LSHLREV is not modified in the loop.
+#
+# The bug is that the coalesced value has a L00000004 subrange (for sub2) that
+# says that it is not live up to the end of the loop block. The symptom is that
+# Rename Independent Subregs separates sub2 into its own register, and it is
+# not live round the loop, so that pass adds an IMPLICIT_DEF for it just before
+# the loop backedge.
+
+# GCN: bb.1:
+# GCN: V_LSHLREV_B32_e32 2, [[val:%[0-9][0-9]*]].sub2
+# GCN-NOT: [[val]]:vreg_128 = IMPLICIT_DEF
+
+---
+name: _amdgpu_cs_main
+tracksRegLiveness: true
+body: |
+  bb.0:
+    successors: %bb.1
+
+    %3:sgpr_32 = S_MOV_B32 0
+    undef %19.sub1:vreg_128 = COPY undef %3
+    %4:sgpr_32 = S_MOV_B32 1
+    %5:sgpr_32 = S_MOV_B32 2
+    %11:sreg_32_xm0 = S_MOV_B32 255
+    undef %28.sub0:vreg_128 = COPY killed %3
+    %28.sub1:vreg_128 = COPY killed %4
+    %28.sub2:vreg_128 = COPY killed %11
+    %28.sub3:vreg_128 = COPY killed %5
+    %2:sreg_64 = S_MOV_B64 0
+    %34:sreg_32 = S_MOV_B32 7
+    %37:vreg_128 = COPY undef %42:vreg_128
+    %43:sreg_64 = COPY killed %2
+    %44:vreg_128 = COPY killed %37
+    %45:vreg_128 = COPY killed %28
+
+  bb.1:
+    successors: %bb.1, %bb.2
+
+    %29:vreg_128 = COPY killed %45
+    %36:vreg_128 = COPY killed %44
+    %0:sreg_64 = COPY killed %43
+    %39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec
+    %41:vgpr_32 = V_ADD_I32_e32 1152, %39, implicit-def dead $vcc, implicit $exec
+    $m0 = S_MOV_B32 -1
+    %12:vreg_64 = DS_READ2_B32 killed %41, 0, 1, 0, implicit $m0, implicit $exec
+    %13:vreg_64 = DS_READ2_B32 %39, -112, -111, 0, implicit $m0, implicit $exec
+    %14:vreg_64 = DS_READ2_B32 %39, 0, 1, 0, implicit $m0, implicit $exec
+    %40:vgpr_32 = V_ADD_I32_e32 1160, %39, implicit-def dead $vcc, implicit $exec
+    %15:vreg_64 = DS_READ2_B32 killed %40, 0, 1, 0, implicit $m0, implicit $exec
+    %16:vreg_64 = DS_READ2_B32 %39, -110, -109, 0, implicit $m0, implicit $exec
+    %17:vreg_64 = DS_READ2_B32 %39, 2, 3, 0, implicit $m0, implicit $exec
+    undef %35.sub1:vreg_128 = COPY undef %34
+    %31:vreg_128 = COPY killed %29
+    %31.sub1:vreg_128 = COPY %34
+    %38:vgpr_32 = V_ADD_I32_e32 1, %36.sub0, implicit-def dead $vcc, implicit $exec
+    %18:sreg_64 = V_CMP_LT_I32_e64 5, %38, implicit $exec
+    %1:sreg_64 = S_OR_B64 killed %18, killed %0, implicit-def $scc
+    %30:vreg_128 = COPY %31
+    %43:sreg_64 = COPY %1
+    %44:vreg_128 = COPY %35
+    %45:vreg_128 = COPY killed %30
+    $exec = S_ANDN2_B64_term $exec, %1
+    S_CBRANCH_EXECNZ %bb.1, implicit $exec
+    S_BRANCH %bb.2
+
+  bb.2:
+    $exec = S_OR_B64 $exec, killed %1, implicit-def $scc
+    %33:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    undef %32.sub0:vreg_128 = COPY killed %31.sub0
+    %32.sub2:vreg_128 = COPY %33
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %32:vreg_128
+    S_ENDPGM
+
+...