AMDGPU: Fix scalar_to_vector for v4i16/v4f16

[kzhuravl]

LGTM

[arsenm]

r335161

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

case AMDGPUISD::FMA_W_CHAIN: {
     SelectFMA_W_CHAIN(N);
     return;
   }
 
   case ISD::SCALAR_TO_VECTOR:
   case ISD::BUILD_VECTOR: {
     EVT VT = N->getValueType(0);
     unsigned NumVectorElts = VT.getVectorNumElements();
-
-    if (VT == MVT::v2i16 || VT == MVT::v2f16) {
-      if (Opc == ISD::BUILD_VECTOR) {
+    if (VT.getScalarSizeInBits() == 16) {
+      if (Opc == ISD::BUILD_VECTOR && NumVectorElts == 2) {
         uint32_t LHSVal, RHSVal;
         if (getConstantValue(N->getOperand(0), LHSVal) &&
             getConstantValue(N->getOperand(1), RHSVal)) {
           uint32_t K = LHSVal | (RHSVal << 16);
           CurDAG->SelectNodeTo(N, AMDGPU::S_MOV_B32, VT,
                                CurDAG->getTargetConstant(K, SDLoc(N), MVT::i32));
           return;
         }

lib/Target/AMDGPU/SIInstructions.td

 //   (COPY $src0)
 // >;
 
 // def : GCNPat <
 //   (v2i16 (scalar_to_vector i16:$src0)),
 //   (COPY $src0)
 // >;
 
+def : GCNPat <
+  (v4i16 (scalar_to_vector i16:$src0)),
+  (INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
+>;
+
+def : GCNPat <
+  (v4f16 (scalar_to_vector f16:$src0)),
+  (INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
+>;
+
 //===----------------------------------------------------------------------===//
 // Fract Patterns
 //===----------------------------------------------------------------------===//
 
 let SubtargetPredicate = isSI in {
 
 // V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is
 // used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient

test/CodeGen/AMDGPU/scalar_to_vector.ll

 define amdgpu_kernel void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind {
   %tmp1 = load float, float addrspace(1)* %in, align 4
   %bc = bitcast float %tmp1 to <2 x i16>
   %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8
   ret void
 }
 
+; GCN-LABEL: {{^}}scalar_to_vector_v4i16:
+; VI: v_lshlrev_b16_e32
+; VI: v_lshlrev_b16_e32
+; VI: v_or_b32_e32
+; VI: v_lshlrev_b32
+; VI: v_or_b32_sdwa
+; VI: v_or_b32_sdwa
+define amdgpu_kernel void @scalar_to_vector_v4i16() {
+bb:
+  %tmp = load <2 x i8>, <2 x i8> addrspace(1)* undef, align 1
+  %tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
+  store <8 x i8> %tmp2, <8 x i8> addrspace(1)* undef, align 8
+  ret void
+}
+
+; GCN-LABEL: {{^}}scalar_to_vector_v4f16:
+; VI: v_lshlrev_b16_e32
+; VI: v_lshlrev_b16_e32
+; VI: v_or_b32_e32
+; VI: v_lshlrev_b32
+; VI: v_or_b32_sdwa
+; VI: v_or_b32_sdwa
+define amdgpu_kernel void @scalar_to_vector_v4f16() {
+bb:
+  %load = load half, half addrspace(1)* undef, align 1
+  %tmp = bitcast half %load to <2 x i8>
+  %tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
+  store <8 x i8> %tmp2, <8 x i8> addrspace(1)* undef, align 8
+  ret void
+}
+
 ; Getting a SCALAR_TO_VECTOR seems to be tricky. These cases managed
 ; to produce one, but for some reason never made it to selection.
 
 
 ; define amdgpu_kernel void @scalar_to_vector_test2(<8 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
 ;   %tmp1 = load i32, i32 addrspace(1)* %in, align 4
 ;   %bc = bitcast i32 %tmp1 to <4 x i8>