[RISCV] Tail calls don't need to save return address

[sabuasal]

Summary

When expanding the PseudoTail in expandFunctionCall() we were using X6
to save the return address. Since this is a tail call the return
address is not needed, this patch replaces it with X0 to be ignored.

This matches the behaviour listed in the ISA V2.2 document page 110.
tail offset -----> jalr x0, x6, offset

GCC exhibits the same behavior.

[asb]

Looks good to me, thanks!

llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
 
   // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
   TmpInst = MCInstBuilder(RISCV::AUIPC)
                 .addReg(Ra)
                 .addOperand(MCOperand::createExpr(CallExpr));
   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
   support::endian::write(OS, Binary, support::little);
 
-  // Emit JALR Ra, Ra, 0
+  if (MI.getOpcode() == RISCV::PseudoTAIL)
+    // Emit JALR X0, X6, 0
+    TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
+  else
+    // Emit JALR X1, X1, 0
     TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
   support::endian::write(OS, Binary, support::little);
 }
 
 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());

llvm/trunk/test/MC/RISCV/tail-call.s

 # RUN: llvm-mc -triple riscv64 < %s -show-encoding \
 # RUN:   | FileCheck -check-prefix=FIXUP %s
 
 .long foo
 
 tail foo
 # RELOC: R_RISCV_CALL foo 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: foo, kind:
 tail bar
 # RELOC: R_RISCV_CALL bar 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: bar, kind:
 
 # Ensure that tail calls to functions whose names coincide with register names
 # work.
 
 tail zero
 # RELOC: R_RISCV_CALL zero 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: zero, kind:
 
 tail f1
 # RELOC: R_RISCV_CALL f1 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: f1, kind:
 
 tail ra
 # RELOC: R_RISCV_CALL ra 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: ra, kind: