[AMDGPU] findMaskOperands() - prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'

[msearles]

Summary

The use iterator, used within findMaskOperands(), can return anything which is not a def. isUse() requires a register, so check isReg() before calling isUse().

[rampitec]

LGTM

[msearles]

Added a test

[arsenm]

test/CodeGen/AMDGPU/si-lower-control-flow.mir

1

Nothing about this requires asserts?

[msearles]

Removed # REQUIRES: asserts in test

[msearles]

test/CodeGen/AMDGPU/si-lower-control-flow.mir

1

removed # REQUIRES: asserts

[arsenm]

LGTM

lib/Target/AMDGPU/SILowerControlFlow.cpp

void SILowerControlFlow::findMaskOperands(MachineInstr &MI, unsigned OpNo,
   // A copy with implcitly defined exec inserted earlier is an exclusion, it
   // does not really modify exec.
   for (auto I = Def->getIterator(); I != MI.getIterator(); ++I)
     if (I->modifiesRegister(AMDGPU::EXEC, TRI) &&
         !(I->isCopy() && I->getOperand(0).getReg() != AMDGPU::EXEC))
       return;
 
   for (const auto &SrcOp : Def->explicit_operands())
-    if (SrcOp.isUse() && (!SrcOp.isReg() ||
-        TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) ||
+    if (SrcOp.isReg() && SrcOp.isUse() &&
+        (TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) ||
         SrcOp.getReg() == AMDGPU::EXEC))
       Src.push_back(SrcOp);
 }
 
 // Search and combine pairs of equivalent instructions, like
 // S_AND_B64 x, (S_AND_B64 x, y) => S_AND_B64 x, y
 // S_OR_B64  x, (S_OR_B64  x, y) => S_OR_B64  x, y
 // One of the operands is exec mask.

test/CodeGen/AMDGPU/si-lower-control-flow.mir

+# REQUIRES: asserts
+# RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgizcl -run-pass=si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
+
+# Check that assert is not triggered
+# GCN-LABEL: name: si-lower-control-flow{{$}}
+# GCN-CHECK: S_LOAD_DWORD_IMM
+
+--- |
+
+  define amdgpu_kernel void @si-lower-control-flow() {
+    ret void
+  }
+
+...
+---
+name: si-lower-control-flow
+body: |
+  bb.0:
+    %0:sgpr_64 = COPY $sgpr4_sgpr5
+    %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0
+    %2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc
+    %3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc
+    S_ENDPGM
+...