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[AMDGPU] findMaskOperands() - prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'
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Authored by msearles on Jun 11 2018, 1:11 PM.

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rampitec
arsenm

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rG987f292c5606: [AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'
rL334459: [AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'

Summary

The use iterator, used within findMaskOperands(), can return anything which is not a def. isUse() requires a register, so check isReg() before calling isUse().

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Repository: rL LLVM

Event Timeline

msearles created this revision.Jun 11 2018, 1:11 PM

Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptJun 11 2018, 1:11 PM

LGTM

This revision is now accepted and ready to land.Jun 11 2018, 1:17 PM

Added a test

arsenm added inline comments.Jun 11 2018, 1:28 PM

test/CodeGen/AMDGPU/si-lower-control-flow.mir
1 ↗	(On Diff #150825)	Nothing about this requires asserts?

Removed # REQUIRES: asserts in test

msearles marked an inline comment as done.Jun 11 2018, 1:37 PM

msearles added inline comments.

test/CodeGen/AMDGPU/si-lower-control-flow.mir
1 ↗	(On Diff #150825)	removed # REQUIRES: asserts

LGTM

Closed by commit rL334459: [AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"' (authored by msearles). · Explain WhyJun 11 2018, 5:45 PM

This revision was automatically updated to reflect the committed changes.

msearles marked an inline comment as done.

Revision Contents

Path

Size

llvm/

trunk/

lib/

Target/

AMDGPU/

SILowerControlFlow.cpp

4 lines

test/

CodeGen/

AMDGPU/

si-lower-control-flow.mir

23 lines

Diff 150871

llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp

Show First 20 Lines • Show All 447 Lines • ▼ Show 20 Lines	void SILowerControlFlow::findMaskOperands(MachineInstr &MI, unsigned OpNo,
// A copy with implcitly defined exec inserted earlier is an exclusion, it		// A copy with implcitly defined exec inserted earlier is an exclusion, it
// does not really modify exec.		// does not really modify exec.
for (auto I = Def->getIterator(); I != MI.getIterator(); ++I)		for (auto I = Def->getIterator(); I != MI.getIterator(); ++I)
if (I->modifiesRegister(AMDGPU::EXEC, TRI) &&		if (I->modifiesRegister(AMDGPU::EXEC, TRI) &&
!(I->isCopy() && I->getOperand(0).getReg() != AMDGPU::EXEC))		!(I->isCopy() && I->getOperand(0).getReg() != AMDGPU::EXEC))
return;		return;

for (const auto &SrcOp : Def->explicit_operands())		for (const auto &SrcOp : Def->explicit_operands())
if (SrcOp.isUse() && (!SrcOp.isReg() \|\|		if (SrcOp.isReg() && SrcOp.isUse() &&
TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) \|\|		(TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) \|\|
SrcOp.getReg() == AMDGPU::EXEC))		SrcOp.getReg() == AMDGPU::EXEC))
Src.push_back(SrcOp);		Src.push_back(SrcOp);
}		}

// Search and combine pairs of equivalent instructions, like		// Search and combine pairs of equivalent instructions, like
// S_AND_B64 x, (S_AND_B64 x, y) => S_AND_B64 x, y		// S_AND_B64 x, (S_AND_B64 x, y) => S_AND_B64 x, y
// S_OR_B64 x, (S_OR_B64 x, y) => S_OR_B64 x, y		// S_OR_B64 x, (S_OR_B64 x, y) => S_OR_B64 x, y
// One of the operands is exec mask.		// One of the operands is exec mask.
▲ Show 20 Lines • Show All 91 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/si-lower-control-flow.mir

				# RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgizcl -run-pass=si-lower-control-flow -verify-machineinstrs %s -o - \| FileCheck -check-prefixes=GCN %s

				# Check that assert is not triggered
				# GCN-LABEL: name: si-lower-control-flow{{$}}
				# GCN-CHECK: S_LOAD_DWORD_IMM

				--- \|

				define amdgpu_kernel void @si-lower-control-flow() {
				ret void
				}

				...
				---
				name: si-lower-control-flow
				body: \|
				bb.0:
				%0:sgpr_64 = COPY $sgpr4_sgpr5
				%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0
				%2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc
				%3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc
				S_ENDPGM
				...