[llvm-exegesis] Cleaner design without mutable data.

[gchatelet]

Summary

Previous design was relying on the 'mutate' keyword and was quite confusing. This version separate mutable from immutable data and makes it clearer what changes and what doesn't.

[gchatelet]

Removed dead code and fixed documentation.

[courbet]

unit tests ?

tools/llvm-exegesis/lib/Latency.cpp

72

let's add a tiny comment there as this triggers my weirdness detector.

tools/llvm-exegesis/lib/MCInstrDescView.h

147

selects

[gchatelet]

Adding unit tests for latency and uops.

[gchatelet]

Rebasing.

[courbet]

tools/llvm-exegesis/lib/Latency.cpp

81

what about splitting the if in two subfunctions ?

tools/llvm-exegesis/lib/Uops.cpp

106

rm this

[gchatelet]

Removing commented function.

[courbet]

unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

66 ↗

(On Diff #151127)

ASSERT_THAT, since you're taking the front below.

87 ↗

(On Diff #151127)

ditto

115 ↗

(On Diff #151127)

ditto

125 ↗

(On Diff #151127)

should you be testing that ? this is randomized.

157 ↗

(On Diff #151127)

ditto

174 ↗

(On Diff #151127)

ditto

192 ↗

(On Diff #151127)

ditto

193 ↗

(On Diff #151127)

Same here: any ordering would be OK.

228 ↗

(On Diff #151127)

ditto

232 ↗

(On Diff #151127)

i don;t think you shoul dbe testing the exact assignment

[gchatelet]

Made tests less britle.

tools/llvm-exegesis/lib/Latency.cpp

LatencyBenchmarkRunner::createConfigurations(RegisterAliasingTrackerCache &RATC,
   if (IsInfeasible(ThisInstruction, Error))
     return llvm::make_error<llvm::StringError>(
         llvm::Twine("Infeasible : ").concat(Error),
         llvm::inconvertibleErrorCode());
 
   BenchmarkConfiguration Conf;
   const AliasingConfigurations SelfAliasing(ThisInstruction, ThisInstruction);
   if (!SelfAliasing.empty()) {
+    InstructionInstance II(ThisInstruction);
     if (!SelfAliasing.hasImplicitAliasing()) {
       Conf.Info = "explicit self cycles, selecting one aliasing Conf.";
-      setRandomAliasing(SelfAliasing);
+      setRandomAliasing(SelfAliasing, II, II);
     } else {
       Conf.Info = "implicit Self cycles, picking random values.";
     }
-    Conf.Snippet = {randomizeUnsetVariablesAndBuild(ThisInstruction)};
+    Conf.Snippet = {II.randomizeUnsetVariablesAndBuild()};
     return std::vector<BenchmarkConfiguration>{Conf};
   }
 
   // Let's try to create a dependency through another opcode.
   std::vector<unsigned> Opcodes;
   Opcodes.resize(MCInstrInfo.getNumOpcodes());
   std::iota(Opcodes.begin(), Opcodes.end(), 0U);
   std::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
   for (const unsigned OtherOpcode : Opcodes) {
-    clearVariableAssignments(ThisInstruction);
+    InstructionInstance ThisII(ThisInstruction);
     if (OtherOpcode == Opcode)
       continue;
     const Instruction OtherInstruction(MCInstrInfo.get(OtherOpcode), RATC);
     if (IsInfeasible(OtherInstruction, Error))
       continue;
     const AliasingConfigurations Forward(ThisInstruction, OtherInstruction);
     const AliasingConfigurations Back(OtherInstruction, ThisInstruction);
     if (Forward.empty() || Back.empty())
       continue;
-    setRandomAliasing(Forward);
-    setRandomAliasing(Back);
+    InstructionInstance OtherII(OtherInstruction);
+    setRandomAliasing(Forward, ThisII, OtherII);
+    setRandomAliasing(Back, OtherII, ThisII);
     Conf.Info = llvm::Twine("creating cycle through ")
                     .concat(MCInstrInfo.getName(OtherOpcode))
                     .concat(".")
                     .str();
-    Conf.Snippet.push_back(randomizeUnsetVariablesAndBuild(ThisInstruction));
-    Conf.Snippet.push_back(randomizeUnsetVariablesAndBuild(OtherInstruction));
+    Conf.Snippet.push_back(ThisII.randomizeUnsetVariablesAndBuild());
+    Conf.Snippet.push_back(OtherII.randomizeUnsetVariablesAndBuild());
     return std::vector<BenchmarkConfiguration>{Conf};
   }
 
   return llvm::make_error<llvm::StringError>(
       "Infeasible : Didn't find any scheme to make the instruction serial",
       llvm::inconvertibleErrorCode());
 }
 

tools/llvm-exegesis/lib/MCInstrDescView.h

 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 
 namespace exegesis {
 
 struct Operand; // forward declaration.
 
-// A variable represents the value of an Operand or a set of Operands if they ar
-// tied together.
+// A variable represents the value associated to an Operand or a set of Operands
+// if they are tied together.
 struct Variable {
   llvm::SmallVector<const Operand *, 2> TiedOperands;
   llvm::MCOperand AssignedValue;
+  // The index of this Variable in Instruction.Variables and its associated
+  // Value in InstructionInstance.VariableValues.
+  unsigned Index = -1;
 };
 
 // MCOperandInfo can only represents Explicit operands. This object gives a
 // uniform view of Implicit and Explicit Operands.
 //
 // - Index: can be used to refer to MCInstrDesc::operands for Explicit operands.
 // - Tracker: is set for Register Operands and is used to keep track of possible
 // registers and the registers reachable from them (aliasing registers).
 // - Info: a shortcut for MCInstrDesc::operands()[Index].
-// - TiedTo: a pointer to the Operand holding the value or nullptr.
+// - TiedToIndex: the index of the Operand holding the value or -1.
 // - ImplicitReg: a pointer to the register value when Operand is Implicit,
 // nullptr otherwise.
-// - Variable: The value associated with this Operand. It is only set for
-// explicit operands that are not TiedTo.
+// - VariableIndex: the index of the Variable holding the value for this Operand
+// or -1 if this operand is implicit.
 struct Operand {
-  uint8_t Index = 0;
+  unsigned Index = 0;
   bool IsDef = false;
   bool IsExplicit = false;
   const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
   const llvm::MCOperandInfo *Info = nullptr;        // Set for Explicit Op.
-  const Operand *TiedTo = nullptr;                  // Set for Reg/Explicit Op.
+  int TiedToIndex = -1;                             // Set for Reg/Explicit Op.
   const llvm::MCPhysReg *ImplicitReg = nullptr;     // Set for Implicit Op.
-  mutable llvm::Optional<Variable> Var;             // Set for Explicit Op.
+  int VariableIndex = -1;                           // Set for Reg/Explicit Op.
 };
 
 // A view over an MCInstrDesc offering a convenient interface to compute
-// Register aliasing and assign values to Operands.
+// Register aliasing.
 struct Instruction {
   Instruction(const llvm::MCInstrDesc &MCInstrDesc,
               RegisterAliasingTrackerCache &ATC);
 
   const llvm::MCInstrDesc &Description;
   llvm::SmallVector<Operand, 8> Operands;
-  llvm::SmallVector<Variable *, 8> Variables;
+  llvm::SmallVector<Variable, 4> Variables;
   llvm::BitVector DefRegisters; // The union of the aliased def registers.
   llvm::BitVector UseRegisters; // The union of the aliased use registers.
 };
 
+// An instance of an Instruction holding values for each of its Variables.
+struct InstructionInstance {
+  InstructionInstance(const Instruction &Instr);
+
+  llvm::MCOperand &getValueFor(const Variable &Var);
+  llvm::MCOperand &getValueFor(const Operand &Op);
+
+  // Assigns a Random Value to all Variables that are still Invalid and returns
+  // the instance as an llvm::MCInst.
+  llvm::MCInst randomizeUnsetVariablesAndBuild();
+
+  const Instruction &Instr;
+  llvm::SmallVector<llvm::MCOperand, 4> VariableValues;
+};
+
 // Represents the assignment of a Register to an Operand.
 struct RegisterOperandAssignment {
   RegisterOperandAssignment(const Operand *Operand, llvm::MCPhysReg Reg)
       : Op(Operand), Reg(Reg) {}
 
   const Operand *Op; // Pointer to an Explicit Register Operand.
   llvm::MCPhysReg Reg;
 

 // FIXME: Move random number generation into an object and make it seedable for
 // unit tests.
 std::mt19937 &randomGenerator();
 
 // Picks a random bit among the bits set in Vector and returns its index.
 // Precondition: Vector must have at least one bit set.
 size_t randomBit(const llvm::BitVector &Vector);
 
 // Picks a random configuration, then select a random def and a random use from
-// it and set the target Variables to the selected values.
-// FIXME: This function mutates some nested variables in a const object, please
-// fix ASAP.
-void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations);
-
-// Set all Instruction's Variables AssignedValue to Invalid.
-void clearVariableAssignments(const Instruction &Instruction);
-
-// Assigns a Random Value to all Instruction's Variables that are still Invalid.
-llvm::MCInst randomizeUnsetVariablesAndBuild(const Instruction &Instruction);
+// it and finally set the selected values in the provided InstructionInstances.
+void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
+                       InstructionInstance &DefII, InstructionInstance &UseII);
 
 // Writes MCInst to OS.
 // This is not assembly but the internal LLVM's name for instructions and
 // registers.
 void DumpMCInst(const llvm::MCRegisterInfo &MCRegisterInfo,
                 const llvm::MCInstrInfo &MCInstrInfo,
                 const llvm::MCInst &MCInst, llvm::raw_ostream &OS);
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H

tools/llvm-exegesis/lib/MCInstrDescView.cpp

 #include <iterator>
 #include <map>
 #include <tuple>
 
 #include "llvm/ADT/STLExtras.h"
 
 namespace exegesis {
 
-static void tie(const Operand *FromOperand, llvm::Optional<Variable> &Var) {
-  if (!Var)
-    Var.emplace();
-  Var->TiedOperands.push_back(FromOperand);
-}
-
 Instruction::Instruction(const llvm::MCInstrDesc &MCInstrDesc,
                          RegisterAliasingTrackerCache &RATC)
     : Description(MCInstrDesc) {
   unsigned OpIndex = 0;
   for (; OpIndex < MCInstrDesc.getNumOperands(); ++OpIndex) {
     const auto &OpInfo = MCInstrDesc.opInfo_begin()[OpIndex];
     Operand Operand;
     Operand.Index = OpIndex;
     Operand.IsDef = (OpIndex < MCInstrDesc.getNumDefs());
     Operand.IsExplicit = true;
     // TODO(gchatelet): Handle isLookupPtrRegClass.
     if (OpInfo.RegClass >= 0)
       Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass);
+    Operand.TiedToIndex =
+        MCInstrDesc.getOperandConstraint(OpIndex, llvm::MCOI::TIED_TO);
     Operand.Info = &OpInfo;
     Operands.push_back(Operand);
   }
   for (const llvm::MCPhysReg *MCPhysReg = MCInstrDesc.getImplicitDefs();
        MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) {
     Operand Operand;
     Operand.Index = OpIndex;
     Operand.IsDef = true;
     Operand.IsExplicit = false;
     Operand.Tracker = &RATC.getRegister(*MCPhysReg);
     Operand.ImplicitReg = MCPhysReg;
     Operands.push_back(Operand);
   }
   for (const llvm::MCPhysReg *MCPhysReg = MCInstrDesc.getImplicitUses();
        MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) {
     Operand Operand;
     Operand.Index = OpIndex;
     Operand.IsDef = false;
     Operand.IsExplicit = false;
     Operand.Tracker = &RATC.getRegister(*MCPhysReg);
     Operand.ImplicitReg = MCPhysReg;
     Operands.push_back(Operand);
   }
-  // Set TiedTo for operands.
-  for (auto &Op : Operands) {
-    if (Op.IsExplicit) {
-      const int TiedTo =
-          MCInstrDesc.getOperandConstraint(Op.Index, llvm::MCOI::TIED_TO);
-      if (TiedTo >= 0) {
-        Op.TiedTo = &Operands[TiedTo];
-        tie(&Op, Operands[TiedTo].Var);
-      } else {
-        tie(&Op, Op.Var);
-      }
-    }
-  }
-  for (auto &Op : Operands) {
-    if (Op.Var) {
-      Variables.push_back(&*Op.Var);
-    }
-  }
+  // Assigning Variables to non tied explicit operands.
+  Variables.reserve(Operands.size()); // Variables.size() <= Operands.size()
+  for (auto &Op : Operands)
+    if (Op.IsExplicit && Op.TiedToIndex < 0) {
+      const size_t VariableIndex = Variables.size();
+      Op.VariableIndex = VariableIndex;
+      Variables.emplace_back();
+      Variables.back().Index = VariableIndex;
+    }
+  // Assigning Variables to tied operands.
+  for (auto &Op : Operands)
+    if (Op.TiedToIndex >= 0)
+      Op.VariableIndex = Operands[Op.TiedToIndex].VariableIndex;
+  // Assigning Operands to Variables.
+  for (auto &Op : Operands)
+    if (Op.VariableIndex >= 0)
+      Variables[Op.VariableIndex].TiedOperands.push_back(&Op);
   // Processing Aliasing.
   DefRegisters = RATC.emptyRegisters();
   UseRegisters = RATC.emptyRegisters();
   for (const auto &Op : Operands) {
     if (Op.Tracker) {
       auto &Registers = Op.IsDef ? DefRegisters : UseRegisters;
       Registers |= Op.Tracker->aliasedBits();
     }
   }
 }
 
+InstructionInstance::InstructionInstance(const Instruction &Instr)
+    : Instr(Instr), VariableValues(Instr.Variables.size()) {}
+
+llvm::MCOperand &InstructionInstance::getValueFor(const Variable &Var) {
+  return VariableValues[Var.Index];
+}
+
+llvm::MCOperand &InstructionInstance::getValueFor(const Operand &Op) {
+  assert(Op.VariableIndex >= 0);
+  return getValueFor(Instr.Variables[Op.VariableIndex]);
+}
+
+// forward declaration.
+static void randomize(const Variable &Var, llvm::MCOperand &AssignedValue);
+
+llvm::MCInst InstructionInstance::randomizeUnsetVariablesAndBuild() {
+  for (const Variable &Var : Instr.Variables) {
+    llvm::MCOperand &AssignedValue = getValueFor(Var);
+    if (!AssignedValue.isValid())
+      randomize(Var, AssignedValue);
+  }
+  llvm::MCInst Result;
+  Result.setOpcode(Instr.Description.Opcode);
+  for (const auto &Op : Instr.Operands)
+    if (Op.IsExplicit)
+      Result.addOperand(getValueFor(Op));
+  return Result;
+}
+
 bool RegisterOperandAssignment::
 operator==(const RegisterOperandAssignment &Other) const {
   return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg);
 }
 
 bool AliasingRegisterOperands::
 operator==(const AliasingRegisterOperands &Other) const {
   return std::tie(Defs, Uses) == std::tie(Other.Defs, Other.Uses);
static size_t randomIndex(size_t Size) {
   return Distribution(randomGenerator());
 }
 
 template <typename C>
 static auto randomElement(const C &Container) -> decltype(Container[0]) {
   return Container[randomIndex(Container.size())];
 }
 
-static void randomize(Variable &Var) {
+static void randomize(const Variable &Var, llvm::MCOperand &AssignedValue) {
   assert(!Var.TiedOperands.empty());
   assert(Var.TiedOperands.front() != nullptr);
   const Operand &Op = *Var.TiedOperands.front();
   assert(Op.Info != nullptr);
   const auto &OpInfo = *Op.Info;
   switch (OpInfo.OperandType) {
   case llvm::MCOI::OperandType::OPERAND_IMMEDIATE:
     // FIXME: explore immediate values too.
-    Var.AssignedValue = llvm::MCOperand::createImm(1);
+    AssignedValue = llvm::MCOperand::createImm(1);
     break;
   case llvm::MCOI::OperandType::OPERAND_REGISTER: {
     assert(Op.Tracker);
     const auto &Registers = Op.Tracker->sourceBits();
-    Var.AssignedValue = llvm::MCOperand::createReg(randomBit(Registers));
+    AssignedValue = llvm::MCOperand::createReg(randomBit(Registers));
     break;
   }
   default:
     break;
   }
 }
 
-static void setRegisterOperandValue(const RegisterOperandAssignment &ROV) {
-  const Operand *Op = ROV.Op->TiedTo ? ROV.Op->TiedTo : ROV.Op;
-  assert(Op->Var);
-  auto &AssignedValue = Op->Var->AssignedValue;
+static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
+                                    InstructionInstance &II) {
+  assert(ROV.Op);
+  auto &AssignedValue = II.getValueFor(*ROV.Op);
   if (AssignedValue.isValid()) {
     assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
     return;
   }
-  Op->Var->AssignedValue = llvm::MCOperand::createReg(ROV.Reg);
+  AssignedValue = llvm::MCOperand::createReg(ROV.Reg);
 }
 
 size_t randomBit(const llvm::BitVector &Vector) {
   assert(Vector.any());
   auto Itr = Vector.set_bits_begin();
   for (size_t I = randomIndex(Vector.count()); I != 0; --I)
     ++Itr;
   return *Itr;
 }
 
-void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations) {
+void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
+                       InstructionInstance &DefII, InstructionInstance &UseII) {
   assert(!AliasingConfigurations.empty());
   assert(!AliasingConfigurations.hasImplicitAliasing());
   const auto &RandomConf = randomElement(AliasingConfigurations.Configurations);
-  setRegisterOperandValue(randomElement(RandomConf.Defs));
-  setRegisterOperandValue(randomElement(RandomConf.Uses));
-}
-
-void randomizeUnsetVariable(const Instruction &Instruction) {
-  for (auto *Var : Instruction.Variables)
-    if (!Var->AssignedValue.isValid())
-      randomize(*Var);
-}
-
-void clearVariableAssignments(const Instruction &Instruction) {
-  for (auto *Var : Instruction.Variables)
-    Var->AssignedValue = llvm::MCOperand();
-}
-
-llvm::MCInst build(const Instruction &Instruction) {
-  llvm::MCInst Result;
-  Result.setOpcode(Instruction.Description.Opcode);
-  for (const auto &Op : Instruction.Operands) {
-    if (Op.IsExplicit) {
-      auto &Var = Op.TiedTo ? Op.TiedTo->Var : Op.Var;
-      assert(Var);
-      Result.addOperand(Var->AssignedValue);
-    }
-  }
-  return Result;
-}
-
-llvm::MCInst randomizeUnsetVariablesAndBuild(const Instruction &Instruction) {
-  randomizeUnsetVariable(Instruction);
-  return build(Instruction);
+  setRegisterOperandValue(randomElement(RandomConf.Defs), DefII);
+  setRegisterOperandValue(randomElement(RandomConf.Uses), UseII);
 }
 
 void DumpMCOperand(const llvm::MCRegisterInfo &MCRegisterInfo,
                    const llvm::MCOperand &Op, llvm::raw_ostream &OS) {
   if (!Op.isValid())
     OS << "Invalid";
   else if (Op.isReg())
     OS << MCRegisterInfo.getName(Op.getReg());

tools/llvm-exegesis/lib/Uops.cpp

static bool isInfeasible(const Instruction &Instruction, std::string &Error) {
   if (llvm::any_of(MCInstrDesc.operands(), hasUnknownOperand)) {
     Error = "has unknown operands";
     return true;
   }
   if (llvm::any_of(MCInstrDesc.operands(), hasMemoryOperand)) {
     Error = "has memory operands";
     return true;
   }
   return false;
 }
 
 // Returns whether this Variable ties Use and Def operands together.
-static bool hasTiedOperands(const Variable *Var) {
+static bool hasTiedOperands(const Variable &Var) {
   bool HasUse = false;
   bool HasDef = false;
-  for (const Operand *Op : Var->TiedOperands) {
+  for (const Operand *Op : Var.TiedOperands) {
     if (Op->IsDef)
       HasDef = true;
     else
       HasUse = true;
   }
   return HasUse && HasDef;
 }
 
-static llvm::SmallVector<Variable *, 8>
+static llvm::SmallVector<const Variable *, 8>
 getTiedVariables(const Instruction &Instruction) {
-  llvm::SmallVector<Variable *, 8> Result;
-  for (auto *Var : Instruction.Variables)
+  llvm::SmallVector<const Variable *, 8> Result;
+  for (const auto &Var : Instruction.Variables)
     if (hasTiedOperands(Var))
-      Result.push_back(Var);
+      Result.push_back(&Var);
   return Result;
 }
 
 static void remove(llvm::BitVector &a, const llvm::BitVector &b) {
   assert(a.size() == b.size());
   for (auto I : b.set_bits())
     a.reset(I);
 }
UopsBenchmarkRunner::createConfigurations(RegisterAliasingTrackerCache &RATC,
   if (isInfeasible(Instruction, Error))
     return llvm::make_error<llvm::StringError>(
         llvm::Twine("Infeasible : ").concat(Error),
         llvm::inconvertibleErrorCode());
 
   BenchmarkConfiguration Conf;
   const AliasingConfigurations SelfAliasing(Instruction, Instruction);
   if (SelfAliasing.empty()) {
+    InstructionInstance II(Instruction);
     Conf.Info = "instruction is parallel, repeating a random one.";
-    Conf.Snippet = {randomizeUnsetVariablesAndBuild(Instruction)};
+    Conf.Snippet = {II.randomizeUnsetVariablesAndBuild()};
     return std::vector<BenchmarkConfiguration>{Conf};
   }
   if (SelfAliasing.hasImplicitAliasing()) {
+    InstructionInstance II(Instruction);
     Conf.Info = "instruction is serial, repeating a random one.";
-    Conf.Snippet = {randomizeUnsetVariablesAndBuild(Instruction)};
+    Conf.Snippet = {II.randomizeUnsetVariablesAndBuild()};
     return std::vector<BenchmarkConfiguration>{Conf};
   }
   const auto TiedVariables = getTiedVariables(Instruction);
   if (!TiedVariables.empty()) {
     if (TiedVariables.size() > 1)
       return llvm::make_error<llvm::StringError>(
           "Infeasible : don't know how to handle several tied variables",
           llvm::inconvertibleErrorCode());
     Conf.Info = "instruction has tied variables using static renaming.";
-    Variable *Var = TiedVariables.front();
+    const Variable *Var = TiedVariables.front();
     assert(Var);
     assert(!Var->TiedOperands.empty());
     const Operand &Operand = *Var->TiedOperands.front();
     assert(Operand.Tracker);
     for (const llvm::MCPhysReg Reg : Operand.Tracker->sourceBits().set_bits()) {
-      clearVariableAssignments(Instruction);
-      Var->AssignedValue = llvm::MCOperand::createReg(Reg);
-      Conf.Snippet.push_back(randomizeUnsetVariablesAndBuild(Instruction));
+      InstructionInstance II(Instruction);
+      II.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
+      Conf.Snippet.push_back(II.randomizeUnsetVariablesAndBuild());
     }
     return std::vector<BenchmarkConfiguration>{Conf};
   }
+  InstructionInstance II(Instruction);
   // No tied variables, we pick random values for defs.
   llvm::BitVector Defs(MCRegisterInfo.getNumRegs());
   for (const auto &Op : Instruction.Operands) {
     if (Op.Tracker && Op.IsExplicit && Op.IsDef) {
-      assert(Op.Var);
       auto PossibleRegisters = Op.Tracker->sourceBits();
       remove(PossibleRegisters, RATC.reservedRegisters());
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
       Defs.set(RandomReg);
-      Op.Var->AssignedValue = llvm::MCOperand::createReg(RandomReg);
+      II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
   // And pick random use values that are not reserved and don't alias with defs.
   const auto DefAliases = getAliasedBits(MCRegisterInfo, Defs);
   for (const auto &Op : Instruction.Operands) {
     if (Op.Tracker && Op.IsExplicit && !Op.IsDef) {
-      assert(Op.Var);
       auto PossibleRegisters = Op.Tracker->sourceBits();
       remove(PossibleRegisters, RATC.reservedRegisters());
       remove(PossibleRegisters, DefAliases);
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
-      Op.Var->AssignedValue = llvm::MCOperand::createReg(RandomReg);
+      II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
   Conf.Info =
       "instruction has no tied variables picking Uses different from defs";
-  Conf.Snippet = {randomizeUnsetVariablesAndBuild(Instruction)};
+  Conf.Snippet = {II.randomizeUnsetVariablesAndBuild()};
   return std::vector<BenchmarkConfiguration>{Conf};
 }
 
 std::vector<BenchmarkMeasure>
 UopsBenchmarkRunner::runMeasurements(const ExecutableFunction &Function,
                                      const unsigned NumRepetitions) const {
   const auto &SchedModel = State.getSubtargetInfo().getSchedModel();