[IR][PatternMatch] m_APInt(): allow undef elements.

[lebedev.ri]

Summary

Allows to match more splatted vectors with integer constants,
with some elements being undef.
This deficiency was noticed during D47980.

This does not propagate undef elements, that would require
returning not the splatted APInt, but the vector itself,
which would require major changes on every callsite.

Later, i suppose some deduplication with api_pred_ty may be wanted.

Thoughts?

[lebedev.ri]

Rebased ontop of more tests, NFC.

[lebedev.ri]

Ping.
Or is it intentional for m_APInt not to do this?

[spatel]

In D47983#1134797, @lebedev.ri wrote:

Ping.
Or is it intentional for m_APInt not to do this?

No, it's not intentional to bail on undef when matching. Until recently, all of the constant matchers failed with undef elements in vectors. I enhanced most of those matchers, but missed this one (and apfloat_match?).

I also made a comment in one of those patches about being careful about changing the binding code, but I was probably confusing api_pred_ty with this. That does need to be careful AFAICT because callers may capture and use a vector with undefs when they didn't mean to.

Sorry for the delay - LGTM.

include/llvm/IR/PatternMatch.h

170

typo - 'Different'

[lebedev.ri]

In D47983#1135404, @spatel wrote:

In D47983#1134797, @lebedev.ri wrote:

Ping.
Or is it intentional for m_APInt not to do this?

No, it's not intentional to bail on undef when matching.
Until recently, all of the constant matchers failed with
undef elements in vectors. I enhanced most of those matchers,
but missed this one (and apfloat_match?).

Aha, great!

I also made a comment in one of those patches about being careful
about changing the binding code, but I was probably confusing
api_pred_ty with this. That does need to be careful AFAICT because
callers may capture and use a vector with undefs when they didn't mean to.

Sorry for the delay - LGTM.

No worries, thank you for the review!

[spatel]

On 2nd thought, I confused myself. :)
This patch is potentially dangerous - although it's hard to find cases where that danger propagates.
As with the earlier undef matcher changes, we have to audit the users to make sure they are not incorrectly using the matcher to propagate a value with undefs where it's not safe.

Example:

define <3 x i8> @f(<3 x i8> %x) {
  %x1 = or <3 x i8> %x, <i8 8, i8 8, i8 8>
  %r = urem <3 x i8> <i8 7, i8 undef, i8 7>, %x1
  ret <3 x i8> %r
}

InstSimplify can't return <i8 7, i8 undef, i8 7> here because the return value of the middle element of that vector is not unbounded.

[RKSimon]

Would it be better to implement m_APInt_or_Undef and m_APFloat_or_Undef - explaining that the undef is only for vectors (and naturally must still contain at least one APInt).

Get that in with a couple of combines updated to use it (with thorough testing), We can then gradually audit the remaining cases.

[lebedev.ri]

In D47983#1135568, @RKSimon wrote:

Would it be better to implement m_APInt_or_Undef and m_APFloat_or_Undef - explaining that the undef is only for vectors (and naturally must still contain at least one APInt).

Get that in with a couple of combines updated to use it (with thorough testing), We can then gradually audit the remaining cases.

Yes. That is the road i was planning on taking.
It is unfeasible to do this in one (more or less) go.

include/llvm/IR/PatternMatch.h

struct apint_match {
   apint_match(const APInt *&R) : Res(R) {}
 
   template <typename ITy> bool match(ITy *V) {
     if (auto *CI = dyn_cast<ConstantInt>(V)) {
       Res = &CI->getValue();
       return true;
     }
     if (V->getType()->isVectorTy())
-      if (const auto *C = dyn_cast<Constant>(V))
+      if (const auto *C = dyn_cast<Constant>(V)) {
         if (auto *CI = dyn_cast_or_null<ConstantInt>(C->getSplatValue())) {
           Res = &CI->getValue();
           return true;
         }
+
+        // Non-splat vector constant. Find first non-undef element, and then
+        // check the rest of the elements - they should either be undef,
+        // or they should match the first non-undef element.
+        unsigned NumElts = V->getType()->getVectorNumElements();
+        assert(NumElts != 0 && "Constant vector with no elements?");
+        const APInt *FirstNonUndefElt = nullptr;
+        for (unsigned i = 0; i != NumElts; ++i) {
+          Constant *Elt = C->getAggregateElement(i);
+          if (!Elt)
+            return false;
+          if (isa<UndefValue>(Elt))
+            continue;
+          auto *CI = dyn_cast<ConstantInt>(Elt);
+          if (!CI)
+            return false;
+          if (!FirstNonUndefElt) // This is the first non-undef element.
+            FirstNonUndefElt = &CI->getValue();
+          else if (*FirstNonUndefElt != CI->getValue()) // (still non-undef)
+            return false; // Diferent from the first non-undef element.
+        }
+        if (FirstNonUndefElt) {
+          // There were non-undef elements, and they all matched.
+          Res = FirstNonUndefElt;
+          return true;
+        }
+      }
+
     return false;
   }
 };
 // Either constexpr if or renaming ConstantFP::getValueAPF to
 // ConstantFP::getValue is needed to do it via single template
 // function for both apint/apfloat.
 struct apfloat_match {
   const APFloat *&Res;
if (V->getType()->isVectorTy())
           return true;
         }
     return false;
   }
 };
 
 /// Match a ConstantInt or splatted ConstantVector, binding the
 /// specified pointer to the contained APInt.
+/// For vector constants, undefined elements are ignored.
 inline apint_match m_APInt(const APInt *&Res) { return Res; }
 
 /// Match a ConstantFP or splatted ConstantVector, binding the
 /// specified pointer to the contained APFloat.
 inline apfloat_match m_APFloat(const APFloat *&Res) { return Res; }
 
 template <int64_t Val> struct constantint_match {
   template <typename ITy> bool match(ITy *V) {

test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll

 ;
   %tmp0 = ashr <2 x i32> %x, <i32 5, i32 5>
   %ret = shl <2 x i32> %tmp0, <i32 5, i32 5>
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @positive_sameconst_vec_undef0(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_sameconst_vec_undef0(
-; CHECK-NEXT:    [[TMP0:%.*]] = ashr <3 x i32> [[X:%.*]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 5, i32 5>
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and <3 x i32> [[X:%.*]], <i32 -32, i32 -32, i32 -32>
+; CHECK-NEXT:    ret <3 x i32> [[TMP1]]
 ;
   %tmp0 = ashr <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 5, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_sameconst_vec_undef1(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_sameconst_vec_undef1(
-; CHECK-NEXT:    [[TMP0:%.*]] = ashr <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and <3 x i32> [[X:%.*]], <i32 -32, i32 -32, i32 -32>
+; CHECK-NEXT:    ret <3 x i32> [[TMP1]]
 ;
   %tmp0 = ashr <3 x i32> %x, <i32 5, i32 5, i32 5>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_sameconst_vec_undef2(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_sameconst_vec_undef2(
-; CHECK-NEXT:    [[RET:%.*]] = and <3 x i32> [[X:%.*]], <i32 -32, i32 undef, i32 -32>
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and <3 x i32> [[X:%.*]], <i32 -32, i32 -32, i32 -32>
+; CHECK-NEXT:    ret <3 x i32> [[TMP1]]
 ;
   %tmp0 = ashr <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <2 x i32> @positive_biggerashr_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerashr_vec(
 ; CHECK-NEXT:    [[TMP0:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 10, i32 10>
 ; CHECK-NEXT:    [[RET:%.*]] = shl nsw <2 x i32> [[TMP0]], <i32 5, i32 5>
 ; CHECK-NEXT:    ret <2 x i32> [[RET]]
 ;
   %tmp0 = ashr <2 x i32> %x, <i32 10, i32 10>
   %ret = shl <2 x i32> %tmp0, <i32 5, i32 5>
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerashr_vec_undef0(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerashr_vec_undef0(
 ; CHECK-NEXT:    [[TMP0:%.*]] = ashr <3 x i32> [[X:%.*]], <i32 10, i32 undef, i32 10>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = shl nsw <3 x i32> [[TMP0]], <i32 5, i32 5, i32 5>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = ashr <3 x i32> %x, <i32 10, i32 undef, i32 10>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 5, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerashr_vec_undef1(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerashr_vec_undef1(
 ; CHECK-NEXT:    [[TMP0:%.*]] = ashr <3 x i32> [[X:%.*]], <i32 10, i32 10, i32 10>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = shl nsw <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = ashr <3 x i32> %x, <i32 10, i32 10, i32 10>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerashr_vec_undef2(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerashr_vec_undef2(
 ; CHECK-NEXT:    [[TMP0:%.*]] = ashr <3 x i32> [[X:%.*]], <i32 10, i32 undef, i32 10>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = shl nsw <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = ashr <3 x i32> %x, <i32 10, i32 undef, i32 10>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <2 x i32> @positive_biggershl_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @positive_biggershl_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 5, i32 5>
 ; CHECK-NEXT:    [[RET:%.*]] = shl <2 x i32> [[TMP1]], <i32 10, i32 10>
 ; CHECK-NEXT:    ret <2 x i32> [[RET]]
 ;
   %tmp0 = ashr <2 x i32> %x, <i32 5, i32 5>
   %ret = shl <2 x i32> %tmp0, <i32 10, i32 10>
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @positive_biggershl_vec_undef0(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggershl_vec_undef0(
-; CHECK-NEXT:    [[TMP0:%.*]] = ashr <3 x i32> [[X:%.*]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 10, i32 10, i32 10>
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 5, i32 undef, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP1]], <i32 10, i32 10, i32 10>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = ashr <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = shl <3 x i32> %tmp0, <i32 10, i32 10, i32 10>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggershl_vec_undef1(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggershl_vec_undef1(
-; CHECK-NEXT:    [[TMP0:%.*]] = ashr <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 10, i32 undef, i32 10>
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP1]], <i32 10, i32 undef, i32 10>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = ashr <3 x i32> %x, <i32 5, i32 5, i32 5>
   %ret = shl <3 x i32> %tmp0, <i32 10, i32 undef, i32 10>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggershl_vec_undef2(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggershl_vec_undef2(
-; CHECK-NEXT:    [[TMP0:%.*]] = ashr <3 x i32> [[X:%.*]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 10, i32 undef, i32 10>
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 5, i32 undef, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP1]], <i32 10, i32 undef, i32 10>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = ashr <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = shl <3 x i32> %tmp0, <i32 10, i32 undef, i32 10>
   ret <3 x i32> %ret
 }
 
 ; ============================================================================ ;

test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll

 ;
   %tmp0 = lshr <2 x i32> %x, <i32 5, i32 5>
   %ret = shl <2 x i32> %tmp0, <i32 5, i32 5>
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @positive_sameconst_vec_undef0(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_sameconst_vec_undef0(
-; CHECK-NEXT:    [[TMP0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 5, i32 5>
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[TMP0:%.*]] = and <3 x i32> [[X:%.*]], <i32 -32, i32 -32, i32 -32>
+; CHECK-NEXT:    ret <3 x i32> [[TMP0]]
 ;
   %tmp0 = lshr <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 5, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_sameconst_vec_undef1(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_sameconst_vec_undef1(
-; CHECK-NEXT:    [[TMP0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[TMP0:%.*]] = and <3 x i32> [[X:%.*]], <i32 -32, i32 -32, i32 -32>
+; CHECK-NEXT:    ret <3 x i32> [[TMP0]]
 ;
   %tmp0 = lshr <3 x i32> %x, <i32 5, i32 5, i32 5>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_sameconst_vec_undef2(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_sameconst_vec_undef2(
-; CHECK-NEXT:    [[RET:%.*]] = and <3 x i32> [[X:%.*]], <i32 -32, i32 undef, i32 -32>
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[TMP0:%.*]] = and <3 x i32> [[X:%.*]], <i32 -32, i32 -32, i32 -32>
+; CHECK-NEXT:    ret <3 x i32> [[TMP0]]
 ;
   %tmp0 = lshr <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <2 x i32> @positive_biggerlshr_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerlshr_vec(
 ; CHECK-NEXT:    [[TMP0:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 10, i32 10>
 ; CHECK-NEXT:    [[RET:%.*]] = shl nuw nsw <2 x i32> [[TMP0]], <i32 5, i32 5>
 ; CHECK-NEXT:    ret <2 x i32> [[RET]]
 ;
   %tmp0 = lshr <2 x i32> %x, <i32 10, i32 10>
   %ret = shl <2 x i32> %tmp0, <i32 5, i32 5>
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerlshr_vec_undef0(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerlshr_vec_undef0(
 ; CHECK-NEXT:    [[TMP0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 10, i32 undef, i32 10>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = shl nuw nsw <3 x i32> [[TMP0]], <i32 5, i32 5, i32 5>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = lshr <3 x i32> %x, <i32 10, i32 undef, i32 10>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 5, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerlshr_vec_undef1(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerlshr_vec_undef1(
 ; CHECK-NEXT:    [[TMP0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 10, i32 10, i32 10>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = shl nuw nsw <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = lshr <3 x i32> %x, <i32 10, i32 10, i32 10>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerlshr_vec_undef2(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerlshr_vec_undef2(
 ; CHECK-NEXT:    [[TMP0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 10, i32 undef, i32 10>
-; CHECK-NEXT:    [[RET:%.*]] = shl <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = shl nuw nsw <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = lshr <3 x i32> %x, <i32 10, i32 undef, i32 10>
   %ret = shl <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <2 x i32> @positive_biggershl_vec(<2 x i32> %x) {

test/Transforms/InstCombine/canonicalize-shl-lshr-to-masking.ll

 ;
   %tmp0 = shl <2 x i32> %x, <i32 5, i32 5>
   %ret = lshr <2 x i32> %tmp0, <i32 5, i32 5>
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @positive_sameconst_vec_undef0(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_sameconst_vec_undef0(
-; CHECK-NEXT:    [[TMP0:%.*]] = shl <3 x i32> [[X:%.*]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = lshr <3 x i32> [[TMP0]], <i32 5, i32 5, i32 5>
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[TMP0:%.*]] = and <3 x i32> [[X:%.*]], <i32 134217727, i32 134217727, i32 134217727>
+; CHECK-NEXT:    ret <3 x i32> [[TMP0]]
 ;
   %tmp0 = shl <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = lshr <3 x i32> %tmp0, <i32 5, i32 5, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_sameconst_vec_undef1(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_sameconst_vec_undef1(
-; CHECK-NEXT:    [[TMP0:%.*]] = shl <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = lshr <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[TMP0:%.*]] = and <3 x i32> [[X:%.*]], <i32 134217727, i32 134217727, i32 134217727>
+; CHECK-NEXT:    ret <3 x i32> [[TMP0]]
 ;
   %tmp0 = shl <3 x i32> %x, <i32 5, i32 5, i32 5>
   %ret = lshr <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_sameconst_vec_undef2(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_sameconst_vec_undef2(
-; CHECK-NEXT:    [[RET:%.*]] = and <3 x i32> [[X:%.*]], <i32 134217727, i32 undef, i32 134217727>
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[TMP0:%.*]] = and <3 x i32> [[X:%.*]], <i32 134217727, i32 134217727, i32 134217727>
+; CHECK-NEXT:    ret <3 x i32> [[TMP0]]
 ;
   %tmp0 = shl <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = lshr <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <2 x i32> @positive_biggerShl_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerShl_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 5, i32 5>
 ; CHECK-NEXT:    [[RET:%.*]] = and <2 x i32> [[TMP1]], <i32 134217696, i32 134217696>
 ; CHECK-NEXT:    ret <2 x i32> [[RET]]
 ;
   %tmp0 = shl <2 x i32> %x, <i32 10, i32 10>
   %ret = lshr <2 x i32> %tmp0, <i32 5, i32 5>
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerShl_vec_undef0(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerShl_vec_undef0(
-; CHECK-NEXT:    [[TMP0:%.*]] = shl <3 x i32> [[X:%.*]], <i32 10, i32 undef, i32 10>
-; CHECK-NEXT:    [[RET:%.*]] = lshr <3 x i32> [[TMP0]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = and <3 x i32> [[TMP1]], <i32 134217696, i32 134217696, i32 134217696>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = shl <3 x i32> %x, <i32 10, i32 undef, i32 10>
   %ret = lshr <3 x i32> %tmp0, <i32 5, i32 5, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerShl_vec_undef1(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerShl_vec_undef1(
-; CHECK-NEXT:    [[TMP0:%.*]] = shl <3 x i32> [[X:%.*]], <i32 10, i32 10, i32 10>
-; CHECK-NEXT:    [[RET:%.*]] = lshr <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = and <3 x i32> [[TMP1]], <i32 134217696, i32 134217696, i32 134217696>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = shl <3 x i32> %x, <i32 10, i32 10, i32 10>
   %ret = lshr <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerShl_vec_undef2(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerShl_vec_undef2(
-; CHECK-NEXT:    [[TMP0:%.*]] = shl <3 x i32> [[X:%.*]], <i32 10, i32 undef, i32 10>
-; CHECK-NEXT:    [[RET:%.*]] = lshr <3 x i32> [[TMP0]], <i32 5, i32 undef, i32 5>
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = and <3 x i32> [[TMP1]], <i32 134217696, i32 134217696, i32 134217696>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = shl <3 x i32> %x, <i32 10, i32 undef, i32 10>
   %ret = lshr <3 x i32> %tmp0, <i32 5, i32 undef, i32 5>
   ret <3 x i32> %ret
 }
 
 define <2 x i32> @positive_biggerLshr_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerLshr_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 5, i32 5>
 ; CHECK-NEXT:    [[RET:%.*]] = and <2 x i32> [[TMP1]], <i32 4194303, i32 4194303>
 ; CHECK-NEXT:    ret <2 x i32> [[RET]]
 ;
   %tmp0 = shl <2 x i32> %x, <i32 5, i32 5>
   %ret = lshr <2 x i32> %tmp0, <i32 10, i32 10>
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerLshr_vec_undef0(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerLshr_vec_undef0(
-; CHECK-NEXT:    [[TMP0:%.*]] = shl <3 x i32> [[X:%.*]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = lshr <3 x i32> [[TMP0]], <i32 10, i32 10, i32 10>
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = and <3 x i32> [[TMP1]], <i32 4194303, i32 4194303, i32 4194303>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = shl <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = lshr <3 x i32> %tmp0, <i32 10, i32 10, i32 10>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerLshr_vec_undef1(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerLshr_vec_undef1(
-; CHECK-NEXT:    [[TMP0:%.*]] = shl <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = lshr <3 x i32> [[TMP0]], <i32 10, i32 undef, i32 10>
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = and <3 x i32> [[TMP1]], <i32 4194303, i32 4194303, i32 4194303>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = shl <3 x i32> %x, <i32 5, i32 5, i32 5>
   %ret = lshr <3 x i32> %tmp0, <i32 10, i32 undef, i32 10>
   ret <3 x i32> %ret
 }
 
 define <3 x i32> @positive_biggerLshr_vec_undef2(<3 x i32> %x) {
 ; CHECK-LABEL: @positive_biggerLshr_vec_undef2(
-; CHECK-NEXT:    [[TMP0:%.*]] = shl <3 x i32> [[X:%.*]], <i32 5, i32 undef, i32 5>
-; CHECK-NEXT:    [[RET:%.*]] = lshr <3 x i32> [[TMP0]], <i32 10, i32 undef, i32 10>
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 5, i32 5, i32 5>
+; CHECK-NEXT:    [[RET:%.*]] = and <3 x i32> [[TMP1]], <i32 4194303, i32 4194303, i32 4194303>
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %tmp0 = shl <3 x i32> %x, <i32 5, i32 undef, i32 5>
   %ret = lshr <3 x i32> %tmp0, <i32 10, i32 undef, i32 10>
   ret <3 x i32> %ret
 }
 
 ; ============================================================================ ;

test/Transforms/InstCombine/masked-merge-add.ll

;
   %ret = add <2 x i32> %and, %and1
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @p_constmask_vec_undef(<3 x i32> %x, <3 x i32> %y) {
 ; CHECK-LABEL: @p_constmask_vec_undef(
 ; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[X:%.*]], <i32 65280, i32 undef, i32 65280>
 ; CHECK-NEXT:    [[AND1:%.*]] = and <3 x i32> [[Y:%.*]], <i32 -65281, i32 undef, i32 -65281>
-; CHECK-NEXT:    [[RET:%.*]] = add <3 x i32> [[AND]], [[AND1]]
+; CHECK-NEXT:    [[RET:%.*]] = or <3 x i32> [[AND]], [[AND1]]
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %and = and <3 x i32> %x, <i32 65280, i32 undef, i32 65280>
   %and1 = and <3 x i32> %y, <i32 -65281, i32 undef, i32 -65281>
   %ret = add <3 x i32> %and, %and1
   ret <3 x i32> %ret
 }
 
;
   %ret = add <2 x i32> %and, %and1
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @p_constmask2_vec_undef(<3 x i32> %x, <3 x i32> %y) {
 ; CHECK-LABEL: @p_constmask2_vec_undef(
 ; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[X:%.*]], <i32 61440, i32 undef, i32 61440>
 ; CHECK-NEXT:    [[AND1:%.*]] = and <3 x i32> [[Y:%.*]], <i32 -65281, i32 undef, i32 -65281>
-; CHECK-NEXT:    [[RET:%.*]] = add <3 x i32> [[AND]], [[AND1]]
+; CHECK-NEXT:    [[RET:%.*]] = or <3 x i32> [[AND]], [[AND1]]
 ; CHECK-NEXT:    ret <3 x i32> [[RET]]
 ;
   %and = and <3 x i32> %x, <i32 61440, i32 undef, i32 61440>
   %and1 = and <3 x i32> %y, <i32 -65281, i32 undef, i32 -65281>
   %ret = add <3 x i32> %and, %and1
   ret <3 x i32> %ret
 }
 

test/Transforms/InstCombine/masked-merge-xor.ll

;
   %ret = xor <2 x i32> %and, %and1
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @p_constmask_vec_undef(<3 x i32> %x, <3 x i32> %y) {
 ; CHECK-LABEL: @p_constmask_vec_undef(
 ; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[X:%.*]], <i32 65280, i32 undef, i32 65280>
 ; CHECK-NEXT:    [[AND1:%.*]] = and <3 x i32> [[Y:%.*]], <i32 -65281, i32 undef, i32 -65281>
-; CHECK-NEXT:    [[RET:%.*]] = xor <3 x i32> [[AND]], [[AND1]]
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[RET1:%.*]] = or <3 x i32> [[AND]], [[AND1]]
+; CHECK-NEXT:    ret <3 x i32> [[RET1]]
 ;
   %and = and <3 x i32> %x, <i32 65280, i32 undef, i32 65280>
   %and1 = and <3 x i32> %y, <i32 -65281, i32 undef, i32 -65281>
   %ret = xor <3 x i32> %and, %and1
   ret <3 x i32> %ret
 }
 
 ; ============================================================================ ;
;
   %ret = xor <2 x i32> %and, %and1
   ret <2 x i32> %ret
 }
 
 define <3 x i32> @p_constmask2_vec_undef(<3 x i32> %x, <3 x i32> %y) {
 ; CHECK-LABEL: @p_constmask2_vec_undef(
 ; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[X:%.*]], <i32 61440, i32 undef, i32 61440>
 ; CHECK-NEXT:    [[AND1:%.*]] = and <3 x i32> [[Y:%.*]], <i32 -65281, i32 undef, i32 -65281>
-; CHECK-NEXT:    [[RET:%.*]] = xor <3 x i32> [[AND]], [[AND1]]
-; CHECK-NEXT:    ret <3 x i32> [[RET]]
+; CHECK-NEXT:    [[RET1:%.*]] = or <3 x i32> [[AND]], [[AND1]]
+; CHECK-NEXT:    ret <3 x i32> [[RET1]]
 ;
   %and = and <3 x i32> %x, <i32 61440, i32 undef, i32 61440>
   %and1 = and <3 x i32> %y, <i32 -65281, i32 undef, i32 -65281>
   %ret = xor <3 x i32> %and, %and1
   ret <3 x i32> %ret
 }
 
 ; ============================================================================ ;

test/Transforms/InstCombine/vec_shuffle.ll

 ;
   %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
   %r = shl <2 x i32> %splat, <i32 5, i32 5>
   ret <2 x i32> %r
 }
 
 define <2 x i32> @ashr_splat_constant0(<2 x i32> %x) {
 ; CHECK-LABEL: @ashr_splat_constant0(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> <i32 5, i32 undef>, [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> <i32 5, i32 undef>, [[X:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
   %r = ashr <2 x i32> <i32 5, i32 5>, %splat
   ret <2 x i32> %r
 }