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Differential D47941

[mips] Add additional parameter to LONG_BRANCH_LUi/ADDiu pseudo instructions
ClosedPublic

Authored by abeserminji on Jun 8 2018, 6:12 AM.

Details

Reviewers
sdardis
petarj
Commits
rG8acdc10220af: [mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter
rL334490: [mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter
Summary

Extend LONG_BRANCH_LUi and LONG_BRANCH_ADDiu pseudo instructions
with additional flag, so instead of always lowering to lui %hi(...), addiu %lo(...) or addiu %hi(...),
now they can lower to either %lo, %hi, %higher or %highest depending on the added flag.

Diff Detail

Repository
rL LLVM

Event Timeline

abeserminji created this revision.Jun 8 2018, 6:12 AM
Herald added subscribers: atanasyan, arichardson. · View Herald TranscriptJun 8 2018, 6:12 AM
abeserminji edited the summary of this revision. (Show Details)Jun 8 2018, 6:14 AM
sdardis accepted this revision.Jun 11 2018, 4:22 AM

LGTM with nit addressed.

lib/Target/Mips/MipsMCInstLower.cpp
274 ↗(On Diff #150497)

Spurious semi-colon.

This revision is now accepted and ready to land.Jun 11 2018, 4:22 AM
abeserminji updated this revision to Diff 150766.Jun 11 2018, 8:25 AM
abeserminji marked an inline comment as done.

Comment addressed.

Closed by commit rL334490: [mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter (authored by abeserminji). · Explain WhyJun 12 2018, 3:28 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 150921

llvm/trunk/lib/Target/Mips/MipsBranchExpansion.cpp

Show First 20 Lines • Show All 440 Lines • ▼ Show 20 Lines if (!ABI.IsN64()) {
// we replace LUi and ADDiu with pseudo instructions // we replace LUi and ADDiu with pseudo instructions
// LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic // LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic
// blocks as operands to these instructions. When lowering these pseudo // blocks as operands to these instructions. When lowering these pseudo
// instructions to LUi and ADDiu in the MC layer, we will create // instructions to LUi and ADDiu in the MC layer, we will create
// %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
// operands to lowered instructions. // operands to lowered instructions.
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
.addMBB(TgtMBB) .addMBB(TgtMBB, MipsII::MO_ABS_HI)
.addMBB(BalTgtMBB); .addMBB(BalTgtMBB);
MachineInstrBuilder BalInstr = MachineInstrBuilder BalInstr =
BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
MachineInstrBuilder ADDiuInstr = MachineInstrBuilder ADDiuInstr =
BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
.addReg(Mips::AT) .addReg(Mips::AT)
.addMBB(TgtMBB) .addMBB(TgtMBB, MipsII::MO_ABS_LO)
.addMBB(BalTgtMBB); .addMBB(BalTgtMBB);
if (STI->hasMips32r6()) { if (STI->hasMips32r6()) {
LongBrMBB->insert(Pos, ADDiuInstr); LongBrMBB->insert(Pos, ADDiuInstr);
LongBrMBB->insert(Pos, BalInstr); LongBrMBB->insert(Pos, BalInstr);
} else { } else {
LongBrMBB->insert(Pos, BalInstr); LongBrMBB->insert(Pos, BalInstr);
LongBrMBB->insert(Pos, ADDiuInstr); LongBrMBB->insert(Pos, ADDiuInstr);
LongBrMBB->rbegin()->bundleWithPred(); LongBrMBB->rbegin()->bundleWithPred();
▲ Show 20 Lines • Show All 333 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsMCInstLower.h

Show All 38 Linespublic:
MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const; MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const;
private: private:
MCOperand LowerSymbolOperand(const MachineOperand &MO, MCOperand LowerSymbolOperand(const MachineOperand &MO,
MachineOperandType MOTy, unsigned Offset) const; MachineOperandType MOTy, unsigned Offset) const;
MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2, MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
MipsMCExpr::MipsExprKind Kind) const; MipsMCExpr::MipsExprKind Kind) const;
void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const; void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode, void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
MipsMCExpr::MipsExprKind Kind) const; int Opcode) const;
bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const; bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
}; };
} // end namespace llvm } // end namespace llvm
#endif // LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H #endif // LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H

llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp

Show First 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
void MipsMCInstLower:: void MipsMCInstLower::
lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const { lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(Mips::LUi); OutMI.setOpcode(Mips::LUi);
// Lower register operand. // Lower register operand.
OutMI.addOperand(LowerOperand(MI->getOperand(0))); OutMI.addOperand(LowerOperand(MI->getOperand(0)));
MipsMCExpr::MipsExprKind Kind;
unsigned TargetFlags = MI->getOperand(1).getTargetFlags();
switch (TargetFlags) {
case MipsII::MO_HIGHEST:
Kind = MipsMCExpr::MEK_HIGHEST;
break;
case MipsII::MO_HIGHER:
Kind = MipsMCExpr::MEK_HIGHER;
break;
case MipsII::MO_ABS_HI:
Kind = MipsMCExpr::MEK_HI;
break;
case MipsII::MO_ABS_LO:
Kind = MipsMCExpr::MEK_LO;
break;
default:
report_fatal_error("Unexpected flags for lowerLongBranchLUi");
}
if (MI->getNumOperands() == 2) {
const MCExpr *Expr =
MCSymbolRefExpr::create(MI->getOperand(1).getMBB()->getSymbol(), *Ctx);
const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
OutMI.addOperand(MCOperand::createExpr(MipsExpr));
} else if (MI->getNumOperands() == 3) {
// Create %hi($tgt-$baltgt). // Create %hi($tgt-$baltgt).
OutMI.addOperand(createSub(MI->getOperand(1).getMBB(), OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
MI->getOperand(2).getMBB(), MI->getOperand(2).getMBB(), Kind));
MipsMCExpr::MEK_HI)); }
} }
void MipsMCInstLower::lowerLongBranchADDiu( void MipsMCInstLower::lowerLongBranchADDiu(const MachineInstr *MI,
const MachineInstr *MI, MCInst &OutMI, int Opcode, MCInst &OutMI, int Opcode) const {
MipsMCExpr::MipsExprKind Kind) const {
OutMI.setOpcode(Opcode); OutMI.setOpcode(Opcode);
MipsMCExpr::MipsExprKind Kind;
unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
switch (TargetFlags) {
case MipsII::MO_HIGHEST:
Kind = MipsMCExpr::MEK_HIGHEST;
break;
case MipsII::MO_HIGHER:
Kind = MipsMCExpr::MEK_HIGHER;
break;
case MipsII::MO_ABS_HI:
Kind = MipsMCExpr::MEK_HI;
break;
case MipsII::MO_ABS_LO:
Kind = MipsMCExpr::MEK_LO;
break;
default:
report_fatal_error("Unexpected flags for lowerLongBranchADDiu");
}
// Lower two register operands. // Lower two register operands.
for (unsigned I = 0, E = 2; I != E; ++I) { for (unsigned I = 0, E = 2; I != E; ++I) {
const MachineOperand &MO = MI->getOperand(I); const MachineOperand &MO = MI->getOperand(I);
OutMI.addOperand(LowerOperand(MO)); OutMI.addOperand(LowerOperand(MO));
} }
if (MI->getNumOperands() == 3) {
// Lower register operand.
const MCExpr *Expr =
MCSymbolRefExpr::create(MI->getOperand(2).getMBB()->getSymbol(), *Ctx);
const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
OutMI.addOperand(MCOperand::createExpr(MipsExpr));
} else if (MI->getNumOperands() == 4) {
// Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt). // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
OutMI.addOperand(createSub(MI->getOperand(2).getMBB(), OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
MI->getOperand(3).getMBB(), Kind)); MI->getOperand(3).getMBB(), Kind));
} }
}
bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI, bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI,
MCInst &OutMI) const { MCInst &OutMI) const {
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
default: default:
return false; return false;
case Mips::LONG_BRANCH_LUi: case Mips::LONG_BRANCH_LUi:
lowerLongBranchLUi(MI, OutMI); lowerLongBranchLUi(MI, OutMI);
return true; return true;
case Mips::LONG_BRANCH_ADDiu: case Mips::LONG_BRANCH_ADDiu:
lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu, MipsMCExpr::MEK_LO); lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu);
return true; return true;
case Mips::LONG_BRANCH_DADDiu: case Mips::LONG_BRANCH_DADDiu:
unsigned TargetFlags = MI->getOperand(2).getTargetFlags(); lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu);
if (TargetFlags == MipsII::MO_ABS_HI)
lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_HI);
else if (TargetFlags == MipsII::MO_ABS_LO)
lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_LO);
else
report_fatal_error("Unexpected flags for LONG_BRANCH_DADDiu");
return true; return true;
} }
} }
void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
if (lowerLongBranch(MI, OutMI)) if (lowerLongBranch(MI, OutMI))
return; return;
Show All 10 Lines

llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Linesbody: |
; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0 ; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
; PIC: BC1F_MM $fcc0, %bb.3, implicit-def $at { ; PIC: BC1F_MM $fcc0, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1.entry: ; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra { ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2.entry: ; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Linesbody: |
; PIC: bb.0.entry: ; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000) ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64 ; PIC: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
; PIC: BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $at ; PIC: BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $at
; PIC: bb.1.entry: ; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2.entry: ; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.if.then: ; PIC: bb.3.if.then:
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesbody: |
; PIC: bb.0.entry: ; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; PIC: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; PIC: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64 ; PIC: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
; PIC: BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $at ; PIC: BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $at
; PIC: bb.1.entry: ; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2.entry: ; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.if.then: ; PIC: bb.3.if.then:
Show All 23 Lines

llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Linesbody: |
; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0 ; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
; PIC: BC1F $fcc0, %bb.3, implicit-def $at { ; PIC: BC1F $fcc0, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1.entry: ; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra { ; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2.entry: ; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesbody: |
; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0 ; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
; PIC: BC1T $fcc0, %bb.3, implicit-def $at { ; PIC: BC1T $fcc0, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1.entry: ; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra { ; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2.entry: ; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
Show All 26 Lines

llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Linesbody: |
; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64 ; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
; PIC: BC1NEZ $d0_64, %bb.3 { ; PIC: BC1NEZ $d0_64, %bb.3 {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1.entry: ; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2.entry: ; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.if.then: ; PIC: bb.3.if.then:
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Linesbody: |
; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64 ; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
; PIC: BC1EQZ $d0_64, %bb.3 { ; PIC: BC1EQZ $d0_64, %bb.3 {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1.entry: ; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2.entry: ; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.if.then: ; PIC: bb.3.if.then:
Show All 25 Lines

llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Linesbody: |
; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BNEZC_MM $at, %bb.3, implicit-def $at ; PIC: BNEZC_MM $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra { ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Linesbody: |
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLTZ_MM $at, %bb.3, implicit-def $at { ; PIC: BLTZ_MM $at, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra { ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Linesbody: |
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLEZ_MM $at, %bb.3, implicit-def $at { ; PIC: BLEZ_MM $at, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra { ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Linesbody: |
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGTZ_MM $at, %bb.3, implicit-def $at { ; PIC: BGTZ_MM $at, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra { ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Linesbody: |
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGEZ_MM $at, %bb.3, implicit-def $at { ; PIC: BGEZ_MM $at, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra { ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BEQZC_MM $at, %bb.3, implicit-def $at ; PIC: BEQZC_MM $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra { ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
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; PIC: renamable $v0 = ANDi killed renamable $a0, 1 ; PIC: renamable $v0 = ANDi killed renamable $a0, 1
; PIC: BNEZ16_MM $v0, %bb.3, implicit-def $at { ; PIC: BNEZ16_MM $v0, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra { ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Linesbody: |
; PIC: renamable $v0 = ANDi killed renamable $a0, 1 ; PIC: renamable $v0 = ANDi killed renamable $a0, 1
; PIC: BEQZ16_MM $v0, %bb.3, implicit-def $at { ; PIC: BEQZ16_MM $v0, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra { ; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
Show All 21 Lines

llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Linesbody: |
; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BNEC_MMR6 $at, $zero, %bb.3, implicit-def $at ; PIC: BNEC_MMR6 $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Linesbody: |
; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BEQC_MMR6 $at, $zero, %bb.3, implicit-def $at ; PIC: BEQC_MMR6 $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLTC_MMR6 $at, $zero, %bb.3, implicit-def $at ; PIC: BLTC_MMR6 $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLTUC_MMR6 $at, $zero, %bb.3, implicit-def $at ; PIC: BLTUC_MMR6 $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLTZC_MMR6 $at, %bb.3, implicit-def $at ; PIC: BLTZC_MMR6 $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLEZC_MMR6 $at, %bb.3, implicit-def $at ; PIC: BLEZC_MMR6 $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGTZC_MMR6 $at, %bb.3, implicit-def $at ; PIC: BGTZC_MMR6 $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGEC_MMR6 $at, $zero, %bb.3, implicit-def $at ; PIC: BGEC_MMR6 $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGEUC_MMR6 $at, $zero, %bb.3, implicit-def $at ; PIC: BGEUC_MMR6 $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGEZC_MMR6 $at, %bb.3, implicit-def $at ; PIC: BGEZC_MMR6 $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BNEZC_MMR6 $at, %bb.3, implicit-def $at ; PIC: BNEZC_MMR6 $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BEQZC_MMR6 $at, %bb.3, implicit-def $at ; PIC: BEQZC_MMR6 $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at ; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir

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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BNEC $at, $zero, %bb.3, implicit-def $at ; PIC: BNEC $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BEQC $at, $zero, %bb.3, implicit-def $at ; PIC: BEQC $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLTC $at, $zero, %bb.3, implicit-def $at ; PIC: BLTC $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLTUC $at, $zero, %bb.3, implicit-def $at ; PIC: BLTUC $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLTZC $at, %bb.3, implicit-def $at ; PIC: BLTZC $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLEZC $at, %bb.3, implicit-def $at ; PIC: BLEZC $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGTZC $at, %bb.3, implicit-def $at ; PIC: BGTZC $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGEC $at, $zero, %bb.3, implicit-def $at ; PIC: BGEC $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGEUC $at, $zero, %bb.3, implicit-def $at ; PIC: BGEUC $at, $zero, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGEZC $at, %bb.3, implicit-def $at ; PIC: BGEZC $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BNEZC $at, %bb.3, implicit-def $at ; PIC: BNEZC $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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; PIC: bb.0 (%ir-block.0): ; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BEQZC $at, %bb.3, implicit-def $at ; PIC: BEQZC $at, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra ; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at ; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.iftrue: ; PIC: bb.3.iftrue:
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llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir

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; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BNE $at, $zero, %bb.3, implicit-def $at { ; PIC: BNE $at, $zero, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra { ; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
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; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLTZ $at, %bb.3, implicit-def $at { ; PIC: BLTZ $at, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra { ; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
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; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BLEZ $at, %bb.3, implicit-def $at { ; PIC: BLEZ $at, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra { ; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
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; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGTZ $at, %bb.3, implicit-def $at { ; PIC: BGTZ $at, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra { ; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
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; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BGEZ $at, %bb.3, implicit-def $at { ; PIC: BGEZ $at, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra { ; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
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; PIC: renamable $at = ANDi killed renamable $a0, 1 ; PIC: renamable $at = ANDi killed renamable $a0, 1
; PIC: BEQ $at, $zero, %bb.3, implicit-def $at { ; PIC: BEQ $at, $zero, %bb.3, implicit-def $at {
; PIC: NOP ; PIC: NOP
; PIC: } ; PIC: }
; PIC: bb.1 (%ir-block.0): ; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000) ; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8 ; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0 ; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra { ; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: } ; PIC: }
; PIC: bb.2 (%ir-block.0): ; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000) ; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at ; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0 ; PIC: $ra = LW $sp, 0
; PIC: JR $at { ; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8 ; PIC: $sp = ADDiu $sp, 8
; PIC: } ; PIC: }
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