[AArch64][SVE] Addition patterns for integer scalable vectors

[huntergr]

Summary

Adds ISel patterns to match register-register add operations on
integer scalable vector types, along with unit tests.

Part of the initial SVE codegen series, rfc will be posted soon. Note: this patch is currently just to support the scalable vector codegen rfc, and does not need a full review yet.

[huntergr]

A better set of patterns will be created later.

lib/Target/AArch64/AArch64SVEInstrInfo.td

def : Pat<(store (nxv16i8 ZPR:$val), GPR64sp:$base),
             (ST1B_IMM ZPR:$val, (PTRUE_B 31), GPR64sp:$base, (i64 0))>;
   def : Pat<(store (nxv8i16 ZPR:$val), GPR64sp:$base),
             (ST1H_IMM ZPR:$val, (PTRUE_H 31), GPR64sp:$base, (i64 0))>;
   def : Pat<(store (nxv4i32 ZPR:$val), GPR64sp:$base),
             (ST1W_IMM ZPR:$val, (PTRUE_S 31), GPR64sp:$base, (i64 0))>;
   def : Pat<(store (nxv2i64 ZPR:$val), GPR64sp:$base),
             (ST1D_IMM ZPR:$val, (PTRUE_D 31), GPR64sp:$base, (i64 0))>;
 
+  // Add
+  def : Pat<(nxv16i8 (add (nxv16i8 ZPR:$Zs1), (nxv16i8 ZPR:$Zs2))),
+            (ADD_ZZZ_B ZPR:$Zs1, ZPR:$Zs2)>;
+  def : Pat<(nxv8i16 (add (nxv8i16 ZPR:$Zs1), (nxv8i16 ZPR:$Zs2))),
+            (ADD_ZZZ_H ZPR:$Zs1, ZPR:$Zs2)>;
+  def : Pat<(nxv4i32 (add (nxv4i32 ZPR:$Zs1), (nxv4i32 ZPR:$Zs2))),
+            (ADD_ZZZ_S ZPR:$Zs1, ZPR:$Zs2)>;
+  def : Pat<(nxv2i64 (add (nxv2i64 ZPR:$Zs1), (nxv2i64 ZPR:$Zs2))),
+            (ADD_ZZZ_D ZPR:$Zs1, ZPR:$Zs2)>;
 }

test/CodeGen/AArch64/SVE/arith.ll

+; RUN: llc -verify-machineinstrs -mattr=+sve < %s | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnueabi"
+
+define <scalable 16 x i8> @add_reg_b(<scalable 16 x i8> %a, <scalable 16 x i8> %b) {
+; CHECK-LABEL: add_reg_b:
+; CHECK: add z0.b, z0.b, z1.b
+; CHECK-NEXT: ret
+  %res = add <scalable 16 x i8> %a, %b
+  ret <scalable 16 x i8> %res
+}
+
+define <scalable 8 x i16> @add_reg_h(<scalable 8 x i16> %a, <scalable 8 x i16> %b) {
+; CHECK-LABEL: add_reg_h:
+; CHECK: add z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %res = add <scalable 8 x i16> %a, %b
+  ret <scalable 8 x i16> %res
+}
+
+define <scalable 4 x i32> @add_reg_s(<scalable 4 x i32> %a, <scalable 4 x i32> %b) {
+; CHECK-LABEL: add_reg_s:
+; CHECK: add z0.s, z0.s, z1.s
+; CHECK-NEXT: ret
+  %res = add <scalable 4 x i32> %a, %b
+  ret <scalable 4 x i32> %res
+}
+
+define <scalable 2 x i64> @add_reg_d(<scalable 2 x i64> %a, <scalable 2 x i64> %b) {
+; CHECK-LABEL: add_reg_d:
+; CHECK: add z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+  %res = add <scalable 2 x i64> %a, %b
+  ret <scalable 2 x i64> %res
+}