[CodeGen] print max throughput for 0-latency insts

[spatel]

Summary

This is a fix for the problem arising in D47374 (PR37678):
https://bugs.llvm.org/show_bug.cgi?id=37678

We don't have throughput info for instructions with variant scheduling, so assume that a zero latency inst can execute/complete at max-issue-width.

[andreadb]

Hey Sanjay,

what if instead we change method MCSchedModel::getReciprocalThroughput?
If we decide to always return a meaningful value for instructions that don't consume processor resources, then I think that we can get rid of Optional<>.
If an instruction is associated with an invalid scheduling class (i.e. !SCDesc->isValid()), then we should just return 1/IssueWidth.
If an instruction doesn't consume resources, then we should return N/IssueWidth (where N is the NumMicroOpcodes).

I also prefer that we don't touch getSchedInfoStr(). My opinion is that adding extra logic to that method is going to make it difficult to get rid of it in the next future. Strictly speaking, the idea of adding that method to the subtarget was bad; there is no reason why the "profile string" should be returned by the subtarget!... My wish is that we get rid of getSchedInfoStr() (as well as function createSchedInfoStr) in the near future.

Not sure if this makes sense.

-Andrea

[spatel]

In D47723#1121109, @andreadb wrote:

Hey Sanjay,

what if instead we change method MCSchedModel::getReciprocalThroughput?
If we decide to always return a meaningful value for instructions that don't consume processor resources, then I think that we can get rid of Optional<>.
If an instruction is associated with an invalid scheduling class (i.e. !SCDesc->isValid()), then we should just return 1/IssueWidth.
If an instruction doesn't consume resources, then we should return N/IssueWidth (where N is the NumMicroOpcodes).

I also prefer that we don't touch getSchedInfoStr(). My opinion is that adding extra logic to that method is going to make it difficult to get rid of it in the next future. Strictly speaking, the idea of adding that method to the subtarget was bad; there is no reason why the "profile string" should be returned by the subtarget!... My wish is that we get rid of getSchedInfoStr() (as well as function createSchedInfoStr) in the near future.

Not sure if this makes sense.

Yes, I think that all makes sense. I actually looked at the higher-level change first to remove the Optional<>, but I wasn't sure if we wanted to do that or just go with the quick hack for now. I'll have a look at fixing this better.

[spatel]

Patch updated:
Please have a close look at the diffs because I'm not sure how to test all of these paths.

The cases that I see behaving as intended via tests are the recent variant scheduled "xorps %xmm0, %xmm0" and existing non-zero latency cases like:
; ZNVER1-SSE-NEXT: ldmxcsr -{{[0-9]+}}(%rsp) # sched: [100:?]
(those cases are all unchanged, as I think is expected for this patch...but let me know if we want to treat that differently)

The big logical difference in this patch is that instead of using an Optional, we rely on FP NaN to represent the unknown state. Then, we modify the throughput calcs to account for the cases where no execution resources are specified by using default/max issue widths.

[andreadb]

In D47723#1121600, @spatel wrote:

Patch updated:
Please have a close look at the diffs because I'm not sure how to test all of these paths.

The cases that I see behaving as intended via tests are the recent variant scheduled "xorps %xmm0, %xmm0" and existing non-zero latency cases like:
; ZNVER1-SSE-NEXT: ldmxcsr -{{[0-9]+}}(%rsp) # sched: [100:?]
(those cases are all unchanged, as I think is expected for this patch...but let me know if we want to treat that differently)

I think that IssueWidth/NumMicroOps should always be the upper bound for the throughput. So, I am of the opinion that we should not restrict this change to zero latency instructions.

The big logical difference in this patch is that instead of using an Optional, we rely on FP NaN to represent the unknown state. Then, we modify the throughput calcs to account for the cases where no execution resources are specified by using default/max issue widths.

I think it is easier to use 0.0 as the default "unknown" value.
The reciprocal throughput can never be 0.0; a RThrougput of zero effectively means that the throughput tends to infinite. This is an impossible scenario since we don't have infinite parallelism in hardware (i.e. we cannot model infinite resources), and we cannot execute an infinite number of instructions per cycle. Essentially, 0.0 is our asymptote.
So, it is safe to use 0.0 as the special "unknown" throughput. For instructions that don't consume resource cycles we would still return N/IssueWidth.
Also, you don't need to use the "unknown" value in any max computation (see comments below).

lib/CodeGen/TargetSchedule.cpp

336 ↗

(On Diff #149845)

I would just return 0.0 instead of NaN.

351 ↗

(On Diff #149845)

Same.

lib/CodeGen/TargetSubtargetInfo.cpp

74 ↗

(On Diff #149845)

If we use 0.0 as the unknown value, then this would become:

IF (Rthroughput != 0.0)

lib/MC/MCSchedule.cpp

91–111 ↗

(On Diff #149845)

My opinion is that we should not limit this to zero-latency instructions.

Here, you could have just reused the original code which computes the Throughput as a Optional<double>.

If Throughput is not defined, then simply return SCDesc.NumMicroOps / SM.IssueWidth.
Basically, you should be able to only change the return statement.

149 ↗

(On Diff #149845)

You can simply return 1/DefaultIssueWidth.
This computation may not accurate; ideally, we should use the actual IssueWidth from the scheduling model. In practice, this code is not used: x86 models don't use itineraries, and - as far as I know - x86 is the only target that enables the -print-schedule functionality.
Fixing this would probably require a change to this API, which is probably outside of the scope of this patch. For now, I think that returning a default 1/DefaultIssueWidth is good enough.

[spatel]

Patch updated:
Calculate throughput for non-zero-latency instructions with no throughput specified.
This is a smaller code change than the last rev, but as shown, it results in a large amount of test diffs.
I was trying to avoid this in previous versions of the patch, but I think it makes sense given that the code change is smaller if we jump directly to this step.

[andreadb]

Thanks Sanjay.
It looks good to me.
I agree that this affects a lot of tests. However it looks like most of the diffs are for znver1, which apparently assigns an arbitrary 100cy latency , 1 uOp and no processor resource cycles to all microcoded instructions. So I am not particularly worried about it.
In the absence of extra/accurate schedule information, I think that computing an optimistic reciprocal throughput based on the number of opcodes and IssueWidth is the best that we can do.

llvm/trunk/include/llvm/CodeGen/TargetSchedule.h

#endif
 
   /// Output dependency latency of a pair of defs of the same register.
   ///
   /// This is typically one cycle.
   unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
                                 const MachineInstr *DepMI) const;
 
   /// Compute the reciprocal throughput of the given instruction.
-  Optional<double> computeReciprocalThroughput(const MachineInstr *MI) const;
-  Optional<double> computeReciprocalThroughput(const MCInst &MI) const;
-  Optional<double> computeReciprocalThroughput(unsigned Opcode) const;
+  double computeReciprocalThroughput(const MachineInstr *MI) const;
+  double computeReciprocalThroughput(const MCInst &MI) const;
+  double computeReciprocalThroughput(unsigned Opcode) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_TARGETSCHEDULE_H

llvm/trunk/include/llvm/MC/MCSchedule.h

struct MCSchedModel {
   static int computeInstrLatency(const MCSubtargetInfo &STI,
                                  const MCSchedClassDesc &SCDesc);
 
   int computeInstrLatency(const MCSubtargetInfo &STI, unsigned SClass) const;
   int computeInstrLatency(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
                           const MCInst &Inst) const;
 
   // Returns the reciprocal throughput information from a MCSchedClassDesc.
-  static Optional<double>
+  static double
   getReciprocalThroughput(const MCSubtargetInfo &STI,
                           const MCSchedClassDesc &SCDesc);
 
-  static Optional<double>
+  static double
   getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
 
-  Optional<double>
+  double
   getReciprocalThroughput(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
                           const MCInst &Inst) const;
 
   /// Returns the default initialized model.
   static const MCSchedModel &GetDefaultSchedModel() { return Default; }
   static const MCSchedModel Default;
 };
 
 } // namespace llvm
 
 #endif

llvm/trunk/lib/CodeGen/TargetSchedule.cpp

if (SCDesc->isValid()) {
         if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
           return 1;
       }
     }
   }
   return 0;
 }
 
-Optional<double>
+double
 TargetSchedModel::computeReciprocalThroughput(const MachineInstr *MI) const {
   if (hasInstrItineraries()) {
     unsigned SchedClass = MI->getDesc().getSchedClass();
     return MCSchedModel::getReciprocalThroughput(SchedClass,
                                                  *getInstrItineraries());
   }
 
   if (hasInstrSchedModel())
     return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI));
-  return Optional<double>();
+
+  return 0.0;
 }
 
-Optional<double>
+double
 TargetSchedModel::computeReciprocalThroughput(unsigned Opcode) const {
   unsigned SchedClass = TII->get(Opcode).getSchedClass();
   if (hasInstrItineraries())
     return MCSchedModel::getReciprocalThroughput(SchedClass,
                                                  *getInstrItineraries());
   if (hasInstrSchedModel()) {
     const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass);
     if (SCDesc.isValid() && !SCDesc.isVariant())
       return MCSchedModel::getReciprocalThroughput(*STI, SCDesc);
   }
-  return Optional<double>();
+
+  return 0.0;
 }
 
-Optional<double>
+double
 TargetSchedModel::computeReciprocalThroughput(const MCInst &MI) const {
   if (hasInstrSchedModel())
     return SchedModel.getReciprocalThroughput(*STI, *TII, MI);
   return computeReciprocalThroughput(MI.getOpcode());
 }
 

llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp

 bool TargetSubtargetInfo::enablePostRAScheduler() const {
   return getSchedModel().PostRAScheduler;
 }
 
 bool TargetSubtargetInfo::useAA() const {
   return false;
 }
 
-static std::string createSchedInfoStr(unsigned Latency,
-                                      Optional<double> RThroughput) {
+static std::string createSchedInfoStr(unsigned Latency, double RThroughput) {
   static const char *SchedPrefix = " sched: [";
   std::string Comment;
   raw_string_ostream CS(Comment);
-  if (RThroughput.hasValue())
-    CS << SchedPrefix << Latency << format(":%2.2f", RThroughput.getValue())
+  if (RThroughput != 0.0)
+    CS << SchedPrefix << Latency << format(":%2.2f", RThroughput)
        << "]";
   else
     CS << SchedPrefix << Latency << ":?]";
   CS.flush();
   return Comment;
 }
 
 /// Returns string representation of scheduler comment
 std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
   if (MI.isPseudo() || MI.isTerminator())
     return std::string();
   // We don't cache TSchedModel because it depends on TargetInstrInfo
   // that could be changed during the compilation
   TargetSchedModel TSchedModel;
   TSchedModel.init(this);
   unsigned Latency = TSchedModel.computeInstrLatency(&MI);
-  Optional<double> RThroughput = TSchedModel.computeReciprocalThroughput(&MI);
+  double RThroughput = TSchedModel.computeReciprocalThroughput(&MI);
   return createSchedInfoStr(Latency, RThroughput);
 }
 
 /// Returns string representation of scheduler comment
 std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
   // We don't cache TSchedModel because it depends on TargetInstrInfo
   // that could be changed during the compilation
   TargetSchedModel TSchedModel;
   TSchedModel.init(this);
   unsigned Latency;
   if (TSchedModel.hasInstrSchedModel())
     Latency = TSchedModel.computeInstrLatency(MCI);
   else if (TSchedModel.hasInstrItineraries()) {
     auto *ItinData = TSchedModel.getInstrItineraries();
     Latency = ItinData->getStageLatency(
         getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
   } else
     return std::string();
-  Optional<double> RThroughput =
-      TSchedModel.computeReciprocalThroughput(MCI);
+  double RThroughput = TSchedModel.computeReciprocalThroughput(MCI);
   return createSchedInfoStr(Latency, RThroughput);
 }
 
 void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const {
 }

llvm/trunk/lib/MC/MCSchedule.cpp

int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
   }
 
   if (SchedClass)
     return MCSchedModel::computeInstrLatency(STI, *SCDesc);
 
   llvm_unreachable("unsupported variant scheduling class");
 }
 
-Optional<double>
+double
 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
                                       const MCSchedClassDesc &SCDesc) {
   Optional<double> Throughput;
   const MCSchedModel &SM = STI.getSchedModel();
   const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
   const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
   for (; I != E; ++I) {
     if (!I->Cycles)
       continue;
     unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
     double Temp = NumUnits * 1.0 / I->Cycles;
     Throughput = Throughput ? std::min(Throughput.getValue(), Temp) : Temp;
   }
-  return Throughput ? 1 / Throughput.getValue() : Throughput;
+  if (Throughput.hasValue())
+    return 1.0 / Throughput.getValue();
+
+  // If no throughput value was calculated, assume that we can execute at the
+  // maximum issue width scaled by number of micro-ops for the schedule class.
+  return ((double)SCDesc.NumMicroOps) / SM.IssueWidth;
 }
 
-Optional<double>
+double
 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
                                       const MCInstrInfo &MCII,
                                       const MCInst &Inst) const {
-  Optional<double> Throughput;
   unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
   const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
+
+  // If there's no valid class, assume that the instruction executes/completes
+  // at the maximum issue width.
   if (!SCDesc->isValid())
-    return Throughput;
+    return 1.0 / IssueWidth;
 
   unsigned CPUID = getProcessorID();
   while (SCDesc->isVariant()) {
     SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
     SCDesc = getSchedClassDesc(SchedClass);
   }
 
   if (SchedClass)
     return MCSchedModel::getReciprocalThroughput(STI, *SCDesc);
 
   llvm_unreachable("unsupported variant scheduling class");
 }
 
-Optional<double>
+double
 MCSchedModel::getReciprocalThroughput(unsigned SchedClass,
                                       const InstrItineraryData &IID) {
   Optional<double> Throughput;
   const InstrStage *I = IID.beginStage(SchedClass);
   const InstrStage *E = IID.endStage(SchedClass);
   for (; I != E; ++I) {
     if (!I->getCycles())
       continue;
     double Temp = countPopulation(I->getUnits()) * 1.0 / I->getCycles();
     Throughput = Throughput ? std::min(Throughput.getValue(), Temp) : Temp;
   }
-  return Throughput ? 1 / Throughput.getValue() : Throughput;
+  if (Throughput.hasValue())
+    return 1.0 / Throughput.getValue();
+
+  // If there are no execution resources specified for this class, then assume
+  // that it can execute at the maximum default issue width.
+  return 1.0 / DefaultIssueWidth;
 }

llvm/trunk/test/CodeGen/X86/avx-schedule.ll

 ; BTVER2-LABEL: test_dpps:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [12:6.00]
 ; BTVER2-NEXT:    vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [17:6.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_dpps:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7)
   %2 = load <8 x float>, <8 x float> *%a2, align 32
   %3 = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %1, <8 x float> %2, i8 7)
   ret <8 x float> %3
 }
 declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
 

 ; BTVER2-NEXT:    vextractf128 $1, %ymm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    vextractf128 $1, %ymm1, (%rdi) # sched: [1:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_extractf128:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vextractf128 $1, %ymm0, %xmm0 # sched: [1:0.33]
 ; ZNVER1-NEXT:    vextractf128 $1, %ymm1, (%rdi) # sched: [8:0.50]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = shufflevector <8 x float> %a0, <8 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %2 = shufflevector <8 x float> %a1, <8 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   store <4 x float> %2, <4 x float> *%a2
   ret <4 x float> %1
 }
 
 define <4 x double> @test_haddpd(<4 x double> %a0, <4 x double> %a1, <4 x double> *%a2) {

 ; BTVER2-LABEL: test_haddpd:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [8:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_haddpd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %a0, <4 x double> %a1)
   %2 = load <4 x double>, <4 x double> *%a2, align 32
   %3 = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %1, <4 x double> %2)
   ret <4 x double> %3
 }
 declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>) nounwind readnone
 

 ; BTVER2-LABEL: test_haddps:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [8:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_haddps:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1)
   %2 = load <8 x float>, <8 x float> *%a2, align 32
   %3 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %1, <8 x float> %2)
   ret <8 x float> %3
 }
 declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind readnone
 

 ; BTVER2-LABEL: test_hsubpd:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [8:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_hsubpd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1)
   %2 = load <4 x double>, <4 x double> *%a2, align 32
   %3 = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %1, <4 x double> %2)
   ret <4 x double> %3
 }
 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
 

 ; BTVER2-LABEL: test_hsubps:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [8:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_hsubps:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1)
   %2 = load <8 x float>, <8 x float> *%a2, align 32
   %3 = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %1, <8 x float> %2)
   ret <8 x float> %3
 }
 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
 

 ; BTVER2-LABEL: test_movmskpd:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vmovmskpd %ymm0, %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_movmskpd:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vmovmskpd %ymm0, %eax # sched: [1:1.00]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %a0)
   ret i32 %1
 }
 declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) nounwind readnone
 
 define i32 @test_movmskps(<8 x float> %a0) {
 ; GENERIC-LABEL: test_movmskps:

 ; BTVER2-LABEL: test_movmskps:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vmovmskps %ymm0, %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_movmskps:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vmovmskps %ymm0, %eax # sched: [1:1.00]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %a0)
   ret i32 %1
 }
 declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone
 
 define void @test_movntdq(<4 x i64> %a0, <4 x i64> *%a1) {
 ; GENERIC-LABEL: test_movntdq:

 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_movntdq:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vmovntdq %ymm0, (%rdi) # sched: [1:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "vmovntdq $0, $1", "x,*m"(<4 x i64> %a0, <4 x i64> *%a1)
   ret void
 }
 
 define <4 x double> @test_movntpd(<4 x double> %a0, <4 x double> *%a1) {
 ; GENERIC-LABEL: test_movntpd:
 ; GENERIC:       # %bb.0:

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [1:0.50]
 ; BTVER2-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [6:1.00]
 ; BTVER2-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_perm2f128:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [100:?]
-; ZNVER1-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [100:?]
+; ZNVER1-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [100:0.25]
+; ZNVER1-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [100:0.25]
 ; ZNVER1-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
   %2 = load <4 x double>, <4 x double> *%a2, align 32
   %3 = shufflevector <4 x double> %a0, <4 x double> %2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
   %4 = fadd <4 x double> %1, %3
   ret <4 x double> %4
 }

 ;
 ; ZNVER1-LABEL: test_testpd_ymm:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    xorl %eax, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    vtestpd %ymm1, %ymm0 # sched: [1:0.25]
 ; ZNVER1-NEXT:    setb %al # sched: [1:0.25]
 ; ZNVER1-NEXT:    vtestpd (%rdi), %ymm0 # sched: [8:0.50]
 ; ZNVER1-NEXT:    adcl $0, %eax # sched: [1:0.25]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %a0, <4 x double> %a1)
   %2 = load <4 x double>, <4 x double> *%a2, align 32
   %3 = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %a0, <4 x double> %2)
   %4 = add i32 %1, %3
   ret i32 %4
 }
 declare i32 @llvm.x86.avx.vtestc.pd.256(<4 x double>, <4 x double>) nounwind readnone

 ;
 ; ZNVER1-LABEL: test_testps_ymm:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    xorl %eax, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    vtestps %ymm1, %ymm0 # sched: [1:0.25]
 ; ZNVER1-NEXT:    setb %al # sched: [1:0.25]
 ; ZNVER1-NEXT:    vtestps (%rdi), %ymm0 # sched: [8:0.50]
 ; ZNVER1-NEXT:    adcl $0, %eax # sched: [1:0.25]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %a0, <8 x float> %a1)
   %2 = load <8 x float>, <8 x float> *%a2, align 32
   %3 = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %a0, <8 x float> %2)
   %4 = add i32 %1, %3
   ret i32 %4
 }
 declare i32 @llvm.x86.avx.vtestc.ps.256(<8 x float>, <8 x float>) nounwind readnone

 ;
 ; SKX-LABEL: test_zeroall:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vzeroall # sched: [16:4.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_zeroall:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vzeroall # sched: [90:?]
+; BTVER2-NEXT:    vzeroall # sched: [90:36.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_zeroall:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vzeroall # sched: [100:?]
+; ZNVER1-NEXT:    vzeroall # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void @llvm.x86.avx.vzeroall()
   ret void
 }
 declare void @llvm.x86.avx.vzeroall() nounwind
 
 define void @test_zeroupper() {
 ; GENERIC-LABEL: test_zeroupper:

 ;
 ; SKX-LABEL: test_zeroupper:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_zeroupper:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vzeroupper # sched: [46:?]
+; BTVER2-NEXT:    vzeroupper # sched: [46:18.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_zeroupper:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void @llvm.x86.avx.vzeroupper()
   ret void
 }
 declare void @llvm.x86.avx.vzeroupper() nounwind
 
 !0 = !{i32 1}

llvm/trunk/test/CodeGen/X86/avx2-schedule.ll

 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_extracti128:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vpaddd %ymm1, %ymm0, %ymm2 # sched: [1:0.25]
 ; ZNVER1-NEXT:    vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.25]
 ; ZNVER1-NEXT:    vextracti128 $1, %ymm0, %xmm0 # sched: [2:0.25]
 ; ZNVER1-NEXT:    vextracti128 $1, %ymm2, (%rdi) # sched: [1:0.50]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = add <8 x i32> %a0, %a1
   %2 = sub <8 x i32> %a0, %a1
   %3 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %4 = shufflevector <8 x i32> %2, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   store <4 x i32> %3, <4 x i32> *%a2
   ret <4 x i32> %4
 }

 ;
 ; SKX-LABEL: test_gatherdpd:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherdpd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0, i8* %a1, <4 x i32> %a2, <2 x double> %a3, i8 2)
   ret <2 x double> %1
 }
 declare <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double>, i8*, <4 x i32>, <2 x double>, i8) nounwind readonly
 
 define <4 x double> @test_gatherdpd_ymm(<4 x double> %a0, i8* %a1, <4 x i32> %a2, <4 x double> %a3) {
 ; GENERIC-LABEL: test_gatherdpd_ymm:

 ;
 ; SKX-LABEL: test_gatherdpd_ymm:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [25:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherdpd_ymm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> %a0, i8* %a1, <4 x i32> %a2, <4 x double> %a3, i8 8)
   ret <4 x double> %1
 }
 declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, i8*, <4 x i32>, <4 x double>, i8) nounwind readonly
 
 define <4 x float> @test_gatherdps(<4 x float> %a0, i8* %a1, <4 x i32> %a2, <4 x float> %a3) {
 ; GENERIC-LABEL: test_gatherdps:

 ;
 ; SKX-LABEL: test_gatherdps:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherdps:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0, i8* %a1, <4 x i32> %a2, <4 x float> %a3, i8 2)
   ret <4 x float> %1
 }
 declare <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float>, i8*, <4 x i32>, <4 x float>, i8) nounwind readonly
 
 define <8 x float> @test_gatherdps_ymm(<8 x float> %a0, i8* %a1, <8 x i32> %a2, <8 x float> %a3) {
 ; GENERIC-LABEL: test_gatherdps_ymm:

 ;
 ; SKX-LABEL: test_gatherdps_ymm:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [25:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherdps_ymm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0, i8* %a1, <8 x i32> %a2, <8 x float> %a3, i8 4)
   ret <8 x float> %1
 }
 declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, i8*, <8 x i32>, <8 x float>, i8) nounwind readonly
 
 define <2 x double> @test_gatherqpd(<2 x double> %a0, i8* %a1, <2 x i64> %a2, <2 x double> %a3) {
 ; GENERIC-LABEL: test_gatherqpd:

 ;
 ; SKX-LABEL: test_gatherqpd:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherqpd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0, i8* %a1, <2 x i64> %a2, <2 x double> %a3, i8 2)
   ret <2 x double> %1
 }
 declare <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double>, i8*, <2 x i64>, <2 x double>, i8) nounwind readonly
 
 define <4 x double> @test_gatherqpd_ymm(<4 x double> %a0, i8* %a1, <4 x i64> %a2, <4 x double> %a3) {
 ; GENERIC-LABEL: test_gatherqpd_ymm:

 ;
 ; SKX-LABEL: test_gatherqpd_ymm:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [25:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherqpd_ymm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> %a0, i8* %a1, <4 x i64> %a2, <4 x double> %a3, i8 8)
   ret <4 x double> %1
 }
 declare <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double>, i8*, <4 x i64>, <4 x double>, i8) nounwind readonly
 
 define <4 x float> @test_gatherqps(<4 x float> %a0, i8* %a1, <2 x i64> %a2, <4 x float> %a3) {
 ; GENERIC-LABEL: test_gatherqps:

 ;
 ; SKX-LABEL: test_gatherqps:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherqps:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> %a0, i8* %a1, <2 x i64> %a2, <4 x float> %a3, i8 2)
   ret <4 x float> %1
 }
 declare <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float>, i8*, <2 x i64>, <4 x float>, i8) nounwind readonly
 
 define <4 x float> @test_gatherqps_ymm(<4 x float> %a0, i8* %a1, <4 x i64> %a2, <4 x float> %a3) {
 ; GENERIC-LABEL: test_gatherqps_ymm:

 ; SKX-LABEL: test_gatherqps_ymm:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [25:1.00]
 ; SKX-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherqps_ymm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> %a0, i8* %a1, <4 x i64> %a2, <4 x float> %a3, i8 4)
   ret <4 x float> %1
 }
 declare <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float>, i8*, <4 x i64>, <4 x float>, i8) nounwind readonly
 
 define <8 x i32> @test_inserti128(<8 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
 ; GENERIC-LABEL: test_inserti128:

 ; SKX-LABEL: test_mpsadbw:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [4:2.00]
 ; SKX-NEXT:    vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [11:2.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_mpsadbw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i8 7)
   %2 = bitcast <16 x i16> %1 to <32 x i8>
   %3 = load <32 x i8>, <32 x i8> *%a2, align 32
   %4 = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %2, <32 x i8> %3, i8 7)
   ret <16 x i16> %4
 }
 declare <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8>, <32 x i8>, i8) nounwind readnone

 ;
 ; SKX-LABEL: test_pgatherdd:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherdd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> %a0, i8* %a1, <4 x i32> %a2, <4 x i32> %a3, i8 2)
   ret <4 x i32> %1
 }
 declare <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32>, i8*, <4 x i32>, <4 x i32>, i8) nounwind readonly
 
 define <8 x i32> @test_pgatherdd_ymm(<8 x i32> %a0, i8* %a1, <8 x i32> %a2, <8 x i32> %a3) {
 ; GENERIC-LABEL: test_pgatherdd_ymm:

 ;
 ; SKX-LABEL: test_pgatherdd_ymm:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [25:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherdd_ymm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> %a0, i8* %a1, <8 x i32> %a2, <8 x i32> %a3, i8 2)
   ret <8 x i32> %1
 }
 declare <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32>, i8*, <8 x i32>, <8 x i32>, i8) nounwind readonly
 
 define <2 x i64> @test_pgatherdq(<2 x i64> %a0, i8* %a1, <4 x i32> %a2, <2 x i64> %a3) {
 ; GENERIC-LABEL: test_pgatherdq:

 ;
 ; SKX-LABEL: test_pgatherdq:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherdq:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> %a0, i8* %a1, <4 x i32> %a2, <2 x i64> %a3, i8 2)
   ret <2 x i64> %1
 }
 declare <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64>, i8*, <4 x i32>, <2 x i64>, i8) nounwind readonly
 
 define <4 x i64> @test_pgatherdq_ymm(<4 x i64> %a0, i8* %a1, <4 x i32> %a2, <4 x i64> %a3) {
 ; GENERIC-LABEL: test_pgatherdq_ymm:

 ;
 ; SKX-LABEL: test_pgatherdq_ymm:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [25:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherdq_ymm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> %a0, i8* %a1, <4 x i32> %a2, <4 x i64> %a3, i8 2)
   ret <4 x i64> %1
 }
 declare <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64>, i8*, <4 x i32>, <4 x i64>, i8) nounwind readonly
 
 define <4 x i32> @test_pgatherqd(<4 x i32> %a0, i8* %a1, <2 x i64> %a2, <4 x i32> %a3) {
 ; GENERIC-LABEL: test_pgatherqd:

 ;
 ; SKX-LABEL: test_pgatherqd:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherqd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> %a0, i8* %a1, <2 x i64> %a2, <4 x i32> %a3, i8 2)
   ret <4 x i32> %1
 }
 declare <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32>, i8*, <2 x i64>, <4 x i32>, i8) nounwind readonly
 
 define <4 x i32> @test_pgatherqd_ymm(<4 x i32> %a0, i8* %a1, <4 x i64> %a2, <4 x i32> %a3) {
 ; GENERIC-LABEL: test_pgatherqd_ymm:

 ; SKX-LABEL: test_pgatherqd_ymm:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [25:1.00]
 ; SKX-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherqd_ymm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> %a0, i8* %a1, <4 x i64> %a2, <4 x i32> %a3, i8 2)
   ret <4 x i32> %1
 }
 declare <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32>, i8*, <4 x i64>, <4 x i32>, i8) nounwind readonly
 
 define <2 x i64> @test_pgatherqq(<2 x i64> %a0, i8 *%a1, <2 x i64> %a2, <2 x i64> %a3) {
 ; GENERIC-LABEL: test_pgatherqq:

 ;
 ; SKX-LABEL: test_pgatherqq:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherqq:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0, i8* %a1, <2 x i64> %a2, <2 x i64> %a3, i8 2)
   ret <2 x i64> %1
 }
 declare <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64>, i8*, <2 x i64>, <2 x i64>, i8) nounwind readonly
 
 define <4 x i64> @test_pgatherqq_ymm(<4 x i64> %a0, i8 *%a1, <4 x i64> %a2, <4 x i64> %a3) {
 ; GENERIC-LABEL: test_pgatherqq_ymm:

 ;
 ; SKX-LABEL: test_pgatherqq_ymm:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [25:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherqq_ymm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> %a0, i8* %a1, <4 x i64> %a2, <4 x i64> %a3, i8 2)
   ret <4 x i64> %1
 }
 declare <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64>, i8*, <4 x i64>, <4 x i64>, i8) nounwind readonly
 
 define <8 x i32> @test_phaddd(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> *%a2) {
 ; GENERIC-LABEL: test_phaddd:

 ; SKX-LABEL: test_phaddd:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vphaddd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; SKX-NEXT:    vphaddd (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_phaddd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphaddd %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphaddd (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphaddd %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphaddd (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %a0, <8 x i32> %a1)
   %2 = load <8 x i32>, <8 x i32> *%a2, align 32
   %3 = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %1, <8 x i32> %2)
   ret <8 x i32> %3
 }
 declare <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32>, <8 x i32>) nounwind readnone
 

 ; SKX-LABEL: test_phaddsw:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vphaddsw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; SKX-NEXT:    vphaddsw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_phaddsw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphaddsw %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphaddsw (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphaddsw %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphaddsw (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %a0, <16 x i16> %a1)
   %2 = load <16 x i16>, <16 x i16> *%a2, align 32
   %3 = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %1, <16 x i16> %2)
   ret <16 x i16> %3
 }
 declare <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16>, <16 x i16>) nounwind readnone
 

 ; SKX-LABEL: test_phaddw:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vphaddw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; SKX-NEXT:    vphaddw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_phaddw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphaddw %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphaddw (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphaddw %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphaddw (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %a0, <16 x i16> %a1)
   %2 = load <16 x i16>, <16 x i16> *%a2, align 32
   %3 = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %1, <16 x i16> %2)
   ret <16 x i16> %3
 }
 declare <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16>, <16 x i16>) nounwind readnone
 

 ; SKX-LABEL: test_phsubd:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vphsubd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; SKX-NEXT:    vphsubd (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_phsubd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphsubd %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphsubd (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphsubd %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphsubd (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %a0, <8 x i32> %a1)
   %2 = load <8 x i32>, <8 x i32> *%a2, align 32
   %3 = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %1, <8 x i32> %2)
   ret <8 x i32> %3
 }
 declare <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32>, <8 x i32>) nounwind readnone
 

 ; SKX-LABEL: test_phsubsw:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vphsubsw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; SKX-NEXT:    vphsubsw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_phsubsw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphsubsw %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphsubsw (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphsubsw %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphsubsw (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %a0, <16 x i16> %a1)
   %2 = load <16 x i16>, <16 x i16> *%a2, align 32
   %3 = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %1, <16 x i16> %2)
   ret <16 x i16> %3
 }
 declare <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16>, <16 x i16>) nounwind readnone
 

 ; SKX-LABEL: test_phsubw:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vphsubw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
 ; SKX-NEXT:    vphsubw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_phsubw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphsubw %ymm1, %ymm0, %ymm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphsubw (%rdi), %ymm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphsubw %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphsubw (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %a0, <16 x i16> %a1)
   %2 = load <16 x i16>, <16 x i16> *%a2, align 32
   %3 = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %1, <16 x i16> %2)
   ret <16 x i16> %3
 }
 declare <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16>, <16 x i16>) nounwind readnone
 

 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
 ; SKX-NEXT:    vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
 ; SKX-NEXT:    vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pmaskmovd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [100:?]
-; ZNVER1-NEXT:    vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [100:?]
+; ZNVER1-NEXT:    vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [100:0.25]
+; ZNVER1-NEXT:    vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %a0, <4 x i32> %a1)
   call void @llvm.x86.avx2.maskstore.d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2)
   ret <4 x i32> %1
 }
 declare <4 x i32> @llvm.x86.avx2.maskload.d(i8*, <4 x i32>) nounwind readonly
 declare void @llvm.x86.avx2.maskstore.d(i8*, <4 x i32>, <4 x i32>) nounwind

 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
 ; SKX-NEXT:    vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
 ; SKX-NEXT:    vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pmaskmovd_ymm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [100:?]
-; ZNVER1-NEXT:    vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [100:?]
+; ZNVER1-NEXT:    vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [100:0.25]
+; ZNVER1-NEXT:    vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    vmovdqa %ymm2, %ymm0 # sched: [2:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %a0, <8 x i32> %a1)
   call void @llvm.x86.avx2.maskstore.d.256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2)
   ret <8 x i32> %1
 }
 declare <8 x i32> @llvm.x86.avx2.maskload.d.256(i8*, <8 x i32>) nounwind readonly
 declare void @llvm.x86.avx2.maskstore.d.256(i8*, <8 x i32>, <8 x i32>) nounwind

 ; SKX-NEXT:    vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
 ; SKX-NEXT:    vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
 ; SKX-NEXT:    vmovdqa %xmm2, %xmm0 # sched: [1:0.33]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pmaskmovq:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [8:1.00]
-; ZNVER1-NEXT:    vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [100:?]
+; ZNVER1-NEXT:    vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %a0, <2 x i64> %a1)
   call void @llvm.x86.avx2.maskstore.q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2)
   ret <2 x i64> %1
 }
 declare <2 x i64> @llvm.x86.avx2.maskload.q(i8*, <2 x i64>) nounwind readonly
 declare void @llvm.x86.avx2.maskstore.q(i8*, <2 x i64>, <2 x i64>) nounwind

 ; SKX-NEXT:    vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
 ; SKX-NEXT:    vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
 ; SKX-NEXT:    vmovdqa %ymm2, %ymm0 # sched: [1:0.33]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pmaskmovq_ymm:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [9:1.50]
-; ZNVER1-NEXT:    vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [100:?]
+; ZNVER1-NEXT:    vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    vmovdqa %ymm2, %ymm0 # sched: [2:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %a0, <4 x i64> %a1)
   call void @llvm.x86.avx2.maskstore.q.256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2)
   ret <4 x i64> %1
 }
 declare <4 x i64> @llvm.x86.avx2.maskload.q.256(i8*, <4 x i64>) nounwind readonly
 declare void @llvm.x86.avx2.maskstore.q.256(i8*, <4 x i64>, <4 x i64>) nounwind

 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpmovmskb %ymm0, %eax # sched: [2:1.00]
 ; SKX-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pmovmskb:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vpmovmskb %ymm0, %eax # sched: [2:2.00]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> %a0)
   ret i32 %1
 }
 declare i32 @llvm.x86.avx2.pmovmskb(<32 x i8>) nounwind readnone
 
 define <8 x i32> @test_pmovsxbd(<16 x i8> %a0, <16 x i8> *%a1) {
 ; GENERIC-LABEL: test_pmovsxbd:

llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll

 ; KNL:       # %bb.0:
 ; KNL-NEXT:    pdepl (%rdx), %edi, %ecx # sched: [8:1.00]
 ; KNL-NEXT:    pdepl %esi, %edi, %eax # sched: [3:1.00]
 ; KNL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
 ; KNL-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pdep_i32:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    pdepl (%rdx), %edi, %ecx # sched: [100:?]
-; ZNVER1-NEXT:    pdepl %esi, %edi, %eax # sched: [100:?]
+; ZNVER1-NEXT:    pdepl (%rdx), %edi, %ecx # sched: [100:0.25]
+; ZNVER1-NEXT:    pdepl %esi, %edi, %eax # sched: [100:0.25]
 ; ZNVER1-NEXT:    addl %ecx, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = load i32, i32 *%a2
   %2 = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a0, i32 %1)
   %3 = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a0, i32 %a1)
   %4 = add i32 %2, %3
   ret i32 %4
 }

 ; KNL:       # %bb.0:
 ; KNL-NEXT:    pdepq (%rdx), %rdi, %rcx # sched: [8:1.00]
 ; KNL-NEXT:    pdepq %rsi, %rdi, %rax # sched: [3:1.00]
 ; KNL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
 ; KNL-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pdep_i64:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    pdepq (%rdx), %rdi, %rcx # sched: [100:?]
-; ZNVER1-NEXT:    pdepq %rsi, %rdi, %rax # sched: [100:?]
+; ZNVER1-NEXT:    pdepq (%rdx), %rdi, %rcx # sched: [100:0.25]
+; ZNVER1-NEXT:    pdepq %rsi, %rdi, %rax # sched: [100:0.25]
 ; ZNVER1-NEXT:    addq %rcx, %rax # sched: [1:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = load i64, i64 *%a2
   %2 = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a0, i64 %1)
   %3 = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a0, i64 %a1)
   %4 = add i64 %2, %3
   ret i64 %4
 }

 ; KNL:       # %bb.0:
 ; KNL-NEXT:    pextl (%rdx), %edi, %ecx # sched: [8:1.00]
 ; KNL-NEXT:    pextl %esi, %edi, %eax # sched: [3:1.00]
 ; KNL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
 ; KNL-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pext_i32:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    pextl (%rdx), %edi, %ecx # sched: [100:?]
-; ZNVER1-NEXT:    pextl %esi, %edi, %eax # sched: [100:?]
+; ZNVER1-NEXT:    pextl (%rdx), %edi, %ecx # sched: [100:0.25]
+; ZNVER1-NEXT:    pextl %esi, %edi, %eax # sched: [100:0.25]
 ; ZNVER1-NEXT:    addl %ecx, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = load i32, i32 *%a2
   %2 = tail call i32 @llvm.x86.bmi.pext.32(i32 %a0, i32 %1)
   %3 = tail call i32 @llvm.x86.bmi.pext.32(i32 %a0, i32 %a1)
   %4 = add i32 %2, %3
   ret i32 %4
 }

 ; KNL:       # %bb.0:
 ; KNL-NEXT:    pextq (%rdx), %rdi, %rcx # sched: [8:1.00]
 ; KNL-NEXT:    pextq %rsi, %rdi, %rax # sched: [3:1.00]
 ; KNL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
 ; KNL-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pext_i64:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    pextq (%rdx), %rdi, %rcx # sched: [100:?]
-; ZNVER1-NEXT:    pextq %rsi, %rdi, %rax # sched: [100:?]
+; ZNVER1-NEXT:    pextq (%rdx), %rdi, %rcx # sched: [100:0.25]
+; ZNVER1-NEXT:    pextq %rsi, %rdi, %rax # sched: [100:0.25]
 ; ZNVER1-NEXT:    addq %rcx, %rax # sched: [1:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = load i64, i64 *%a2
   %2 = tail call i64 @llvm.x86.bmi.pext.64(i64 %a0, i64 %1)
   %3 = tail call i64 @llvm.x86.bmi.pext.64(i64 %a0, i64 %a1)
   %4 = add i64 %2, %3
   ret i64 %4
 }

llvm/trunk/test/CodeGen/X86/clzero-schedule.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+clzero | FileCheck %s --check-prefix=GENERIC
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=ZNVER1
 
 define void @test_clzero(i8* %p) {
 ; GENERIC-LABEL: test_clzero:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    leaq (%rdi), %rax # sched: [1:0.50]
 ; GENERIC-NEXT:    clzero # sched: [100:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; ZNVER1-LABEL: test_clzero:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    leaq (%rdi), %rax # sched: [1:0.25]
-; ZNVER1-NEXT:    clzero # sched: [100:?]
+; ZNVER1-NEXT:    clzero # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void @llvm.x86.clzero(i8* %p)
   ret void
 }
 declare void @llvm.x86.clzero(i8*)

llvm/trunk/test/CodeGen/X86/f16c-schedule.ll

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [8:1.00]
 ; BTVER2-NEXT:    vcvtph2ps %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_vcvtph2ps_128:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [100:?]
-; ZNVER1-NEXT:    vcvtph2ps %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [100:0.25]
+; ZNVER1-NEXT:    vcvtph2ps %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = load <8 x i16>, <8 x i16> *%a1
   %2 = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %1)
   %3 = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0)
   %4 = fadd <4 x float> %2, %3
   ret <4 x float> %4
 }

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [8:2.00]
 ; BTVER2-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_vcvtph2ps_256:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [100:?]
-; ZNVER1-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [100:?]
+; ZNVER1-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [100:0.25]
+; ZNVER1-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = load <8 x i16>, <8 x i16> *%a1
   %2 = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %1)
   %3 = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0)
   %4 = fadd <8 x float> %2, %3
   ret <8 x float> %4
 }

 ; BTVER2-LABEL: test_vcvtps2ph_128:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vcvtps2ph $0, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_vcvtps2ph_128:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vcvtps2ph $0, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [100:?]
+; ZNVER1-NEXT:    vcvtps2ph $0, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0)
   %2 = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a1, i32 0)
   %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   store <4 x i16> %3, <4 x i16> *%a2
   ret <8 x i16> %1
 }
 declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32)

 ; BTVER2-LABEL: test_vcvtps2ph_256:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [6:2.00]
 ; BTVER2-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [7:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_vcvtps2ph_256:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0)
   %2 = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a1, i32 0)
   store <8 x i16> %2, <8 x i16> *%a2
   ret <8 x i16> %1
 }
 declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32)

llvm/trunk/test/CodeGen/X86/fma-schedule.ll

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfmadd132pd {{.*#+}} ymm0 = (ymm0 * ymm2) + ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmadd231pd {{.*#+}} ymm0 = (ymm1 * ymm2) + ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmadd132pd {{.*#+}} ymm0 = (ymm0 * mem) + ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmadd231pd {{.*#+}} ymm0 = (ymm1 * mem) + ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfmadd132pd $2, $1, $0 \0A\09 vfmadd213pd $2, $1, $0 \0A\09 vfmadd231pd $2, $1, $0 \0A\09 vfmadd132pd $3, $1, $0 \0A\09 vfmadd213pd $3, $1, $0 \0A\09 vfmadd231pd $3, $1, $0", "x,x,x,*m"(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, <4 x double> *%a3) nounwind
   ret void
 }
 
 define void @test_vfmaddps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> *%a3) optsize {
 ; GENERIC-LABEL: test_vfmaddps_128:
 ; GENERIC:       # %bb.0:

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfmadd132ps {{.*#+}} ymm0 = (ymm0 * ymm2) + ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmadd231ps {{.*#+}} ymm0 = (ymm1 * ymm2) + ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmadd132ps {{.*#+}} ymm0 = (ymm0 * mem) + ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) + mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmadd231ps {{.*#+}} ymm0 = (ymm1 * mem) + ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfmadd132ps $2, $1, $0 \0A\09 vfmadd213ps $2, $1, $0 \0A\09 vfmadd231ps $2, $1, $0 \0A\09 vfmadd132ps $3, $1, $0 \0A\09 vfmadd213ps $3, $1, $0 \0A\09 vfmadd231ps $3, $1, $0", "x,x,x,*m"(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, <8 x float> *%a3) nounwind
   ret void
 }
 
 define void @test_vfmaddsd_128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> *%a3) optsize {
 ; GENERIC-LABEL: test_vfmaddsd_128:
 ; GENERIC:       # %bb.0:

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfmaddsub132pd {{.*#+}} ymm0 = (ymm0 * ymm2) +/- ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmaddsub213pd {{.*#+}} ymm0 = (ymm1 * ymm0) +/- ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmaddsub231pd {{.*#+}} ymm0 = (ymm1 * ymm2) +/- ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmaddsub132pd {{.*#+}} ymm0 = (ymm0 * mem) +/- ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmaddsub213pd {{.*#+}} ymm0 = (ymm1 * ymm0) +/- mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmaddsub231pd {{.*#+}} ymm0 = (ymm1 * mem) +/- ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfmaddsub132pd $2, $1, $0 \0A\09 vfmaddsub213pd $2, $1, $0 \0A\09 vfmaddsub231pd $2, $1, $0 \0A\09 vfmaddsub132pd $3, $1, $0 \0A\09 vfmaddsub213pd $3, $1, $0 \0A\09 vfmaddsub231pd $3, $1, $0", "x,x,x,*m"(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, <4 x double> *%a3) nounwind
   ret void
 }
 
 define void @test_vfmaddsubps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> *%a3) optsize {
 ; GENERIC-LABEL: test_vfmaddsubps_128:
 ; GENERIC:       # %bb.0:

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfmaddsub132ps {{.*#+}} ymm0 = (ymm0 * ymm2) +/- ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmaddsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) +/- ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmaddsub231ps {{.*#+}} ymm0 = (ymm1 * ymm2) +/- ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmaddsub132ps {{.*#+}} ymm0 = (ymm0 * mem) +/- ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmaddsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) +/- mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmaddsub231ps {{.*#+}} ymm0 = (ymm1 * mem) +/- ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfmaddsub132ps $2, $1, $0 \0A\09 vfmaddsub213ps $2, $1, $0 \0A\09 vfmaddsub231ps $2, $1, $0 \0A\09 vfmaddsub132ps $3, $1, $0 \0A\09 vfmaddsub213ps $3, $1, $0 \0A\09 vfmaddsub231ps $3, $1, $0", "x,x,x,*m"(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, <8 x float> *%a3) nounwind
   ret void
 }
 
 ;
 ; VFMSUBADD
 ;

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfmsubadd132pd {{.*#+}} ymm0 = (ymm0 * ymm2) -/+ ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsubadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsubadd231pd {{.*#+}} ymm0 = (ymm1 * ymm2) -/+ ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsubadd132pd {{.*#+}} ymm0 = (ymm0 * mem) -/+ ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmsubadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmsubadd231pd {{.*#+}} ymm0 = (ymm1 * mem) -/+ ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfmsubadd132pd $2, $1, $0 \0A\09 vfmsubadd213pd $2, $1, $0 \0A\09 vfmsubadd231pd $2, $1, $0 \0A\09 vfmsubadd132pd $3, $1, $0 \0A\09 vfmsubadd213pd $3, $1, $0 \0A\09 vfmsubadd231pd $3, $1, $0", "x,x,x,*m"(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, <4 x double> *%a3) nounwind
   ret void
 }
 
 define void @test_vfmsubaddps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> *%a3) optsize {
 ; GENERIC-LABEL: test_vfmsubaddps_128:
 ; GENERIC:       # %bb.0:

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfmsubadd132ps {{.*#+}} ymm0 = (ymm0 * ymm2) -/+ ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsubadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsubadd231ps {{.*#+}} ymm0 = (ymm1 * ymm2) -/+ ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsubadd132ps {{.*#+}} ymm0 = (ymm0 * mem) -/+ ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmsubadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmsubadd231ps {{.*#+}} ymm0 = (ymm1 * mem) -/+ ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfmsubadd132ps $2, $1, $0 \0A\09 vfmsubadd213ps $2, $1, $0 \0A\09 vfmsubadd231ps $2, $1, $0 \0A\09 vfmsubadd132ps $3, $1, $0 \0A\09 vfmsubadd213ps $3, $1, $0 \0A\09 vfmsubadd231ps $3, $1, $0", "x,x,x,*m"(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, <8 x float> *%a3) nounwind
   ret void
 }
 
 ;
 ; VFMSUB
 ;

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfmsub132pd {{.*#+}} ymm0 = (ymm0 * ymm2) - ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsub213pd {{.*#+}} ymm0 = (ymm1 * ymm0) - ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsub231pd {{.*#+}} ymm0 = (ymm1 * ymm2) - ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsub132pd {{.*#+}} ymm0 = (ymm0 * mem) - ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmsub213pd {{.*#+}} ymm0 = (ymm1 * ymm0) - mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmsub231pd {{.*#+}} ymm0 = (ymm1 * mem) - ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfmsub132pd $2, $1, $0 \0A\09 vfmsub213pd $2, $1, $0 \0A\09 vfmsub231pd $2, $1, $0 \0A\09 vfmsub132pd $3, $1, $0 \0A\09 vfmsub213pd $3, $1, $0 \0A\09 vfmsub231pd $3, $1, $0", "x,x,x,*m"(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, <4 x double> *%a3) nounwind
   ret void
 }
 
 define void @test_vfmsubps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> *%a3) optsize {
 ; GENERIC-LABEL: test_vfmsubps_128:
 ; GENERIC:       # %bb.0:

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfmsub132ps {{.*#+}} ymm0 = (ymm0 * ymm2) - ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) - ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsub231ps {{.*#+}} ymm0 = (ymm1 * ymm2) - ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfmsub132ps {{.*#+}} ymm0 = (ymm0 * mem) - ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) - mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfmsub231ps {{.*#+}} ymm0 = (ymm1 * mem) - ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfmsub132ps $2, $1, $0 \0A\09 vfmsub213ps $2, $1, $0 \0A\09 vfmsub231ps $2, $1, $0 \0A\09 vfmsub132ps $3, $1, $0 \0A\09 vfmsub213ps $3, $1, $0 \0A\09 vfmsub231ps $3, $1, $0", "x,x,x,*m"(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, <8 x float> *%a3) nounwind
   ret void
 }
 
 define void @test_vfmsubsd_128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> *%a3) optsize {
 ; GENERIC-LABEL: test_vfmsubsd_128:
 ; GENERIC:       # %bb.0:

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfnmadd132pd {{.*#+}} ymm0 = -(ymm0 * ymm2) + ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmadd213pd {{.*#+}} ymm0 = -(ymm1 * ymm0) + ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmadd231pd {{.*#+}} ymm0 = -(ymm1 * ymm2) + ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmadd132pd {{.*#+}} ymm0 = -(ymm0 * mem) + ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfnmadd213pd {{.*#+}} ymm0 = -(ymm1 * ymm0) + mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfnmadd231pd {{.*#+}} ymm0 = -(ymm1 * mem) + ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfnmadd132pd $2, $1, $0 \0A\09 vfnmadd213pd $2, $1, $0 \0A\09 vfnmadd231pd $2, $1, $0 \0A\09 vfnmadd132pd $3, $1, $0 \0A\09 vfnmadd213pd $3, $1, $0 \0A\09 vfnmadd231pd $3, $1, $0", "x,x,x,*m"(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, <4 x double> *%a3) nounwind
   ret void
 }
 
 define void @test_vfnmaddps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> *%a3) optsize {
 ; GENERIC-LABEL: test_vfnmaddps_128:
 ; GENERIC:       # %bb.0:

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfnmadd132ps {{.*#+}} ymm0 = -(ymm0 * ymm2) + ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmadd213ps {{.*#+}} ymm0 = -(ymm1 * ymm0) + ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmadd231ps {{.*#+}} ymm0 = -(ymm1 * ymm2) + ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmadd132ps {{.*#+}} ymm0 = -(ymm0 * mem) + ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfnmadd213ps {{.*#+}} ymm0 = -(ymm1 * ymm0) + mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfnmadd231ps {{.*#+}} ymm0 = -(ymm1 * mem) + ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfnmadd132ps $2, $1, $0 \0A\09 vfnmadd213ps $2, $1, $0 \0A\09 vfnmadd231ps $2, $1, $0 \0A\09 vfnmadd132ps $3, $1, $0 \0A\09 vfnmadd213ps $3, $1, $0 \0A\09 vfnmadd231ps $3, $1, $0", "x,x,x,*m"(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, <8 x float> *%a3) nounwind
   ret void
 }
 
 define void @test_vfnmaddsd_128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> *%a3) optsize {
 ; GENERIC-LABEL: test_vfnmaddsd_128:
 ; GENERIC:       # %bb.0:

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfnmsub132pd {{.*#+}} ymm0 = -(ymm0 * ymm2) - ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmsub213pd {{.*#+}} ymm0 = -(ymm1 * ymm0) - ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmsub231pd {{.*#+}} ymm0 = -(ymm1 * ymm2) - ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmsub132pd {{.*#+}} ymm0 = -(ymm0 * mem) - ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfnmsub213pd {{.*#+}} ymm0 = -(ymm1 * ymm0) - mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfnmsub231pd {{.*#+}} ymm0 = -(ymm1 * mem) - ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfnmsub132pd $2, $1, $0 \0A\09 vfnmsub213pd $2, $1, $0 \0A\09 vfnmsub231pd $2, $1, $0 \0A\09 vfnmsub132pd $3, $1, $0 \0A\09 vfnmsub213pd $3, $1, $0 \0A\09 vfnmsub231pd $3, $1, $0", "x,x,x,*m"(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, <4 x double> *%a3) nounwind
   ret void
 }
 
 define void @test_vfnmsubps_128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> *%a3) optsize {
 ; GENERIC-LABEL: test_vfnmsubps_128:
 ; GENERIC:       # %bb.0:

 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    vfnmsub132ps {{.*#+}} ymm0 = -(ymm0 * ymm2) - ymm1 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmsub213ps {{.*#+}} ymm0 = -(ymm1 * ymm0) - ymm2 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmsub231ps {{.*#+}} ymm0 = -(ymm1 * ymm2) - ymm0 sched: [5:0.50]
 ; ZNVER1-NEXT:    vfnmsub132ps {{.*#+}} ymm0 = -(ymm0 * mem) - ymm1 sched: [12:0.50]
 ; ZNVER1-NEXT:    vfnmsub213ps {{.*#+}} ymm0 = -(ymm1 * ymm0) - mem sched: [12:0.50]
 ; ZNVER1-NEXT:    vfnmsub231ps {{.*#+}} ymm0 = -(ymm1 * mem) - ymm0 sched: [12:0.50]
 ; ZNVER1-NEXT:    #NO_APP
-; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
+; ZNVER1-NEXT:    vzeroupper # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "vfnmsub132ps $2, $1, $0 \0A\09 vfnmsub213ps $2, $1, $0 \0A\09 vfnmsub231ps $2, $1, $0 \0A\09 vfnmsub132ps $3, $1, $0 \0A\09 vfnmsub213ps $3, $1, $0 \0A\09 vfnmsub231ps $3, $1, $0", "x,x,x,*m"(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, <8 x float> *%a3) nounwind
   ret void
 }
 
 define void @test_vfnmsubsd_128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> *%a3) optsize {
 ; GENERIC-LABEL: test_vfnmsubsd_128:
 ; GENERIC:       # %bb.0:

llvm/trunk/test/CodeGen/X86/fsgsbase-schedule.ll

 ;
 ; BDVER-LABEL: test_x86_rdfsbase_32:
 ; BDVER:       # %bb.0:
 ; BDVER-NEXT:    rdfsbasel %eax
 ; BDVER-NEXT:    retq
 ;
 ; ZNVER1-LABEL: test_x86_rdfsbase_32:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdfsbasel %eax # sched: [100:?]
+; ZNVER1-NEXT:    rdfsbasel %eax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %res = call i32 @llvm.x86.rdfsbase.32()
   ret i32 %res
 }
 declare i32 @llvm.x86.rdfsbase.32() nounwind readnone
 
 define i32 @test_x86_rdgsbase_32() {
 ; GENERIC-LABEL: test_x86_rdgsbase_32:

 ;
 ; BDVER-LABEL: test_x86_rdgsbase_32:
 ; BDVER:       # %bb.0:
 ; BDVER-NEXT:    rdgsbasel %eax
 ; BDVER-NEXT:    retq
 ;
 ; ZNVER1-LABEL: test_x86_rdgsbase_32:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdgsbasel %eax # sched: [100:?]
+; ZNVER1-NEXT:    rdgsbasel %eax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %res = call i32 @llvm.x86.rdgsbase.32()
   ret i32 %res
 }
 declare i32 @llvm.x86.rdgsbase.32() nounwind readnone
 
 define i64 @test_x86_rdfsbase_64() {
 ; GENERIC-LABEL: test_x86_rdfsbase_64:

 ;
 ; BDVER-LABEL: test_x86_rdfsbase_64:
 ; BDVER:       # %bb.0:
 ; BDVER-NEXT:    rdfsbaseq %rax
 ; BDVER-NEXT:    retq
 ;
 ; ZNVER1-LABEL: test_x86_rdfsbase_64:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdfsbaseq %rax # sched: [100:?]
+; ZNVER1-NEXT:    rdfsbaseq %rax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %res = call i64 @llvm.x86.rdfsbase.64()
   ret i64 %res
 }
 declare i64 @llvm.x86.rdfsbase.64() nounwind readnone
 
 define i64 @test_x86_rdgsbase_64() {
 ; GENERIC-LABEL: test_x86_rdgsbase_64:

 ;
 ; BDVER-LABEL: test_x86_rdgsbase_64:
 ; BDVER:       # %bb.0:
 ; BDVER-NEXT:    rdgsbaseq %rax
 ; BDVER-NEXT:    retq
 ;
 ; ZNVER1-LABEL: test_x86_rdgsbase_64:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdgsbaseq %rax # sched: [100:?]
+; ZNVER1-NEXT:    rdgsbaseq %rax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %res = call i64 @llvm.x86.rdgsbase.64()
   ret i64 %res
 }
 declare i64 @llvm.x86.rdgsbase.64() nounwind readnone
 
 define void @test_x86_wrfsbase_32(i32 %x) {
 ; GENERIC-LABEL: test_x86_wrfsbase_32:

 ;
 ; BDVER-LABEL: test_x86_wrfsbase_32:
 ; BDVER:       # %bb.0:
 ; BDVER-NEXT:    wrfsbasel %edi
 ; BDVER-NEXT:    retq
 ;
 ; ZNVER1-LABEL: test_x86_wrfsbase_32:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    wrfsbasel %edi # sched: [100:?]
+; ZNVER1-NEXT:    wrfsbasel %edi # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void @llvm.x86.wrfsbase.32(i32 %x)
   ret void
 }
 declare void @llvm.x86.wrfsbase.32(i32) nounwind readnone
 
 define void @test_x86_wrgsbase_32(i32 %x) {
 ; GENERIC-LABEL: test_x86_wrgsbase_32:

 ;
 ; BDVER-LABEL: test_x86_wrgsbase_32:
 ; BDVER:       # %bb.0:
 ; BDVER-NEXT:    wrgsbasel %edi
 ; BDVER-NEXT:    retq
 ;
 ; ZNVER1-LABEL: test_x86_wrgsbase_32:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    wrgsbasel %edi # sched: [100:?]
+; ZNVER1-NEXT:    wrgsbasel %edi # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void @llvm.x86.wrgsbase.32(i32 %x)
   ret void
 }
 declare void @llvm.x86.wrgsbase.32(i32) nounwind readnone
 
 define void @test_x86_wrfsbase_64(i64 %x) {
 ; GENERIC-LABEL: test_x86_wrfsbase_64:

 ;
 ; BDVER-LABEL: test_x86_wrfsbase_64:
 ; BDVER:       # %bb.0:
 ; BDVER-NEXT:    wrfsbaseq %rdi
 ; BDVER-NEXT:    retq
 ;
 ; ZNVER1-LABEL: test_x86_wrfsbase_64:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    wrfsbaseq %rdi # sched: [100:?]
+; ZNVER1-NEXT:    wrfsbaseq %rdi # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void @llvm.x86.wrfsbase.64(i64 %x)
   ret void
 }
 declare void @llvm.x86.wrfsbase.64(i64) nounwind readnone
 
 define void @test_x86_wrgsbase_64(i64 %x) {
 ; GENERIC-LABEL: test_x86_wrgsbase_64:

 ;
 ; BDVER-LABEL: test_x86_wrgsbase_64:
 ; BDVER:       # %bb.0:
 ; BDVER-NEXT:    wrgsbaseq %rdi
 ; BDVER-NEXT:    retq
 ;
 ; ZNVER1-LABEL: test_x86_wrgsbase_64:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    wrgsbaseq %rdi # sched: [100:?]
+; ZNVER1-NEXT:    wrgsbaseq %rdi # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void @llvm.x86.wrgsbase.64(i64 %x)
   ret void
 }
 declare void @llvm.x86.wrgsbase.64(i64) nounwind readnone

llvm/trunk/test/CodeGen/X86/mmx-schedule.ll

 ;
 ; BTVER2-LABEL: test_maskmovq:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    maskmovq %mm1, %mm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_maskmovq:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    maskmovq %mm1, %mm0 # sched: [100:?]
+; ZNVER1-NEXT:    maskmovq %mm1, %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void @llvm.x86.mmx.maskmovq(x86_mmx %a0, x86_mmx %a1, i8* %a2)
   ret void
 }
 declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, i8*) nounwind
 
 define i32 @test_movd(x86_mmx %a0, i32 %a1, i32 *%a2) {
 ; GENERIC-LABEL: test_movd:

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    phaddd %mm1, %mm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    phaddd (%rdi), %mm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phaddd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    phaddd %mm1, %mm0 # sched: [100:?]
-; ZNVER1-NEXT:    phaddd (%rdi), %mm0 # sched: [100:?]
+; ZNVER1-NEXT:    phaddd %mm1, %mm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    phaddd (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx %a0, x86_mmx %a1)
   %2 = load x86_mmx, x86_mmx *%a2, align 8
   %3 = call x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx %1, x86_mmx %2)
   %4 = bitcast x86_mmx %3 to i64
   ret i64 %4
 }

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    phaddsw %mm1, %mm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    phaddsw (%rdi), %mm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phaddsw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    phaddsw %mm1, %mm0 # sched: [100:?]
-; ZNVER1-NEXT:    phaddsw (%rdi), %mm0 # sched: [100:?]
+; ZNVER1-NEXT:    phaddsw %mm1, %mm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    phaddsw (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call x86_mmx @llvm.x86.ssse3.phadd.sw(x86_mmx %a0, x86_mmx %a1)
   %2 = load x86_mmx, x86_mmx *%a2, align 8
   %3 = call x86_mmx @llvm.x86.ssse3.phadd.sw(x86_mmx %1, x86_mmx %2)
   %4 = bitcast x86_mmx %3 to i64
   ret i64 %4
 }

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    phaddw %mm1, %mm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    phaddw (%rdi), %mm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phaddw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    phaddw %mm1, %mm0 # sched: [100:?]
-; ZNVER1-NEXT:    phaddw (%rdi), %mm0 # sched: [100:?]
+; ZNVER1-NEXT:    phaddw %mm1, %mm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    phaddw (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %a0, x86_mmx %a1)
   %2 = load x86_mmx, x86_mmx *%a2, align 8
   %3 = call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %1, x86_mmx %2)
   %4 = bitcast x86_mmx %3 to i64
   ret i64 %4
 }

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    phsubd %mm1, %mm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    phsubd (%rdi), %mm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phsubd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    phsubd %mm1, %mm0 # sched: [100:?]
-; ZNVER1-NEXT:    phsubd (%rdi), %mm0 # sched: [100:?]
+; ZNVER1-NEXT:    phsubd %mm1, %mm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    phsubd (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call x86_mmx @llvm.x86.ssse3.phsub.d(x86_mmx %a0, x86_mmx %a1)
   %2 = load x86_mmx, x86_mmx *%a2, align 8
   %3 = call x86_mmx @llvm.x86.ssse3.phsub.d(x86_mmx %1, x86_mmx %2)
   %4 = bitcast x86_mmx %3 to i64
   ret i64 %4
 }

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    phsubsw %mm1, %mm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    phsubsw (%rdi), %mm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phsubsw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    phsubsw %mm1, %mm0 # sched: [100:?]
-; ZNVER1-NEXT:    phsubsw (%rdi), %mm0 # sched: [100:?]
+; ZNVER1-NEXT:    phsubsw %mm1, %mm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    phsubsw (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call x86_mmx @llvm.x86.ssse3.phsub.sw(x86_mmx %a0, x86_mmx %a1)
   %2 = load x86_mmx, x86_mmx *%a2, align 8
   %3 = call x86_mmx @llvm.x86.ssse3.phsub.sw(x86_mmx %1, x86_mmx %2)
   %4 = bitcast x86_mmx %3 to i64
   ret i64 %4
 }

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    phsubw %mm1, %mm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    phsubw (%rdi), %mm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phsubw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    phsubw %mm1, %mm0 # sched: [100:?]
-; ZNVER1-NEXT:    phsubw (%rdi), %mm0 # sched: [100:?]
+; ZNVER1-NEXT:    phsubw %mm1, %mm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    phsubw (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call x86_mmx @llvm.x86.ssse3.phsub.w(x86_mmx %a0, x86_mmx %a1)
   %2 = load x86_mmx, x86_mmx *%a2, align 8
   %3 = call x86_mmx @llvm.x86.ssse3.phsub.w(x86_mmx %1, x86_mmx %2)
   %4 = bitcast x86_mmx %3 to i64
   ret i64 %4
 }

llvm/trunk/test/CodeGen/X86/mwaitx-schedule.ll

 ; BDVER4-NEXT:    movl %esi, %ecx
 ; BDVER4-NEXT:    monitorx
 ; BDVER4-NEXT:    retq
 ;
 ; ZNVER1-LABEL: foo:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    leaq (%rdi), %rax # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl %esi, %ecx # sched: [1:0.25]
-; ZNVER1-NEXT:    monitorx # sched: [100:?]
+; ZNVER1-NEXT:    monitorx # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void @llvm.x86.monitorx(i8* %P, i32 %E, i32 %H)
   ret void
 }
 declare void @llvm.x86.monitorx(i8*, i32, i32) nounwind
 
 define void @bar(i32 %E, i32 %H, i32 %C) nounwind {
 ; GENERIC-LABEL: bar:

 ; BDVER4-NEXT:    retq
 ;
 ; ZNVER1-LABEL: bar:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    pushq %rbx # sched: [1:0.50]
 ; ZNVER1-NEXT:    movl %edi, %ecx # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl %esi, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl %edx, %ebx # sched: [1:0.25]
-; ZNVER1-NEXT:    mwaitx # sched: [100:?]
+; ZNVER1-NEXT:    mwaitx # sched: [100:0.25]
 ; ZNVER1-NEXT:    popq %rbx # sched: [8:0.50]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void @llvm.x86.mwaitx(i32 %E, i32 %H, i32 %C)
   ret void
 }
 declare void @llvm.x86.mwaitx(i32, i32, i32) nounwind

llvm/trunk/test/CodeGen/X86/rdrand-schedule.ll

 ;
 ; SKX-LABEL: test_rdrand_16:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    rdrandw %ax # sched: [100:0.25]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_rdrand_16:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdrandw %ax # sched: [100:?]
+; ZNVER1-NEXT:    rdrandw %ax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %call = call {i16, i32} @llvm.x86.rdrand.16()
   %randval = extractvalue {i16, i32} %call, 0
   ret i16 %randval
 }
 
 define i32 @test_rdrand_32(i32* %random_val) {
 ; GENERIC-LABEL: test_rdrand_32:

 ;
 ; SKX-LABEL: test_rdrand_32:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    rdrandl %eax # sched: [100:0.25]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_rdrand_32:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdrandl %eax # sched: [100:?]
+; ZNVER1-NEXT:    rdrandl %eax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %call = call {i32, i32} @llvm.x86.rdrand.32()
   %randval = extractvalue {i32, i32} %call, 0
   ret i32 %randval
 }
 
 define i64 @test_rdrand_64(i64* %random_val) {
 ; GENERIC-LABEL: test_rdrand_64:

 ;
 ; SKX-LABEL: test_rdrand_64:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    rdrandq %rax # sched: [100:0.25]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_rdrand_64:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdrandq %rax # sched: [100:?]
+; ZNVER1-NEXT:    rdrandq %rax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %call = call {i64, i32} @llvm.x86.rdrand.64()
   %randval = extractvalue {i64, i32} %call, 0
   ret i64 %randval
 }

llvm/trunk/test/CodeGen/X86/rdseed-schedule.ll

 ;
 ; SKX-LABEL: test_rdseed_16:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    rdseedw %ax # sched: [100:0.25]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_rdseed_16:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdseedw %ax # sched: [100:?]
+; ZNVER1-NEXT:    rdseedw %ax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %call = call {i16, i32} @llvm.x86.rdseed.16()
   %randval = extractvalue {i16, i32} %call, 0
   ret i16 %randval
 }
 
 define i32 @test_rdseed_32(i16* %random_val) {
 ; GENERIC-LABEL: test_rdseed_32:

 ;
 ; SKX-LABEL: test_rdseed_32:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    rdseedl %eax # sched: [100:0.25]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_rdseed_32:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdseedl %eax # sched: [100:?]
+; ZNVER1-NEXT:    rdseedl %eax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %call = call {i32, i32} @llvm.x86.rdseed.32()
   %randval = extractvalue {i32, i32} %call, 0
   ret i32 %randval
 }
 
 define i64 @test_rdseed_64(i64* %random_val) {
 ; GENERIC-LABEL: test_rdseed_64:

 ;
 ; SKX-LABEL: test_rdseed_64:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    rdseedq %rax # sched: [100:0.25]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_rdseed_64:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    rdseedq %rax # sched: [100:?]
+; ZNVER1-NEXT:    rdseedq %rax # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %call = call {i64, i32} @llvm.x86.rdseed.64()
   %randval = extractvalue {i64, i32} %call, 0
   ret i64 %randval
 }

llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll

 ; BTVER2-NEXT:    aaa # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_aaa:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    aaa # sched: [100:?]
+; ZNVER1-NEXT:    aaa # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   %1 = tail call i8 asm "aaa", "=r,r"(i8 %a0) nounwind
   ret i8 %1
 }
 
 define void @test_aad(i16 %a0) optsize {
 ; GENERIC-LABEL: test_aad:

 ; BTVER2-NEXT:    aad $16 # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_aad:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    aad # sched: [100:?]
-; ZNVER1-NEXT:    aad $16 # sched: [100:?]
+; ZNVER1-NEXT:    aad # sched: [100:0.25]
+; ZNVER1-NEXT:    aad $16 # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm "aad \0A\09 aad $1", "r,i"(i16 %a0, i16 16) nounwind
   ret void
 }
 
 define void @test_aam(i8 %a0) optsize {
 ; GENERIC-LABEL: test_aam:

 ; BTVER2-NEXT:    aam $16 # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_aam:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    aam # sched: [100:?]
-; ZNVER1-NEXT:    aam $16 # sched: [100:?]
+; ZNVER1-NEXT:    aam # sched: [100:0.25]
+; ZNVER1-NEXT:    aam $16 # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm "aam \0A\09 aam $1", "r,i"(i8 %a0, i8 16) nounwind
   ret void
 }
 
 define i8 @test_aas(i8 %a0) optsize {
 ; GENERIC-LABEL: test_aas:

 ; BTVER2-NEXT:    aas # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_aas:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    aas # sched: [100:?]
+; ZNVER1-NEXT:    aas # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   %1 = tail call i8 asm "aas", "=r,r"(i8 %a0) nounwind
   ret i8 %1
 }
 
 define void @test_arpl(i16 %a0, i16 *%a1) optsize {
 ; GENERIC-LABEL: test_arpl:

 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_arpl:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
 ; ZNVER1-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    arpl %ax, (%ecx) # sched: [100:?]
+; ZNVER1-NEXT:    arpl %ax, (%ecx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   call void asm sideeffect "arpl $0, $1", "r,*m"(i16 %a0, i16 *%a1)
   ret void
 }
 
 define void @test_bound(i16 %a0, i16 *%a1, i32 %a2, i32 *%a3) optsize {
 ; GENERIC-LABEL: test_bound:

 ; HASWELL-NEXT:    pushl %esi # sched: [2:1.00]
 ; HASWELL-NEXT:    .cfi_def_cfa_offset 8
 ; HASWELL-NEXT:    .cfi_offset %esi, -8
 ; HASWELL-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; HASWELL-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
 ; HASWELL-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
 ; HASWELL-NEXT:    movl {{[0-9]+}}(%esp), %esi # sched: [5:0.50]
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    bound %ax, (%esi) # sched: [1:?]
-; HASWELL-NEXT:    bound %ecx, (%edx) # sched: [1:?]
+; HASWELL-NEXT:    bound %ax, (%esi) # sched: [1:3.75]
+; HASWELL-NEXT:    bound %ecx, (%edx) # sched: [1:3.75]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    popl %esi # sched: [6:0.50]
 ; HASWELL-NEXT:    .cfi_def_cfa_offset 4
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_bound:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    pushl %esi # sched: [2:1.00]

 ; ZNVER1-NEXT:    pushl %esi # sched: [1:0.50]
 ; ZNVER1-NEXT:    .cfi_def_cfa_offset 8
 ; ZNVER1-NEXT:    .cfi_offset %esi, -8
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [8:0.50]
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %esi # sched: [8:0.50]
 ; ZNVER1-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    bound %ax, (%esi) # sched: [100:?]
-; ZNVER1-NEXT:    bound %ecx, (%edx) # sched: [100:?]
+; ZNVER1-NEXT:    bound %ax, (%esi) # sched: [100:0.25]
+; ZNVER1-NEXT:    bound %ecx, (%edx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    popl %esi # sched: [8:0.50]
 ; ZNVER1-NEXT:    .cfi_def_cfa_offset 4
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   call void asm sideeffect "bound $0, $1 \0A\09 bound $2, $3", "r,*m,r,*m"(i16 %a0, i16 *%a1, i32 %a2, i32 *%a3)
   ret void
 }
 

 ; BTVER2-NEXT:    daa # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_daa:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    daa # sched: [100:?]
+; ZNVER1-NEXT:    daa # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   %1 = tail call i8 asm "daa", "=r,r"(i8 %a0) nounwind
   ret i8 %1
 }
 
 define i8 @test_das(i8 %a0) optsize {
 ; GENERIC-LABEL: test_das:

 ; BTVER2-NEXT:    das # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_das:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    das # sched: [100:?]
+; ZNVER1-NEXT:    das # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   %1 = tail call i8 asm "das", "=r,r"(i8 %a0) nounwind
   ret i8 %1
 }
 
 define void @test_dec16(i16 %a0, i16* %a1) optsize {
 ; GENERIC-LABEL: test_dec16:

 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    into # sched: [100:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_into:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    into # sched: [1:?]
+; HASWELL-NEXT:    into # sched: [1:1.00]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_into:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    into # sched: [100:0.25]
 ; BROADWELL-NEXT:    #NO_APP

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    into # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_into:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    into # sched: [100:?]
+; ZNVER1-NEXT:    into # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   call void asm sideeffect "into", ""()
   ret void
 }
 
 ; TODO - test_jmp
 

 ; BTVER2-NEXT:    pushl %fs # sched: [100:0.50]
 ; BTVER2-NEXT:    pushl %gs # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pop_push:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    popl %ds # sched: [100:?]
-; ZNVER1-NEXT:    popl %es # sched: [100:?]
-; ZNVER1-NEXT:    popl %ss # sched: [100:?]
-; ZNVER1-NEXT:    popl %fs # sched: [100:?]
-; ZNVER1-NEXT:    popl %gs # sched: [100:?]
-; ZNVER1-NEXT:    pushl %cs # sched: [100:?]
-; ZNVER1-NEXT:    pushl %ds # sched: [100:?]
-; ZNVER1-NEXT:    pushl %es # sched: [100:?]
-; ZNVER1-NEXT:    pushl %ss # sched: [100:?]
-; ZNVER1-NEXT:    pushl %fs # sched: [100:?]
-; ZNVER1-NEXT:    pushl %gs # sched: [100:?]
+; ZNVER1-NEXT:    popl %ds # sched: [100:0.25]
+; ZNVER1-NEXT:    popl %es # sched: [100:0.25]
+; ZNVER1-NEXT:    popl %ss # sched: [100:0.25]
+; ZNVER1-NEXT:    popl %fs # sched: [100:0.25]
+; ZNVER1-NEXT:    popl %gs # sched: [100:0.25]
+; ZNVER1-NEXT:    pushl %cs # sched: [100:0.25]
+; ZNVER1-NEXT:    pushl %ds # sched: [100:0.25]
+; ZNVER1-NEXT:    pushl %es # sched: [100:0.25]
+; ZNVER1-NEXT:    pushl %ss # sched: [100:0.25]
+; ZNVER1-NEXT:    pushl %fs # sched: [100:0.25]
+; ZNVER1-NEXT:    pushl %gs # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   call void asm sideeffect "pop %DS \0A\09 pop %ES \0A\09 pop %SS \0A\09 pop %FS \0A\09 pop %GS \0A\09 push %CS \0A\09 push %DS \0A\09 push %ES \0A\09 push %SS \0A\09 push %FS \0A\09 push %GS", ""()
   ret void
 }
 define i16 @test_pop_push_16(i16 %a0, i16 *%a1) optsize {
 ; GENERIC-LABEL: test_pop_push_16:
 ; GENERIC:       # %bb.0:

 ; SANDY-NEXT:    pushal # sched: [1:1.00]
 ; SANDY-NEXT:    pushfl # sched: [1:1.00]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_popa_popf_pusha_pushf:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    popal # sched: [1:?]
+; HASWELL-NEXT:    popal # sched: [1:4.50]
 ; HASWELL-NEXT:    popfl # sched: [5:0.50]
-; HASWELL-NEXT:    pushal # sched: [1:?]
+; HASWELL-NEXT:    pushal # sched: [1:4.75]
 ; HASWELL-NEXT:    pushfl # sched: [1:1.00]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_popa_popf_pusha_pushf:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    popal # sched: [5:0.50]

 ; BTVER2-NEXT:    pushal # sched: [1:1.00]
 ; BTVER2-NEXT:    pushfl # sched: [1:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_popa_popf_pusha_pushf:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    popal # sched: [100:?]
-; ZNVER1-NEXT:    popfl # sched: [100:?]
+; ZNVER1-NEXT:    popal # sched: [100:0.25]
+; ZNVER1-NEXT:    popfl # sched: [100:0.25]
 ; ZNVER1-NEXT:    pushal # sched: [8:0.50]
-; ZNVER1-NEXT:    pushfl # sched: [100:?]
+; ZNVER1-NEXT:    pushfl # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   call void asm sideeffect "popa \0A\09 popf \0A\09 pusha \0A\09 pushf", ""()
   ret void
 }
 
 define void @test_ret() optsize {
 ; GENERIC-LABEL: test_ret:

llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll

 ;
 ; HASWELL-LABEL: test_bt_btc_btr_bts_16:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    btw %si, %di # sched: [1:0.50]
 ; HASWELL-NEXT:    btcw %si, %di # sched: [1:0.50]
 ; HASWELL-NEXT:    btrw %si, %di # sched: [1:0.50]
 ; HASWELL-NEXT:    btsw %si, %di # sched: [1:0.50]
-; HASWELL-NEXT:    btw %si, (%rdx) # sched: [1:?]
-; HASWELL-NEXT:    btcw %si, (%rdx) # sched: [1:?]
-; HASWELL-NEXT:    btrw %si, (%rdx) # sched: [1:?]
-; HASWELL-NEXT:    btsw %si, (%rdx) # sched: [1:?]
+; HASWELL-NEXT:    btw %si, (%rdx) # sched: [1:2.50]
+; HASWELL-NEXT:    btcw %si, (%rdx) # sched: [1:2.75]
+; HASWELL-NEXT:    btrw %si, (%rdx) # sched: [1:2.75]
+; HASWELL-NEXT:    btsw %si, (%rdx) # sched: [1:2.75]
 ; HASWELL-NEXT:    btw $7, %di # sched: [1:0.50]
 ; HASWELL-NEXT:    btcw $7, %di # sched: [1:0.50]
 ; HASWELL-NEXT:    btrw $7, %di # sched: [1:0.50]
 ; HASWELL-NEXT:    btsw $7, %di # sched: [1:0.50]
 ; HASWELL-NEXT:    btw $7, (%rdx) # sched: [6:0.50]
 ; HASWELL-NEXT:    btcw $7, (%rdx) # sched: [7:1.00]
 ; HASWELL-NEXT:    btrw $7, (%rdx) # sched: [7:1.00]
 ; HASWELL-NEXT:    btsw $7, (%rdx) # sched: [7:1.00]

 ;
 ; HASWELL-LABEL: test_bt_btc_btr_bts_32:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    btl %esi, %edi # sched: [1:0.50]
 ; HASWELL-NEXT:    btcl %esi, %edi # sched: [1:0.50]
 ; HASWELL-NEXT:    btrl %esi, %edi # sched: [1:0.50]
 ; HASWELL-NEXT:    btsl %esi, %edi # sched: [1:0.50]
-; HASWELL-NEXT:    btl %esi, (%rdx) # sched: [1:?]
-; HASWELL-NEXT:    btcl %esi, (%rdx) # sched: [1:?]
-; HASWELL-NEXT:    btrl %esi, (%rdx) # sched: [1:?]
-; HASWELL-NEXT:    btsl %esi, (%rdx) # sched: [1:?]
+; HASWELL-NEXT:    btl %esi, (%rdx) # sched: [1:2.50]
+; HASWELL-NEXT:    btcl %esi, (%rdx) # sched: [1:2.75]
+; HASWELL-NEXT:    btrl %esi, (%rdx) # sched: [1:2.75]
+; HASWELL-NEXT:    btsl %esi, (%rdx) # sched: [1:2.75]
 ; HASWELL-NEXT:    btl $7, %edi # sched: [1:0.50]
 ; HASWELL-NEXT:    btcl $7, %edi # sched: [1:0.50]
 ; HASWELL-NEXT:    btrl $7, %edi # sched: [1:0.50]
 ; HASWELL-NEXT:    btsl $7, %edi # sched: [1:0.50]
 ; HASWELL-NEXT:    btl $7, (%rdx) # sched: [6:0.50]
 ; HASWELL-NEXT:    btcl $7, (%rdx) # sched: [7:1.00]
 ; HASWELL-NEXT:    btrl $7, (%rdx) # sched: [7:1.00]
 ; HASWELL-NEXT:    btsl $7, (%rdx) # sched: [7:1.00]

 ;
 ; HASWELL-LABEL: test_bt_btc_btr_bts_64:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    btq %rsi, %rdi # sched: [1:0.50]
 ; HASWELL-NEXT:    btcq %rsi, %rdi # sched: [1:0.50]
 ; HASWELL-NEXT:    btrq %rsi, %rdi # sched: [1:0.50]
 ; HASWELL-NEXT:    btsq %rsi, %rdi # sched: [1:0.50]
-; HASWELL-NEXT:    btq %rsi, (%rdx) # sched: [1:?]
-; HASWELL-NEXT:    btcq %rsi, (%rdx) # sched: [1:?]
-; HASWELL-NEXT:    btrq %rsi, (%rdx) # sched: [1:?]
-; HASWELL-NEXT:    btsq %rsi, (%rdx) # sched: [1:?]
+; HASWELL-NEXT:    btq %rsi, (%rdx) # sched: [1:2.50]
+; HASWELL-NEXT:    btcq %rsi, (%rdx) # sched: [1:2.75]
+; HASWELL-NEXT:    btrq %rsi, (%rdx) # sched: [1:2.75]
+; HASWELL-NEXT:    btsq %rsi, (%rdx) # sched: [1:2.75]
 ; HASWELL-NEXT:    btq $7, %rdi # sched: [1:0.50]
 ; HASWELL-NEXT:    btcq $7, %rdi # sched: [1:0.50]
 ; HASWELL-NEXT:    btrq $7, %rdi # sched: [1:0.50]
 ; HASWELL-NEXT:    btsq $7, %rdi # sched: [1:0.50]
 ; HASWELL-NEXT:    btq $7, (%rdx) # sched: [6:0.50]
 ; HASWELL-NEXT:    btcq $7, (%rdx) # sched: [7:1.00]
 ; HASWELL-NEXT:    btrq $7, (%rdx) # sched: [7:1.00]
 ; HASWELL-NEXT:    btsq $7, (%rdx) # sched: [7:1.00]
; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "cbw \0A\09 cdq \0A\09 cdqe \0A\09 cqo \0A\09 cwd \0A\09 cwde", ""() nounwind
   ret void
 }
 
 define void @test_clc_cld_cmc() optsize {
 ; GENERIC-LABEL: test_clc_cld_cmc:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
-; GENERIC-NEXT:    clc # sched: [1:?]
+; GENERIC-NEXT:    clc # sched: [1:0.25]
 ; GENERIC-NEXT:    cld # sched: [1:0.33]
 ; GENERIC-NEXT:    cmc # sched: [1:0.33]
 ; GENERIC-NEXT:    #NO_APP
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; ATOM-LABEL: test_clc_cld_cmc:
 ; ATOM:       # %bb.0:
 ; ATOM-NEXT:    #APP

 ; SLM-NEXT:    cld # sched: [1:0.50]
 ; SLM-NEXT:    cmc # sched: [1:0.50]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_clc_cld_cmc:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
-; SANDY-NEXT:    clc # sched: [1:?]
+; SANDY-NEXT:    clc # sched: [1:0.25]
 ; SANDY-NEXT:    cld # sched: [1:0.33]
 ; SANDY-NEXT:    cmc # sched: [1:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_clc_cld_cmc:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    clc # sched: [1:?]
+; HASWELL-NEXT:    clc # sched: [1:0.25]
 ; HASWELL-NEXT:    cld # sched: [3:1.00]
 ; HASWELL-NEXT:    cmc # sched: [1:0.25]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retq # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_clc_cld_cmc:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
-; BROADWELL-NEXT:    clc # sched: [1:?]
+; BROADWELL-NEXT:    clc # sched: [1:0.25]
 ; BROADWELL-NEXT:    cld # sched: [3:1.00]
 ; BROADWELL-NEXT:    cmc # sched: [1:0.25]
 ; BROADWELL-NEXT:    #NO_APP
 ; BROADWELL-NEXT:    retq # sched: [7:1.00]
 ;
 ; SKYLAKE-LABEL: test_clc_cld_cmc:
 ; SKYLAKE:       # %bb.0:
 ; SKYLAKE-NEXT:    #APP
-; SKYLAKE-NEXT:    clc # sched: [1:?]
+; SKYLAKE-NEXT:    clc # sched: [1:0.17]
 ; SKYLAKE-NEXT:    cld # sched: [3:1.00]
 ; SKYLAKE-NEXT:    cmc # sched: [1:0.25]
 ; SKYLAKE-NEXT:    #NO_APP
 ; SKYLAKE-NEXT:    retq # sched: [7:1.00]
 ;
 ; SKX-LABEL: test_clc_cld_cmc:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    #APP
-; SKX-NEXT:    clc # sched: [1:?]
+; SKX-NEXT:    clc # sched: [1:0.17]
 ; SKX-NEXT:    cld # sched: [3:1.00]
 ; SKX-NEXT:    cmc # sched: [1:0.25]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_clc_cld_cmc:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP

 ; BTVER2-NEXT:    cmpsl %es:(%rdi), (%rsi) # sched: [100:0.50]
 ; BTVER2-NEXT:    cmpsq %es:(%rdi), (%rsi) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_cmps:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    cmpsb %es:(%rdi), (%rsi) # sched: [100:?]
-; ZNVER1-NEXT:    cmpsw %es:(%rdi), (%rsi) # sched: [100:?]
-; ZNVER1-NEXT:    cmpsl %es:(%rdi), (%rsi) # sched: [100:?]
-; ZNVER1-NEXT:    cmpsq %es:(%rdi), (%rsi) # sched: [100:?]
+; ZNVER1-NEXT:    cmpsb %es:(%rdi), (%rsi) # sched: [100:0.25]
+; ZNVER1-NEXT:    cmpsw %es:(%rdi), (%rsi) # sched: [100:0.25]
+; ZNVER1-NEXT:    cmpsl %es:(%rdi), (%rsi) # sched: [100:0.25]
+; ZNVER1-NEXT:    cmpsq %es:(%rdi), (%rsi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "cmpsb \0A\09 cmpsw \0A\09 cmpsl \0A\09 cmpsq", ""()
   ret void
 }
 
 define void @test_cmpxchg_8(i8 %a0, i8 %a1, i8 *%a2) optsize {
 ; GENERIC-LABEL: test_cmpxchg_8:

 ; BTVER2-NEXT:    cmpxchg16b (%rdi) # sched: [4:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_cmpxchg8b_cmpxchg16b:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    cmpxchg8b (%rdi) # sched: [1:0.50]
-; ZNVER1-NEXT:    cmpxchg16b (%rdi) # sched: [100:?]
+; ZNVER1-NEXT:    cmpxchg16b (%rdi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "cmpxchg8b $0 \0a\09 cmpxchg16b $0", "*m"(i8 *%a0) nounwind
   ret void
 }
 
 define void @test_cpuid() optsize {
 ; GENERIC-LABEL: test_cpuid:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    cpuid # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_cpuid:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    cpuid # sched: [100:?]
+; ZNVER1-NEXT:    cpuid # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "cpuid", ""() nounwind
   ret void
 }
 
 define void @test_dec8(i8 %a0, i8* %a1) optsize {
 ; GENERIC-LABEL: test_dec8:

 ; BTVER2-NEXT:    # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_enter:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    enter $7, $4095 # imm = 0xFFF
-; ZNVER1-NEXT:    # sched: [100:?]
+; ZNVER1-NEXT:    # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "enter $0, $1", "i,i"(i8 7, i16 4095) nounwind
   ret void
 }
 
 define void @test_idiv(i8 %a0, i16 %a1, i32 %a2, i64 %a3, i8 *%p0, i16 *%p1, i32 *%p2, i64 *%p3) optsize {
 ; GENERIC-LABEL: test_idiv:

 ; BTVER2-NEXT:    inw %dx, %ax # sched: [100:0.50]
 ; BTVER2-NEXT:    inl %dx, %eax # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_in:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    inb $7, %al # sched: [100:?]
-; ZNVER1-NEXT:    inw $7, %ax # sched: [100:?]
-; ZNVER1-NEXT:    inl $7, %eax # sched: [100:?]
-; ZNVER1-NEXT:    inb %dx, %al # sched: [100:?]
-; ZNVER1-NEXT:    inw %dx, %ax # sched: [100:?]
-; ZNVER1-NEXT:    inl %dx, %eax # sched: [100:?]
+; ZNVER1-NEXT:    inb $7, %al # sched: [100:0.25]
+; ZNVER1-NEXT:    inw $7, %ax # sched: [100:0.25]
+; ZNVER1-NEXT:    inl $7, %eax # sched: [100:0.25]
+; ZNVER1-NEXT:    inb %dx, %al # sched: [100:0.25]
+; ZNVER1-NEXT:    inw %dx, %ax # sched: [100:0.25]
+; ZNVER1-NEXT:    inl %dx, %eax # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "inb $0, %AL \0A\09 inw $0, %AX \0A\09 inl $0, %EAX \0A\09 inb %DX, %AL \0A\09 inw %DX, %AX \0A\09 inl %DX, %EAX", "i"(i8 7) nounwind
   ret void
 }
 
 define void @test_inc8(i8 %a0, i8* %a1) optsize {
 ; GENERIC-LABEL: test_inc8:

 ; BTVER2-NEXT:    insw %dx, %es:(%rdi) # sched: [100:0.50]
 ; BTVER2-NEXT:    insl %dx, %es:(%rdi) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_ins:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    insb %dx, %es:(%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    insw %dx, %es:(%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    insl %dx, %es:(%rdi) # sched: [100:?]
+; ZNVER1-NEXT:    insb %dx, %es:(%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    insw %dx, %es:(%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    insl %dx, %es:(%rdi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "insb \0A\09 insw \0A\09 insl", ""()
   ret void
 }
 
 define void @test_int() optsize {
 ; GENERIC-LABEL: test_int:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    int $7 # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_int:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    int $7 # sched: [100:?]
+; ZNVER1-NEXT:    int $7 # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "int $0", "i"(i8 7)
   ret void
 }
 
 define void @test_invlpg_invlpga(i8 *%a0) optsize {
 ; GENERIC-LABEL: test_invlpg_invlpga:

 ; BTVER2-NEXT:    invlpg (%rdi) # sched: [100:0.50]
 ; BTVER2-NEXT:    invlpga %rax, %ecx # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_invlpg_invlpga:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    invlpg (%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    invlpga %rax, %ecx # sched: [100:?]
+; ZNVER1-NEXT:    invlpg (%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    invlpga %rax, %ecx # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm sideeffect "invlpg $0 \0A\09 invlpga %rax, %ecx", "*m"(i8 *%a0) nounwind
   ret void
 }
 
 define void @test_jcc() optsize {
 ; GENERIC-LABEL: test_jcc:

 ; BTVER2-NEXT:    lahf # sched: [1:0.50]
 ; BTVER2-NEXT:    sahf # sched: [1:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_lahf_sahf:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    lahf # sched: [100:?]
+; ZNVER1-NEXT:    lahf # sched: [100:0.25]
 ; ZNVER1-NEXT:    sahf # sched: [2:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "lahf \0A\09 sahf", ""() nounwind
   ret void
 }
 
 ; TODO - test_lds

 ; BTVER2-NEXT:    lodsl (%rsi), %eax # sched: [100:0.50]
 ; BTVER2-NEXT:    lodsq (%rsi), %rax # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_lods:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    lodsb (%rsi), %al # sched: [100:?]
-; ZNVER1-NEXT:    lodsw (%rsi), %ax # sched: [100:?]
-; ZNVER1-NEXT:    lodsl (%rsi), %eax # sched: [100:?]
-; ZNVER1-NEXT:    lodsq (%rsi), %rax # sched: [100:?]
+; ZNVER1-NEXT:    lodsb (%rsi), %al # sched: [100:0.25]
+; ZNVER1-NEXT:    lodsw (%rsi), %ax # sched: [100:0.25]
+; ZNVER1-NEXT:    lodsl (%rsi), %eax # sched: [100:0.25]
+; ZNVER1-NEXT:    lodsq (%rsi), %rax # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "lodsb \0A\09 lodsw \0A\09 lodsl \0A\09 lodsq", ""()
   ret void
 }
 
 define void @test_loop() optsize {
 ; GENERIC-LABEL: test_loop:

 ; BTVER2-NEXT:    movsl (%rsi), %es:(%rdi) # sched: [100:0.50]
 ; BTVER2-NEXT:    movsq (%rsi), %es:(%rdi) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_movs:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    movsb (%rsi), %es:(%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    movsw (%rsi), %es:(%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    movsl (%rsi), %es:(%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    movsq (%rsi), %es:(%rdi) # sched: [100:?]
+; ZNVER1-NEXT:    movsb (%rsi), %es:(%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    movsw (%rsi), %es:(%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    movsl (%rsi), %es:(%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    movsq (%rsi), %es:(%rdi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "movsb \0A\09 movsw \0A\09 movsl \0A\09 movsq", ""()
   ret void
 }
 
 ; TODO - test_movsx
 ; TODO - test_movzx
; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "negb $0 \0A\09 negb $4 \0A\09 negw $1 \0A\09 negw $5 \0A\09 negl $2 \0A\09 negl $6 \0A\09 negq $3 \0A\09 negq $7", "r,r,r,r,*m,*m,*m,*m"(i8 %a0, i16 %a1, i32 %a2, i64 %a3, i8 *%p0, i16 *%p1, i32 *%p2, i64 *%p3) nounwind
   ret void
 }
 
 define void @test_nop(i16 %a0, i32 %a1, i64 %a2, i16 *%p0, i32 *%p1, i64 *%p2) optsize {
 ; GENERIC-LABEL: test_nop:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
-; GENERIC-NEXT:    nop # sched: [1:?]
-; GENERIC-NEXT:    nopw %di # sched: [1:?]
-; GENERIC-NEXT:    nopw (%rcx) # sched: [1:?]
-; GENERIC-NEXT:    nopl %esi # sched: [1:?]
-; GENERIC-NEXT:    nopl (%r8) # sched: [1:?]
-; GENERIC-NEXT:    nopq %rdx # sched: [1:?]
-; GENERIC-NEXT:    nopq (%r9) # sched: [1:?]
+; GENERIC-NEXT:    nop # sched: [1:0.25]
+; GENERIC-NEXT:    nopw %di # sched: [1:0.25]
+; GENERIC-NEXT:    nopw (%rcx) # sched: [1:0.25]
+; GENERIC-NEXT:    nopl %esi # sched: [1:0.25]
+; GENERIC-NEXT:    nopl (%r8) # sched: [1:0.25]
+; GENERIC-NEXT:    nopq %rdx # sched: [1:0.25]
+; GENERIC-NEXT:    nopq (%r9) # sched: [1:0.25]
 ; GENERIC-NEXT:    #NO_APP
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; ATOM-LABEL: test_nop:
 ; ATOM:       # %bb.0:
 ; ATOM-NEXT:    #APP
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    nopw %di # sched: [1:0.50]
 ; ATOM-NEXT:    nopw (%rcx) # sched: [1:0.50]
 ; ATOM-NEXT:    nopl %esi # sched: [1:0.50]
 ; ATOM-NEXT:    nopl (%r8) # sched: [1:0.50]
 ; ATOM-NEXT:    nopq %rdx # sched: [1:0.50]
 ; ATOM-NEXT:    nopq (%r9) # sched: [1:0.50]
 ; ATOM-NEXT:    #NO_APP
 ; ATOM-NEXT:    retq # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_nop:
 ; SLM:       # %bb.0:
 ; SLM-NEXT:    #APP
-; SLM-NEXT:    nop # sched: [1:?]
-; SLM-NEXT:    nopw %di # sched: [1:?]
-; SLM-NEXT:    nopw (%rcx) # sched: [1:?]
-; SLM-NEXT:    nopl %esi # sched: [1:?]
-; SLM-NEXT:    nopl (%r8) # sched: [1:?]
-; SLM-NEXT:    nopq %rdx # sched: [1:?]
-; SLM-NEXT:    nopq (%r9) # sched: [1:?]
+; SLM-NEXT:    nop # sched: [1:0.50]
+; SLM-NEXT:    nopw %di # sched: [1:0.50]
+; SLM-NEXT:    nopw (%rcx) # sched: [1:0.50]
+; SLM-NEXT:    nopl %esi # sched: [1:0.50]
+; SLM-NEXT:    nopl (%r8) # sched: [1:0.50]
+; SLM-NEXT:    nopq %rdx # sched: [1:0.50]
+; SLM-NEXT:    nopq (%r9) # sched: [1:0.50]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_nop:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
-; SANDY-NEXT:    nop # sched: [1:?]
-; SANDY-NEXT:    nopw %di # sched: [1:?]
-; SANDY-NEXT:    nopw (%rcx) # sched: [1:?]
-; SANDY-NEXT:    nopl %esi # sched: [1:?]
-; SANDY-NEXT:    nopl (%r8) # sched: [1:?]
-; SANDY-NEXT:    nopq %rdx # sched: [1:?]
-; SANDY-NEXT:    nopq (%r9) # sched: [1:?]
+; SANDY-NEXT:    nop # sched: [1:0.25]
+; SANDY-NEXT:    nopw %di # sched: [1:0.25]
+; SANDY-NEXT:    nopw (%rcx) # sched: [1:0.25]
+; SANDY-NEXT:    nopl %esi # sched: [1:0.25]
+; SANDY-NEXT:    nopl (%r8) # sched: [1:0.25]
+; SANDY-NEXT:    nopq %rdx # sched: [1:0.25]
+; SANDY-NEXT:    nopq (%r9) # sched: [1:0.25]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_nop:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    nop # sched: [1:0.25]
 ; HASWELL-NEXT:    nopw %di # sched: [1:0.25]

 ; BTVER2-NEXT:    nopq %rdx # sched: [1:0.50]
 ; BTVER2-NEXT:    nopq (%r9) # sched: [1:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_nop:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    nop # sched: [1:?]
-; ZNVER1-NEXT:    nopw %di # sched: [1:?]
-; ZNVER1-NEXT:    nopw (%rcx) # sched: [1:?]
-; ZNVER1-NEXT:    nopl %esi # sched: [1:?]
-; ZNVER1-NEXT:    nopl (%r8) # sched: [1:?]
-; ZNVER1-NEXT:    nopq %rdx # sched: [1:?]
-; ZNVER1-NEXT:    nopq (%r9) # sched: [1:?]
+; ZNVER1-NEXT:    nop # sched: [1:0.25]
+; ZNVER1-NEXT:    nopw %di # sched: [1:0.25]
+; ZNVER1-NEXT:    nopw (%rcx) # sched: [1:0.25]
+; ZNVER1-NEXT:    nopl %esi # sched: [1:0.25]
+; ZNVER1-NEXT:    nopl (%r8) # sched: [1:0.25]
+; ZNVER1-NEXT:    nopq %rdx # sched: [1:0.25]
+; ZNVER1-NEXT:    nopq (%r9) # sched: [1:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "nop \0A\09 nopw $0 \0A\09 nopw $3 \0A\09 nopl $1 \0A\09 nopl $4 \0A\09 nopq $2 \0A\09 nopq $5", "r,r,r,*m,*m,*m"(i16 %a0, i32 %a1, i64 %a2, i16 *%p0, i32 *%p1, i64 *%p2) nounwind
   ret void
 }
 
 define void @test_not(i8 %a0, i16 %a1, i32 %a2, i64 %a3, i8 *%p0, i16 *%p1, i32 *%p2, i64 *%p3) optsize {
 ; GENERIC-LABEL: test_not:

 ; BTVER2-NEXT:    outw %ax, %dx # sched: [100:0.50]
 ; BTVER2-NEXT:    outl %eax, %dx # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_out:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    outb %al, $7 # sched: [100:?]
-; ZNVER1-NEXT:    outw %ax, $7 # sched: [100:?]
-; ZNVER1-NEXT:    outl %eax, $7 # sched: [100:?]
-; ZNVER1-NEXT:    outb %al, %dx # sched: [100:?]
-; ZNVER1-NEXT:    outw %ax, %dx # sched: [100:?]
-; ZNVER1-NEXT:    outl %eax, %dx # sched: [100:?]
+; ZNVER1-NEXT:    outb %al, $7 # sched: [100:0.25]
+; ZNVER1-NEXT:    outw %ax, $7 # sched: [100:0.25]
+; ZNVER1-NEXT:    outl %eax, $7 # sched: [100:0.25]
+; ZNVER1-NEXT:    outb %al, %dx # sched: [100:0.25]
+; ZNVER1-NEXT:    outw %ax, %dx # sched: [100:0.25]
+; ZNVER1-NEXT:    outl %eax, %dx # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "outb %AL, $0 \0A\09 outw %AX, $0 \0A\09 outl %EAX, $0 \0A\09 outb %AL, %DX \0A\09 outw %AX, %DX \0A\09 outl %EAX, %DX", "i"(i8 7) nounwind
   ret void
 }
 
 define void @test_outs() optsize {
 ; GENERIC-LABEL: test_outs:

 ; BTVER2-NEXT:    outsw (%rsi), %dx # sched: [100:0.50]
 ; BTVER2-NEXT:    outsl (%rsi), %dx # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_outs:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    outsb (%rsi), %dx # sched: [100:?]
-; ZNVER1-NEXT:    outsw (%rsi), %dx # sched: [100:?]
-; ZNVER1-NEXT:    outsl (%rsi), %dx # sched: [100:?]
+; ZNVER1-NEXT:    outsb (%rsi), %dx # sched: [100:0.25]
+; ZNVER1-NEXT:    outsw (%rsi), %dx # sched: [100:0.25]
+; ZNVER1-NEXT:    outsl (%rsi), %dx # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "outsb \0A\09 outsw \0A\09 outsl", ""()
   ret void
 }
 
 define void @test_pause() optsize {
 ; GENERIC-LABEL: test_pause:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
 ; GENERIC-NEXT:    pause # sched: [4:1.33]
 ; GENERIC-NEXT:    #NO_APP
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; ATOM-LABEL: test_pause:
 ; ATOM:       # %bb.0:
 ; ATOM-NEXT:    #APP
 ; ATOM-NEXT:    pause # sched: [17:8.50]
 ; ATOM-NEXT:    #NO_APP
 ; ATOM-NEXT:    retq # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_pause:
 ; SLM:       # %bb.0:
 ; SLM-NEXT:    #APP
-; SLM-NEXT:    pause # sched: [1:?]
+; SLM-NEXT:    pause # sched: [1:0.50]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_pause:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    pause # sched: [4:1.33]
 ; SANDY-NEXT:    #NO_APP

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    pause # sched: [1:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pause:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    pause # sched: [100:?]
+; ZNVER1-NEXT:    pause # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "pause", ""()
   ret void
 }
 
 define void @test_pop_push() optsize {
 ; GENERIC-LABEL: test_pop_push:

 ; BTVER2-NEXT:    pushq %fs # sched: [100:0.50]
 ; BTVER2-NEXT:    pushq %gs # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pop_push:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    popq %fs # sched: [100:?]
-; ZNVER1-NEXT:    popq %gs # sched: [100:?]
-; ZNVER1-NEXT:    pushq %fs # sched: [100:?]
-; ZNVER1-NEXT:    pushq %gs # sched: [100:?]
+; ZNVER1-NEXT:    popq %fs # sched: [100:0.25]
+; ZNVER1-NEXT:    popq %gs # sched: [100:0.25]
+; ZNVER1-NEXT:    pushq %fs # sched: [100:0.25]
+; ZNVER1-NEXT:    pushq %gs # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "pop %FS \0A\09 pop %GS \0A\09 push %FS \0A\09 push %GS", ""()
   ret void
 }
 define i16 @test_pop_push_16(i16 %a0, i16 *%a1) optsize {
 ; GENERIC-LABEL: test_pop_push_16:
 ; GENERIC:       # %bb.0:

 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_rcl_rcr_8:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    rclb %dil # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrb %dil # sched: [1:0.25]
-; ZNVER1-NEXT:    rclb (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrb (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rclb (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrb (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    rclb $7, %dil # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrb $7, %dil # sched: [1:0.25]
-; ZNVER1-NEXT:    rclb $7, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrb $7, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rclb $7, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrb $7, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    rclb %cl, %dil # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrb %cl, %dil # sched: [1:0.25]
-; ZNVER1-NEXT:    rclb %cl, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrb %cl, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rclb %cl, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrb %cl, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "rclb $0 \0A\09 rcrb $0 \0A\09 rclb $2 \0A\09 rcrb $2 \0A\09 rclb $3, $0 \0A\09 rcrb $3, $0 \0A\09 rclb $3, $2 \0A\09 rcrb $3, $2 \0A\09 rclb %CL, $0 \0A\09 rcrb %CL, $0 \0A\09 rclb %CL, $2 \0A\09 rcrb %CL, $2", "r,r,*m,i"(i8 %a0, i8 %a1, i8 *%a2, i8 7)
   ret void
 }
 define void @test_rcl_rcr_16(i16 %a0, i16 %a1, i16 *%a2) optsize {
 ; GENERIC-LABEL: test_rcl_rcr_16:
 ; GENERIC:       # %bb.0:

 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_rcl_rcr_16:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    rclw %di # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrw %di # sched: [1:0.25]
-; ZNVER1-NEXT:    rclw (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrw (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rclw (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrw (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    rclw $7, %di # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrw $7, %di # sched: [1:0.25]
-; ZNVER1-NEXT:    rclw $7, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrw $7, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rclw $7, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrw $7, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    rclw %cl, %di # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrw %cl, %di # sched: [1:0.25]
-; ZNVER1-NEXT:    rclw %cl, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrw %cl, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rclw %cl, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrw %cl, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "rclw $0 \0A\09 rcrw $0 \0A\09 rclw $2 \0A\09 rcrw $2 \0A\09 rclw $3, $0 \0A\09 rcrw $3, $0 \0A\09 rclw $3, $2 \0A\09 rcrw $3, $2 \0A\09 rclw %CL, $0 \0A\09 rcrw %CL, $0 \0A\09 rclw %CL, $2 \0A\09 rcrw %CL, $2", "r,r,*m,i"(i16 %a0, i16 %a1, i16 *%a2, i8 7)
   ret void
 }
 define void @test_rcl_rcr_32(i32 %a0, i32 %a1, i32 *%a2) optsize {
 ; GENERIC-LABEL: test_rcl_rcr_32:
 ; GENERIC:       # %bb.0:

 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_rcl_rcr_32:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    rcll %edi # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrl %edi # sched: [1:0.25]
-; ZNVER1-NEXT:    rcll (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrl (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rcll (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrl (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    rcll $7, %edi # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrl $7, %edi # sched: [1:0.25]
-; ZNVER1-NEXT:    rcll $7, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrl $7, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rcll $7, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrl $7, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    rcll %cl, %edi # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrl %cl, %edi # sched: [1:0.25]
-; ZNVER1-NEXT:    rcll %cl, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrl %cl, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rcll %cl, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrl %cl, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "rcll $0 \0A\09 rcrl $0 \0A\09 rcll $2 \0A\09 rcrl $2 \0A\09 rcll $3, $0 \0A\09 rcrl $3, $0 \0A\09 rcll $3, $2 \0A\09 rcrl $3, $2 \0A\09 rcll %CL, $0 \0A\09 rcrl %CL, $0 \0A\09 rcll %CL, $2 \0A\09 rcrl %CL, $2", "r,r,*m,i"(i32 %a0, i32 %a1, i32 *%a2, i8 7)
   ret void
 }
 define void @test_rcl_rcr_64(i64 %a0, i64 %a1, i64 *%a2) optsize {
 ; GENERIC-LABEL: test_rcl_rcr_64:
 ; GENERIC:       # %bb.0:

 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_rcl_rcr_64:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    rclq %rdi # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrq %rdi # sched: [1:0.25]
-; ZNVER1-NEXT:    rclq (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrq (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rclq (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrq (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    rclq $7, %rdi # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrq $7, %rdi # sched: [1:0.25]
-; ZNVER1-NEXT:    rclq $7, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrq $7, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rclq $7, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrq $7, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    rclq %cl, %rdi # sched: [1:0.25]
 ; ZNVER1-NEXT:    rcrq %cl, %rdi # sched: [1:0.25]
-; ZNVER1-NEXT:    rclq %cl, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    rcrq %cl, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    rclq %cl, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    rcrq %cl, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "rclq $0 \0A\09 rcrq $0 \0A\09 rclq $2 \0A\09 rcrq $2 \0A\09 rclq $3, $0 \0A\09 rcrq $3, $0 \0A\09 rclq $3, $2 \0A\09 rcrq $3, $2 \0A\09 rclq %CL, $0 \0A\09 rcrq %CL, $0 \0A\09 rclq %CL, $2 \0A\09 rcrq %CL, $2", "r,r,*m,i"(i64 %a0, i64 %a1, i64 *%a2, i8 7)
   ret void
 }
 
 define void @test_rdmsr_wrmsr() optsize {
 ; GENERIC-LABEL: test_rdmsr_wrmsr:

 ; BTVER2-NEXT:    rdmsr # sched: [100:0.50]
 ; BTVER2-NEXT:    wrmsr # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_rdmsr_wrmsr:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    rdmsr # sched: [100:?]
-; ZNVER1-NEXT:    wrmsr # sched: [100:?]
+; ZNVER1-NEXT:    rdmsr # sched: [100:0.25]
+; ZNVER1-NEXT:    wrmsr # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "rdmsr \0A\09 wrmsr", ""()
   ret void
 }
 
 define void @test_rdpmc() optsize {
 ; GENERIC-LABEL: test_rdpmc:

 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    rdpmc # sched: [100:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_rdpmc:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    rdpmc # sched: [1:?]
+; HASWELL-NEXT:    rdpmc # sched: [1:8.50]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retq # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_rdpmc:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    rdpmc # sched: [100:0.25]
 ; BROADWELL-NEXT:    #NO_APP

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    rdpmc # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_rdpmc:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    rdpmc # sched: [100:?]
+; ZNVER1-NEXT:    rdpmc # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "rdpmc", ""()
   ret void
 }
 
 define void @test_rdtsc_rdtscp() optsize {
 ; GENERIC-LABEL: test_rdtsc_rdtscp:

 ; BTVER2-NEXT:    rdtsc # sched: [100:0.50]
 ; BTVER2-NEXT:    rdtscp # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_rdtsc_rdtscp:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    rdtsc # sched: [100:?]
-; ZNVER1-NEXT:    rdtscp # sched: [100:?]
+; ZNVER1-NEXT:    rdtsc # sched: [100:0.25]
+; ZNVER1-NEXT:    rdtscp # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "rdtsc \0A\09 rdtscp", ""()
   ret void
 }
 
 define void @test_ret() optsize {
 ; GENERIC-LABEL: test_ret:

 ; BTVER2-NEXT:    scasl %es:(%rdi), %eax # sched: [100:0.50]
 ; BTVER2-NEXT:    scasq %es:(%rdi), %rax # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_scas:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    scasb %es:(%rdi), %al # sched: [100:?]
-; ZNVER1-NEXT:    scasw %es:(%rdi), %ax # sched: [100:?]
-; ZNVER1-NEXT:    scasl %es:(%rdi), %eax # sched: [100:?]
-; ZNVER1-NEXT:    scasq %es:(%rdi), %rax # sched: [100:?]
+; ZNVER1-NEXT:    scasb %es:(%rdi), %al # sched: [100:0.25]
+; ZNVER1-NEXT:    scasw %es:(%rdi), %ax # sched: [100:0.25]
+; ZNVER1-NEXT:    scasl %es:(%rdi), %eax # sched: [100:0.25]
+; ZNVER1-NEXT:    scasq %es:(%rdi), %rax # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "scasb \0A\09 scasw \0A\09 scasl \0A\09 scasq", ""()
   ret void
 }
 
 define void @test_setcc(i8 %a0, i8 *%a1) optsize {
 ; GENERIC-LABEL: test_setcc:

 ; BTVER2-NEXT:    shldw $7, %si, (%rdx) # sched: [9:11.00]
 ; BTVER2-NEXT:    shrdw $7, %si, (%rdx) # sched: [9:11.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_shld_shrd_16:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    shldw %cl, %si, %di # sched: [100:?]
-; ZNVER1-NEXT:    shrdw %cl, %si, %di # sched: [100:?]
-; ZNVER1-NEXT:    shldw %cl, %si, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    shrdw %cl, %si, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    shldw %cl, %si, %di # sched: [100:0.25]
+; ZNVER1-NEXT:    shrdw %cl, %si, %di # sched: [100:0.25]
+; ZNVER1-NEXT:    shldw %cl, %si, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    shrdw %cl, %si, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    shldw $7, %si, %di # sched: [1:0.25]
 ; ZNVER1-NEXT:    shrdw $7, %si, %di # sched: [1:0.25]
 ; ZNVER1-NEXT:    shldw $7, %si, (%rdx) # sched: [5:0.50]
 ; ZNVER1-NEXT:    shrdw $7, %si, (%rdx) # sched: [5:0.50]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "shld $1, $0 \0A\09 shrd $1, $0 \0A\09 shld $1, $2 \0A\09 shrd $1, $2 \0A\09 shld $3, $1, $0 \0A\09 shrd $3, $1, $0 \0A\09 shld $3, $1, $2 \0A\09 shrd $3, $1, $2", "r,r,*m,i"(i16 %a0, i16 %a1, i16 *%a2, i8 7)
   ret void

 ; BTVER2-NEXT:    shldl $7, %esi, (%rdx) # sched: [9:11.00]
 ; BTVER2-NEXT:    shrdl $7, %esi, (%rdx) # sched: [9:11.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_shld_shrd_32:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    shldl %cl, %esi, %edi # sched: [100:?]
-; ZNVER1-NEXT:    shrdl %cl, %esi, %edi # sched: [100:?]
-; ZNVER1-NEXT:    shldl %cl, %esi, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    shrdl %cl, %esi, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    shldl %cl, %esi, %edi # sched: [100:0.25]
+; ZNVER1-NEXT:    shrdl %cl, %esi, %edi # sched: [100:0.25]
+; ZNVER1-NEXT:    shldl %cl, %esi, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    shrdl %cl, %esi, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    shldl $7, %esi, %edi # sched: [1:0.25]
 ; ZNVER1-NEXT:    shrdl $7, %esi, %edi # sched: [1:0.25]
 ; ZNVER1-NEXT:    shldl $7, %esi, (%rdx) # sched: [5:0.50]
 ; ZNVER1-NEXT:    shrdl $7, %esi, (%rdx) # sched: [5:0.50]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "shld $1, $0 \0A\09 shrd $1, $0 \0A\09 shld $1, $2 \0A\09 shrd $1, $2 \0A\09 shld $3, $1, $0 \0A\09 shrd $3, $1, $0 \0A\09 shld $3, $1, $2 \0A\09 shrd $3, $1, $2", "r,r,*m,i"(i32 %a0, i32 %a1, i32 *%a2, i8 7)
   ret void

 ; BTVER2-NEXT:    shldq $7, %rsi, (%rdx) # sched: [9:11.00]
 ; BTVER2-NEXT:    shrdq $7, %rsi, (%rdx) # sched: [9:11.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_shld_shrd_64:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    shldq %cl, %rsi, %rdi # sched: [100:?]
-; ZNVER1-NEXT:    shrdq %cl, %rsi, %rdi # sched: [100:?]
-; ZNVER1-NEXT:    shldq %cl, %rsi, (%rdx) # sched: [100:?]
-; ZNVER1-NEXT:    shrdq %cl, %rsi, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    shldq %cl, %rsi, %rdi # sched: [100:0.25]
+; ZNVER1-NEXT:    shrdq %cl, %rsi, %rdi # sched: [100:0.25]
+; ZNVER1-NEXT:    shldq %cl, %rsi, (%rdx) # sched: [100:0.25]
+; ZNVER1-NEXT:    shrdq %cl, %rsi, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    shldq $7, %rsi, %rdi # sched: [1:0.25]
 ; ZNVER1-NEXT:    shrdq $7, %rsi, %rdi # sched: [1:0.25]
 ; ZNVER1-NEXT:    shldq $7, %rsi, (%rdx) # sched: [5:0.50]
 ; ZNVER1-NEXT:    shrdq $7, %rsi, (%rdx) # sched: [5:0.50]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "shld $1, $0 \0A\09 shrd $1, $0 \0A\09 shld $1, $2 \0A\09 shrd $1, $2 \0A\09 shld $3, $1, $0 \0A\09 shrd $3, $1, $0 \0A\09 shld $3, $1, $2 \0A\09 shrd $3, $1, $2", "r,r,*m,i"(i64 %a0, i64 %a1, i64 *%a2, i8 7)
   ret void

 ; BTVER2-NEXT:    stosl %eax, %es:(%rdi) # sched: [100:0.50]
 ; BTVER2-NEXT:    stosq %rax, %es:(%rdi) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_stos:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    stosb %al, %es:(%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    stosw %ax, %es:(%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    stosl %eax, %es:(%rdi) # sched: [100:?]
-; ZNVER1-NEXT:    stosq %rax, %es:(%rdi) # sched: [100:?]
+; ZNVER1-NEXT:    stosb %al, %es:(%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    stosw %ax, %es:(%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    stosl %eax, %es:(%rdi) # sched: [100:0.25]
+; ZNVER1-NEXT:    stosq %rax, %es:(%rdi) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "stosb \0A\09 stosw \0A\09 stosl \0A\09 stosq", ""()
   ret void
 }
 
 ; TODO - test_str
 

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    ud2 # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_ud2:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    ud2 # sched: [100:?]
+; ZNVER1-NEXT:    ud2 # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void asm sideeffect "ud2", ""()
   ret void
 }
 
 ; TODO - test_verr
 ; TODO - test_verw

 ; BTVER2-NEXT:    xaddb %dil, (%rdx) # sched: [4:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_xadd_8:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    xaddb %dil, %sil # sched: [1:0.25]
-; ZNVER1-NEXT:    xaddb %dil, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    xaddb %dil, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "xaddb $0, $1 \0A\09 xaddb $0, $2", "r,r,*m"(i8 %a0, i8 %a1, i8 *%a2) nounwind
   ret void
 }
 define void @test_xadd_16(i16 %a0, i16 %a1, i16 *%a2) optsize {
 ; GENERIC-LABEL: test_xadd_16:
 ; GENERIC:       # %bb.0:

 ; BTVER2-NEXT:    xaddw %di, (%rdx) # sched: [4:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_xadd_16:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    xaddw %di, %si # sched: [1:0.25]
-; ZNVER1-NEXT:    xaddw %di, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    xaddw %di, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "xaddw $0, $1 \0A\09 xaddw $0, $2", "r,r,*m"(i16 %a0, i16 %a1, i16 *%a2) nounwind
   ret void
 }
 define void @test_xadd_32(i32 %a0, i32 %a1, i32 *%a2) optsize {
 ; GENERIC-LABEL: test_xadd_32:
 ; GENERIC:       # %bb.0:

 ; BTVER2-NEXT:    xaddl %edi, (%rdx) # sched: [4:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_xadd_32:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    xaddl %edi, %esi # sched: [1:0.25]
-; ZNVER1-NEXT:    xaddl %edi, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    xaddl %edi, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "xaddl $0, $1 \0A\09 xaddl $0, $2", "r,r,*m"(i32 %a0, i32 %a1, i32 *%a2) nounwind
   ret void
 }
 define void @test_xadd_64(i64 %a0, i64 %a1, i64 *%a2) optsize {
 ; GENERIC-LABEL: test_xadd_64:
 ; GENERIC:       # %bb.0:

 ; BTVER2-NEXT:    xaddq %rdi, (%rdx) # sched: [4:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_xadd_64:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    xaddq %rdi, %rsi # sched: [1:0.25]
-; ZNVER1-NEXT:    xaddq %rdi, (%rdx) # sched: [100:?]
+; ZNVER1-NEXT:    xaddq %rdi, (%rdx) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "xaddq $0, $1 \0A\09 xaddq $0, $2", "r,r,*m"(i64 %a0, i64 %a1, i64 *%a2) nounwind
   ret void
 }
 
 define void @test_xchg_8(i8 %a0, i8 %a1, i8 *%a2) optsize {
 ; GENERIC-LABEL: test_xchg_8:

 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    xlatb # sched: [5:0.50]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_xlat:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    xlatb # sched: [7:?]
+; HASWELL-NEXT:    xlatb # sched: [7:0.75]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retq # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_xlat:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    xlatb # sched: [5:0.50]
 ; BROADWELL-NEXT:    #NO_APP

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    xlatb # sched: [5:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_xlat:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    xlatb # sched: [100:?]
+; ZNVER1-NEXT:    xlatb # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "xlat", ""() nounwind
   ret void
 }
 
 define void @test_xor_8(i8 %a0, i8* %a1) optsize {
 ; GENERIC-LABEL: test_xor_8:

llvm/trunk/test/CodeGen/X86/sha-schedule.ll

 ; CANNONLAKE-LABEL: test_sha256msg2:
 ; CANNONLAKE:       # %bb.0:
 ; CANNONLAKE-NEXT:    sha256msg2 %xmm1, %xmm0 # sched: [4:0.33]
 ; CANNONLAKE-NEXT:    sha256msg2 (%rdi), %xmm0 # sched: [10:0.50]
 ; CANNONLAKE-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_sha256msg2:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    sha256msg2 %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    sha256msg2 (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    sha256msg2 %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    sha256msg2 (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = load <4 x i32>, <4 x i32>* %a2
   %2 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a0, <4 x i32> %a1)
   %3 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %2, <4 x i32> %1)
   ret <4 x i32> %3
 }
 declare <4 x i32> @llvm.x86.sha256msg2(<4 x i32>, <4 x i32>)
 

llvm/trunk/test/CodeGen/X86/sse-schedule.ll

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:1.00]
 ; BTVER2-NEXT:    vldmxcsr -{{[0-9]+}}(%rsp) # sched: [5:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_ldmxcsr:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:0.50]
-; ZNVER1-SSE-NEXT:    ldmxcsr -{{[0-9]+}}(%rsp) # sched: [100:?]
+; ZNVER1-SSE-NEXT:    ldmxcsr -{{[0-9]+}}(%rsp) # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_ldmxcsr:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:0.50]
-; ZNVER1-NEXT:    vldmxcsr -{{[0-9]+}}(%rsp) # sched: [100:?]
+; ZNVER1-NEXT:    vldmxcsr -{{[0-9]+}}(%rsp) # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = alloca i32, align 4
   %2 = bitcast i32* %1 to i8*
   store i32 %a0, i32* %1
   call void @llvm.x86.sse.ldmxcsr(i8* %2)
   ret void
 }
 declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind readnone

 ; BTVER2-LABEL: test_stmxcsr:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vstmxcsr -{{[0-9]+}}(%rsp) # sched: [1:1.00]
 ; BTVER2-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [5:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_stmxcsr:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    stmxcsr -{{[0-9]+}}(%rsp) # sched: [100:?]
+; ZNVER1-SSE-NEXT:    stmxcsr -{{[0-9]+}}(%rsp) # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [8:0.50]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_stmxcsr:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vstmxcsr -{{[0-9]+}}(%rsp) # sched: [100:?]
+; ZNVER1-NEXT:    vstmxcsr -{{[0-9]+}}(%rsp) # sched: [100:0.25]
 ; ZNVER1-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = alloca i32, align 4
   %2 = bitcast i32* %1 to i8*
   call void @llvm.x86.sse.stmxcsr(i8* %2)
   %3 = load i32, i32* %1, align 4
   ret i32 %3
 }

 }
 
 ; 'WriteZero' and 'WriteNop' class instructions.
 
 define <4 x float> @test_fnop() nounwind {
 ; GENERIC-LABEL: test_fnop:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
-; GENERIC-NEXT:    nop # sched: [1:?]
+; GENERIC-NEXT:    nop # sched: [1:0.25]
 ; GENERIC-NEXT:    #NO_APP
 ; GENERIC-NEXT:    xorps %xmm0, %xmm0 # sched: [1:1.00]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; ATOM-LABEL: test_fnop:
 ; ATOM:       # %bb.0:
 ; ATOM-NEXT:    xorps %xmm0, %xmm0 # sched: [1:0.50]
 ; ATOM-NEXT:    #APP
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    #NO_APP
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    retq # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_fnop:
 ; SLM:       # %bb.0:
 ; SLM-NEXT:    xorps %xmm0, %xmm0 # sched: [1:0.50]
 ; SLM-NEXT:    #APP
-; SLM-NEXT:    nop # sched: [1:?]
+; SLM-NEXT:    nop # sched: [1:0.50]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-SSE-LABEL: test_fnop:
 ; SANDY-SSE:       # %bb.0:
 ; SANDY-SSE-NEXT:    #APP
-; SANDY-SSE-NEXT:    nop # sched: [1:?]
+; SANDY-SSE-NEXT:    nop # sched: [1:0.25]
 ; SANDY-SSE-NEXT:    #NO_APP
 ; SANDY-SSE-NEXT:    xorps %xmm0, %xmm0 # sched: [1:1.00]
 ; SANDY-SSE-NEXT:    retq # sched: [1:1.00]
 ;
 ; SANDY-LABEL: test_fnop:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
-; SANDY-NEXT:    nop # sched: [1:?]
+; SANDY-NEXT:    nop # sched: [1:0.25]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    vxorps %xmm0, %xmm0, %xmm0 # sched: [1:1.00]
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-SSE-LABEL: test_fnop:
 ; HASWELL-SSE:       # %bb.0:
 ; HASWELL-SSE-NEXT:    #APP
 ; HASWELL-SSE-NEXT:    nop # sched: [1:0.25]

 ; SKX-NEXT:    #APP
 ; SKX-NEXT:    nop # sched: [1:0.25]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    vxorps %xmm0, %xmm0, %xmm0 # sched: [1:0.33]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_fnop:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    xorps %xmm0, %xmm0 # sched: [0:?]
+; BTVER2-SSE-NEXT:    xorps %xmm0, %xmm0 # sched: [0:0.50]
 ; BTVER2-SSE-NEXT:    #APP
 ; BTVER2-SSE-NEXT:    nop # sched: [1:0.50]
 ; BTVER2-SSE-NEXT:    #NO_APP
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_fnop:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vxorps %xmm0, %xmm0, %xmm0 # sched: [0:?]
+; BTVER2-NEXT:    vxorps %xmm0, %xmm0, %xmm0 # sched: [0:0.50]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    nop # sched: [1:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_fnop:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    xorps %xmm0, %xmm0 # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    #APP
-; ZNVER1-SSE-NEXT:    nop # sched: [1:?]
+; ZNVER1-SSE-NEXT:    nop # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    #NO_APP
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_fnop:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vxorps %xmm0, %xmm0, %xmm0 # sched: [1:0.25]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    nop # sched: [1:?]
+; ZNVER1-NEXT:    nop # sched: [1:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm sideeffect "nop", ""() nounwind
   ret <4 x float> zeroinitializer
 }
 
 !0 = !{i32 1}

llvm/trunk/test/CodeGen/X86/sse2-schedule.ll

 ;
 ; BTVER2-LABEL: test_maskmovdqu:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_maskmovdqu:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    maskmovdqu %xmm1, %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    maskmovdqu %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_maskmovdqu:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vmaskmovdqu %xmm1, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vmaskmovdqu %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   call void @llvm.x86.sse2.maskmov.dqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2)
   ret void
 }
 declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind
 
 define <2 x double> @test_maxpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
 ; GENERIC-LABEL: test_maxpd:

llvm/trunk/test/CodeGen/X86/sse3-schedule.ll

 ; BTVER2-LABEL: test_haddpd:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_haddpd:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    haddpd %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    haddpd (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    haddpd %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    haddpd (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_haddpd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1)
   %2 = load <2 x double>, <2 x double> *%a2, align 16
   %3 = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %1, <2 x double> %2)
   ret <2 x double> %3
 }
 declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone
 

 ; BTVER2-LABEL: test_haddps:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vhaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_haddps:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    haddps %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    haddps (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    haddps %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    haddps (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_haddps:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vhaddps %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vhaddps %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1)
   %2 = load <4 x float>, <4 x float> *%a2, align 16
   %3 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %1, <4 x float> %2)
   ret <4 x float> %3
 }
 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
 

 ; BTVER2-LABEL: test_hsubpd:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_hsubpd:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    hsubpd %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    hsubpd (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    hsubpd %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    hsubpd (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_hsubpd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
   %2 = load <2 x double>, <2 x double> *%a2, align 16
   %3 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %1, <2 x double> %2)
   ret <2 x double> %3
 }
 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
 

 ; BTVER2-LABEL: test_hsubps:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vhsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_hsubps:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    hsubps %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    hsubps (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    hsubps %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    hsubps (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_hsubps:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vhsubps %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vhsubps %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
   %2 = load <4 x float>, <4 x float> *%a2, align 16
   %3 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %1, <4 x float> %2)
   ret <4 x float> %3
 }
 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
 

 ; BTVER2-NEXT:    movl %esi, %ecx # sched: [1:0.50]
 ; BTVER2-NEXT:    monitor # sched: [100:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_monitor:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    leaq (%rdi), %rax # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    movl %esi, %ecx # sched: [1:0.25]
-; ZNVER1-SSE-NEXT:    monitor # sched: [100:?]
+; ZNVER1-SSE-NEXT:    monitor # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_monitor:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    leaq (%rdi), %rax # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl %esi, %ecx # sched: [1:0.25]
-; ZNVER1-NEXT:    monitor # sched: [100:?]
+; ZNVER1-NEXT:    monitor # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void @llvm.x86.sse3.monitor(i8* %a0, i32 %a1, i32 %a2)
   ret void
 }
 declare void @llvm.x86.sse3.monitor(i8*, i32, i32)
 
 define <2 x double> @test_movddup(<2 x double> %a0, <2 x double> *%a1) {
 ; GENERIC-LABEL: test_movddup:

 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [6:1.00]
 ; BTVER2-NEXT:    vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:0.50]
 ; BTVER2-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_movsldup:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    movsldup {{.*#+}} xmm1 = xmm0[0,0,2,2] sched: [100:?]
-; ZNVER1-SSE-NEXT:    movsldup {{.*#+}} xmm0 = mem[0,0,2,2] sched: [100:?]
+; ZNVER1-SSE-NEXT:    movsldup {{.*#+}} xmm1 = xmm0[0,0,2,2] sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    movsldup {{.*#+}} xmm0 = mem[0,0,2,2] sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    addps %xmm1, %xmm0 # sched: [3:1.00]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_movsldup:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [8:0.50]
 ; ZNVER1-NEXT:    vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:0.50]
 ; ZNVER1-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]

 ; BTVER2-NEXT:    movl %esi, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    mwait # sched: [100:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_mwait:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    movl %edi, %ecx # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    movl %esi, %eax # sched: [1:0.25]
-; ZNVER1-SSE-NEXT:    mwait # sched: [100:?]
+; ZNVER1-SSE-NEXT:    mwait # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_mwait:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl %edi, %ecx # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl %esi, %eax # sched: [1:0.25]
-; ZNVER1-NEXT:    mwait # sched: [100:?]
+; ZNVER1-NEXT:    mwait # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void @llvm.x86.sse3.mwait(i32 %a0, i32 %a1)
   ret void
 }
 declare void @llvm.x86.sse3.mwait(i32, i32)

llvm/trunk/test/CodeGen/X86/sse41-schedule.ll

 ; BTVER2-LABEL: test_dppd:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vdppd $7, %xmm1, %xmm0, %xmm0 # sched: [9:3.00]
 ; BTVER2-NEXT:    vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [14:3.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_dppd:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    dppd $7, %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    dppd $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    dppd $7, %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    dppd $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_dppd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vdppd $7, %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vdppd $7, %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i8 7)
   %2 = load <2 x double>, <2 x double> *%a2, align 16
   %3 = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %1, <2 x double> %2, i8 7)
   ret <2 x double> %3
 }
 declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i8) nounwind readnone
 

 ; BTVER2-LABEL: test_dpps:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [11:3.00]
 ; BTVER2-NEXT:    vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [16:3.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_dpps:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    dpps $7, %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    dpps $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    dpps $7, %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    dpps $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_dpps:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i8 7)
   %2 = load <4 x float>, <4 x float> *%a2, align 16
   %3 = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %1, <4 x float> %2, i8 7)
   ret <4 x float> %3
 }
 declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8) nounwind readnone
 

 ; BTVER2-LABEL: test_mpsadbw:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vmpsadbw $7, %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [8:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_mpsadbw:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    mpsadbw $7, %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    mpsadbw $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    mpsadbw $7, %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    mpsadbw $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_mpsadbw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vmpsadbw $7, %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vmpsadbw $7, %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7)
   %2 = bitcast <8 x i16> %1 to <16 x i8>
   %3 = load <16 x i8>, <16 x i8> *%a2, align 16
   %4 = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %2, <16 x i8> %3, i8 7)
   ret <8 x i16> %4
 }
 declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8) nounwind readnone

llvm/trunk/test/CodeGen/X86/sse42-schedule.ll

 ; BTVER2-NEXT:    # kill: def $ecx killed $ecx def $rcx
 ; BTVER2-NEXT:    leal (%rcx,%rsi), %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_pcmpestri:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    movl $7, %eax # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    movl $7, %edx # sched: [1:0.25]
-; ZNVER1-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    movl $7, %eax # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    movl $7, %edx # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    movl %ecx, %esi # sched: [1:0.25]
-; ZNVER1-SSE-NEXT:    pcmpestri $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    pcmpestri $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    # kill: def $ecx killed $ecx def $rcx
 ; ZNVER1-SSE-NEXT:    leal (%rcx,%rsi), %eax # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_pcmpestri:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl $7, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl $7, %edx # sched: [1:0.25]
-; ZNVER1-NEXT:    vpcmpestri $7, %xmm1, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpcmpestri $7, %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movl $7, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl $7, %edx # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl %ecx, %esi # sched: [1:0.25]
-; ZNVER1-NEXT:    vpcmpestri $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpcmpestri $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    # kill: def $ecx killed $ecx def $rcx
 ; ZNVER1-NEXT:    leal (%rcx,%rsi), %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %a0, i32 7, <16 x i8> %a1, i32 7, i8 7)
   %2 = load <16 x i8>, <16 x i8> *%a2, align 16
   %3 = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %a0, i32 7, <16 x i8> %2, i32 7, i8 7)
   %4 = add i32 %1, %3
   ret i32 %4

 ; BTVER2-NEXT:    movl $7, %edx # sched: [1:0.50]
 ; BTVER2-NEXT:    vpcmpestrm $7, (%rdi), %xmm0 # sched: [19:5.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_pcmpestrm:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    movl $7, %eax # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    movl $7, %edx # sched: [1:0.25]
-; ZNVER1-SSE-NEXT:    pcmpestrm $7, %xmm1, %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    pcmpestrm $7, %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    movl $7, %eax # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    movl $7, %edx # sched: [1:0.25]
-; ZNVER1-SSE-NEXT:    pcmpestrm $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    pcmpestrm $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_pcmpestrm:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl $7, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl $7, %edx # sched: [1:0.25]
-; ZNVER1-NEXT:    vpcmpestrm $7, %xmm1, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpcmpestrm $7, %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movl $7, %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    movl $7, %edx # sched: [1:0.25]
-; ZNVER1-NEXT:    vpcmpestrm $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpcmpestrm $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %a1, i32 7, i8 7)
   %2 = load <16 x i8>, <16 x i8> *%a2, align 16
   %3 = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %1, i32 7, <16 x i8> %2, i32 7, i8 7)
   ret <16 x i8> %3
 }
 declare <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
 

 ; BTVER2-NEXT:    movl %ecx, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    vpcmpistri $7, (%rdi), %xmm0 # sched: [12:2.00]
 ; BTVER2-NEXT:    # kill: def $ecx killed $ecx def $rcx
 ; BTVER2-NEXT:    leal (%rcx,%rax), %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_pcmpistri:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    pcmpistri $7, %xmm1, %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    pcmpistri $7, %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    movl %ecx, %eax # sched: [1:0.25]
-; ZNVER1-SSE-NEXT:    pcmpistri $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    pcmpistri $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    # kill: def $ecx killed $ecx def $rcx
 ; ZNVER1-SSE-NEXT:    leal (%rcx,%rax), %eax # sched: [1:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_pcmpistri:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpcmpistri $7, %xmm1, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpcmpistri $7, %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movl %ecx, %eax # sched: [1:0.25]
-; ZNVER1-NEXT:    vpcmpistri $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpcmpistri $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    # kill: def $ecx killed $ecx def $rcx
 ; ZNVER1-NEXT:    leal (%rcx,%rax), %eax # sched: [1:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %a0, <16 x i8> %a1, i8 7)
   %2 = load <16 x i8>, <16 x i8> *%a2, align 16
   %3 = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %a0, <16 x i8> %2, i8 7)
   %4 = add i32 %1, %3
   ret i32 %4

 ; BTVER2-LABEL: test_pcmpistrm:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vpcmpistrm $7, %xmm1, %xmm0 # sched: [8:2.00]
 ; BTVER2-NEXT:    vpcmpistrm $7, (%rdi), %xmm0 # sched: [13:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_pcmpistrm:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    pcmpistrm $7, %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    pcmpistrm $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    pcmpistrm $7, %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    pcmpistrm $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_pcmpistrm:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpcmpistrm $7, %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vpcmpistrm $7, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpcmpistrm $7, %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vpcmpistrm $7, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1, i8 7)
   %2 = load <16 x i8>, <16 x i8> *%a2, align 16
   %3 = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %1, <16 x i8> %2, i8 7)
   ret <16 x i8> %3
 }
 declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8) nounwind readnone
 

 ; BTVER2-LABEL: test_pclmulqdq:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
 ; BTVER2-NEXT:    vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_pclmulqdq:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    pclmulqdq $0, %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    pclmulqdq $0, (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    pclmulqdq $0, %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    pclmulqdq $0, (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_pclmulqdq:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = load <2 x i64>, <2 x i64> *%a2, align 16
   %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, i8 0)
   %3 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %2, i8 0)
   ret <2 x i64> %3
 }
 declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8)

llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll

 ; BTVER2-LABEL: test_phaddd:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vphaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    vphaddd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phaddd:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    phaddd %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    phaddd (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    phaddd %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    phaddd (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_phaddd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphaddd %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphaddd (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphaddd %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphaddd (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1)
   %2 = load <4 x i32>, <4 x i32> *%a2, align 16
   %3 = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %1, <4 x i32> %2)
   ret <4 x i32> %3
 }
 declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
 

 ; BTVER2-LABEL: test_phaddsw:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vphaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    vphaddsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phaddsw:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    phaddsw %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    phaddsw (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    phaddsw %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    phaddsw (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_phaddsw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphaddsw %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphaddsw (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphaddsw %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphaddsw (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1)
   %2 = load <8 x i16>, <8 x i16> *%a2, align 16
   %3 = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %1, <8 x i16> %2)
   ret <8 x i16> %3
 }
 declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
 

 ; BTVER2-LABEL: test_phaddw:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vphaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    vphaddw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phaddw:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    phaddw %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    phaddw (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    phaddw %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    phaddw (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_phaddw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphaddw %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphaddw (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphaddw %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphaddw (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1)
   %2 = load <8 x i16>, <8 x i16> *%a2, align 16
   %3 = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %1, <8 x i16> %2)
   ret <8 x i16> %3
 }
 declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind readnone
 

 ; BTVER2-LABEL: test_phsubd:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vphsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    vphsubd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phsubd:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    phsubd %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    phsubd (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    phsubd %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    phsubd (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_phsubd:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphsubd %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphsubd (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphsubd %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphsubd (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1)
   %2 = load <4 x i32>, <4 x i32> *%a2, align 16
   %3 = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %1, <4 x i32> %2)
   ret <4 x i32> %3
 }
 declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind readnone
 

 ; BTVER2-LABEL: test_phsubsw:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vphsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    vphsubsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phsubsw:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    phsubsw %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    phsubsw (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    phsubsw %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    phsubsw (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_phsubsw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphsubsw %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphsubsw (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphsubsw %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphsubsw (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1)
   %2 = load <8 x i16>, <8 x i16> *%a2, align 16
   %3 = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %1, <8 x i16> %2)
   ret <8 x i16> %3
 }
 declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
 

 ; BTVER2-LABEL: test_phsubw:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vphsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    vphsubw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phsubw:
 ; ZNVER1-SSE:       # %bb.0:
-; ZNVER1-SSE-NEXT:    phsubw %xmm1, %xmm0 # sched: [100:?]
-; ZNVER1-SSE-NEXT:    phsubw (%rdi), %xmm0 # sched: [100:?]
+; ZNVER1-SSE-NEXT:    phsubw %xmm1, %xmm0 # sched: [100:0.25]
+; ZNVER1-SSE-NEXT:    phsubw (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_phsubw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vphsubw %xmm1, %xmm0, %xmm0 # sched: [100:?]
-; ZNVER1-NEXT:    vphsubw (%rdi), %xmm0, %xmm0 # sched: [100:?]
+; ZNVER1-NEXT:    vphsubw %xmm1, %xmm0, %xmm0 # sched: [100:0.25]
+; ZNVER1-NEXT:    vphsubw (%rdi), %xmm0, %xmm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1)
   %2 = load <8 x i16>, <8 x i16> *%a2, align 16
   %3 = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %1, <8 x i16> %2)
   ret <8 x i16> %3
 }
 declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind readnone
 

llvm/trunk/test/CodeGen/X86/x87-schedule.ll

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    f2xm1 # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_f2xm1:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    f2xm1 # sched: [100:?]
+; ZNVER1-NEXT:    f2xm1 # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "f2xm1", ""() nounwind
   ret void
 }
 
 define void @test_fabs() optsize {
 ; GENERIC-LABEL: test_fabs:

 ; SANDY-NEXT:    fbstp (%eax) # sched: [100:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_fbld_fbstp:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    fbld (%eax) # sched: [47:?]
+; HASWELL-NEXT:    fbld (%eax) # sched: [47:10.75]
 ; HASWELL-NEXT:    fbstp (%eax) # sched: [1:1.00]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_fbld_fbstp:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; BROADWELL-NEXT:    #APP

 ; BTVER2-NEXT:    fbstp (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fbld_fbstp:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fbld (%eax) # sched: [100:?]
-; ZNVER1-NEXT:    fbstp (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    fbld (%eax) # sched: [100:0.25]
+; ZNVER1-NEXT:    fbstp (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fbld $0 \0A\09 fbstp $0", "*m"(i8 *%a0) nounwind
   ret void
 }
 
 define void @test_fchs() optsize {
 ; GENERIC-LABEL: test_fchs:

 ; BTVER2-NEXT:    fnclex # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fclex:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    wait # sched: [1:1.00]
-; ZNVER1-NEXT:    fnclex # sched: [100:?]
+; ZNVER1-NEXT:    fnclex # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fclex", ""() nounwind
   ret void
 }
 
 define void @test_fnclex() optsize {
 ; GENERIC-LABEL: test_fnclex:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fnclex # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fnclex:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fnclex # sched: [100:?]
+; ZNVER1-NEXT:    fnclex # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fnclex", ""() nounwind
   ret void
 }
 
 define void @test_fcmov() optsize {
 ; GENERIC-LABEL: test_fcmov:

 ; BTVER2-NEXT:    fcmovnu %st(1), %st(0) # sched: [3:1.00]
 ; BTVER2-NEXT:    fcmovu %st(1), %st(0) # sched: [3:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fcmov:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fcmovb %st(1), %st(0) # sched: [100:?]
-; ZNVER1-NEXT:    fcmovbe %st(1), %st(0) # sched: [100:?]
-; ZNVER1-NEXT:    fcmove %st(1), %st(0) # sched: [100:?]
-; ZNVER1-NEXT:    fcmovnb %st(1), %st(0) # sched: [100:?]
-; ZNVER1-NEXT:    fcmovnbe %st(1), %st(0) # sched: [100:?]
-; ZNVER1-NEXT:    fcmovne %st(1), %st(0) # sched: [100:?]
-; ZNVER1-NEXT:    fcmovnu %st(1), %st(0) # sched: [100:?]
-; ZNVER1-NEXT:    fcmovu %st(1), %st(0) # sched: [100:?]
+; ZNVER1-NEXT:    fcmovb %st(1), %st(0) # sched: [100:0.25]
+; ZNVER1-NEXT:    fcmovbe %st(1), %st(0) # sched: [100:0.25]
+; ZNVER1-NEXT:    fcmove %st(1), %st(0) # sched: [100:0.25]
+; ZNVER1-NEXT:    fcmovnb %st(1), %st(0) # sched: [100:0.25]
+; ZNVER1-NEXT:    fcmovnbe %st(1), %st(0) # sched: [100:0.25]
+; ZNVER1-NEXT:    fcmovne %st(1), %st(0) # sched: [100:0.25]
+; ZNVER1-NEXT:    fcmovnu %st(1), %st(0) # sched: [100:0.25]
+; ZNVER1-NEXT:    fcmovu %st(1), %st(0) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fcmovb %st(1), %st(0) \0A\09 fcmovbe %st(1), %st(0) \0A\09 fcmove %st(1), %st(0) \0A\09 fcmovnb %st(1), %st(0) \0A\09 fcmovnbe %st(1), %st(0) \0A\09 fcmovne %st(1), %st(0) \0A\09 fcmovnu %st(1), %st(0) \0A\09 fcmovu %st(1), %st(0)", ""() nounwind
   ret void
 }
 
 define void @test_fcom(float *%a0, double *%a1) optsize {
 ; GENERIC-LABEL: test_fcom:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fcos # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fcos:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fcos # sched: [100:?]
+; ZNVER1-NEXT:    fcos # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fcos", ""() nounwind
   ret void
 }
 
 define void @test_fdecstp() optsize {
 ; GENERIC-LABEL: test_fdecstp:

 ; BTVER2-NEXT:    fninit # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_finit:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    wait # sched: [1:1.00]
-; ZNVER1-NEXT:    fninit # sched: [100:?]
+; ZNVER1-NEXT:    fninit # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "finit", ""() nounwind
   ret void
 }
 
 define void @test_fninit() optsize {
 ; GENERIC-LABEL: test_fninit:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fninit # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fninit:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fninit # sched: [100:?]
+; ZNVER1-NEXT:    fninit # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fninit", ""() nounwind
   ret void
 }
 
 define void @test_fist_fistp_fisttp(i16* %a0, i32* %a1, i64 *%a2) optsize {
 ; GENERIC-LABEL: test_fist_fistp_fisttp:

 ; BTVER2-NEXT:    fldenv (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fldcw_fldenv:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fldcw (%eax) # sched: [100:?]
-; ZNVER1-NEXT:    fldenv (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    fldcw (%eax) # sched: [100:0.25]
+; ZNVER1-NEXT:    fldenv (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fldcw $0 \0A\09 fldenv $0", "*m"(i8* %a0) nounwind
   ret void
 }
 
 define void @test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz() optsize {
 ; GENERIC-LABEL: test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz:

 ; ATOM-NEXT:    #APP
 ; ATOM-NEXT:    fnop # sched: [1:0.50]
 ; ATOM-NEXT:    #NO_APP
 ; ATOM-NEXT:    retl # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_fnop:
 ; SLM:       # %bb.0:
 ; SLM-NEXT:    #APP
-; SLM-NEXT:    fnop # sched: [1:?]
+; SLM-NEXT:    fnop # sched: [1:0.50]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retl # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_fnop:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    fnop # sched: [1:1.00]
 ; SANDY-NEXT:    #NO_APP

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fpatan # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fpatan:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fpatan # sched: [100:?]
+; ZNVER1-NEXT:    fpatan # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fpatan", ""() nounwind
   ret void
 }
 
 define void @test_fprem_fprem1() optsize {
 ; GENERIC-LABEL: test_fprem_fprem1:

 ; SANDY-NEXT:    fprem # sched: [100:0.33]
 ; SANDY-NEXT:    fprem1 # sched: [100:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_fprem_fprem1:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    fprem # sched: [19:?]
-; HASWELL-NEXT:    fprem1 # sched: [27:?]
+; HASWELL-NEXT:    fprem # sched: [19:7.00]
+; HASWELL-NEXT:    fprem1 # sched: [27:10.25]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_fprem_fprem1:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    fprem # sched: [100:0.25]
 ; BROADWELL-NEXT:    fprem1 # sched: [100:0.25]

 ; BTVER2-NEXT:    fprem # sched: [100:0.50]
 ; BTVER2-NEXT:    fprem1 # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fprem_fprem1:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fprem # sched: [100:?]
-; ZNVER1-NEXT:    fprem1 # sched: [100:?]
+; ZNVER1-NEXT:    fprem # sched: [100:0.25]
+; ZNVER1-NEXT:    fprem1 # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fprem \0A\09 fprem1", ""() nounwind
   ret void
 }
 
 define void @test_fptan() optsize {
 ; GENERIC-LABEL: test_fptan:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fptan # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fptan:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fptan # sched: [100:?]
+; ZNVER1-NEXT:    fptan # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fptan", ""() nounwind
   ret void
 }
 
 define void @test_frndint() optsize {
 ; GENERIC-LABEL: test_frndint:

 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    frndint # sched: [100:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_frndint:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    frndint # sched: [11:?]
+; HASWELL-NEXT:    frndint # sched: [11:4.25]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_frndint:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    frndint # sched: [100:0.25]
 ; BROADWELL-NEXT:    #NO_APP

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    frndint # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_frndint:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    frndint # sched: [100:?]
+; ZNVER1-NEXT:    frndint # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "frndint", ""() nounwind
   ret void
 }
 
 define void @test_frstor(i8* %a0) optsize {
 ; GENERIC-LABEL: test_frstor:

 ; SANDY-NEXT:    frstor (%eax) # sched: [100:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_frstor:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    frstor (%eax) # sched: [1:?]
+; HASWELL-NEXT:    frstor (%eax) # sched: [1:22.50]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_frstor:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    frstor (%eax) # sched: [100:0.25]

 ; BTVER2-NEXT:    frstor (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_frstor:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    frstor (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    frstor (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "frstor $0", "*m"(i8* %a0) nounwind
   ret void
 }
 
 define void @test_fsave(i8* %a0) optsize {
 ; GENERIC-LABEL: test_fsave:

 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_fsave:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    wait # sched: [2:0.50]
-; HASWELL-NEXT:    fnsave (%eax) # sched: [1:?]
+; HASWELL-NEXT:    fnsave (%eax) # sched: [1:36.75]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_fsave:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    wait # sched: [2:0.50]

 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fsave:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    wait # sched: [1:1.00]
-; ZNVER1-NEXT:    fnsave (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    fnsave (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fsave $0", "*m"(i8* %a0) nounwind
   ret void
 }
 
 define void @test_fnsave(i8* %a0) optsize {
 ; GENERIC-LABEL: test_fnsave:

 ; SANDY-NEXT:    fnsave (%eax) # sched: [100:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_fnsave:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    fnsave (%eax) # sched: [1:?]
+; HASWELL-NEXT:    fnsave (%eax) # sched: [1:36.75]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_fnsave:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    fnsave (%eax) # sched: [100:0.25]

 ; BTVER2-NEXT:    fnsave (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fnsave:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fnsave (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    fnsave (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fnsave $0", "*m"(i8* %a0) nounwind
   ret void
 }
 
 define void @test_fscale() optsize {
 ; GENERIC-LABEL: test_fscale:

 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    fscale # sched: [100:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_fscale:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    fscale # sched: [75:?]
+; HASWELL-NEXT:    fscale # sched: [75:12.50]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_fscale:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    fscale # sched: [100:0.25]
 ; BROADWELL-NEXT:    #NO_APP

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fscale # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fscale:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fscale # sched: [100:?]
+; ZNVER1-NEXT:    fscale # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fscale", ""() nounwind
   ret void
 }
 
 define void @test_fsin() optsize {
 ; GENERIC-LABEL: test_fsin:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fsin # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fsin:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fsin # sched: [100:?]
+; ZNVER1-NEXT:    fsin # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fsin", ""() nounwind
   ret void
 }
 
 define void @test_fsincos() optsize {
 ; GENERIC-LABEL: test_fsincos:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fsincos # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fsincos:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fsincos # sched: [100:?]
+; ZNVER1-NEXT:    fsincos # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fsincos", ""() nounwind
   ret void
 }
 
 define void @test_fsqrt() optsize {
 ; GENERIC-LABEL: test_fsqrt:

 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fstcw_fstenv_fstsw:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    wait # sched: [1:1.00]
-; ZNVER1-NEXT:    fnstcw (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    fnstcw (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    wait # sched: [1:1.00]
-; ZNVER1-NEXT:    fnstenv (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    fnstenv (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    wait # sched: [1:1.00]
-; ZNVER1-NEXT:    fnstsw (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    fnstsw (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fstcw $0 \0A\09 fstenv $0 \0A\09 fstsw $0", "*m"(i8* %a0) nounwind
   ret void
 }
 
 define void @test_fnstcw_fnstenv_fnstsw(i8* %a0) optsize {
 ; GENERIC-LABEL: test_fnstcw_fnstenv_fnstsw:

 ; BTVER2-NEXT:    fnstsw (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fnstcw_fnstenv_fnstsw:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fnstcw (%eax) # sched: [100:?]
-; ZNVER1-NEXT:    fnstenv (%eax) # sched: [100:?]
-; ZNVER1-NEXT:    fnstsw (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    fnstcw (%eax) # sched: [100:0.25]
+; ZNVER1-NEXT:    fnstenv (%eax) # sched: [100:0.25]
+; ZNVER1-NEXT:    fnstsw (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fnstcw $0 \0A\09 fnstenv $0 \0A\09 fnstsw $0", "*m"(i8* %a0) nounwind
   ret void
 }
 
 define void @test_fsub(float *%a0, double *%a1) optsize {
 ; GENERIC-LABEL: test_fsub:

 ; BTVER2-NEXT:    fxsave (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fxrstor_fxsave:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fxrstor (%eax) # sched: [100:?]
-; ZNVER1-NEXT:    fxsave (%eax) # sched: [100:?]
+; ZNVER1-NEXT:    fxrstor (%eax) # sched: [100:0.25]
+; ZNVER1-NEXT:    fxsave (%eax) # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fxrstor $0 \0A\09 fxsave $0", "*m"(i8 *%a0) nounwind
   ret void
 }
 
 define void @test_fxtract() optsize {
 ; GENERIC-LABEL: test_fxtract:

 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    fxtract # sched: [100:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_fxtract:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    fxtract # sched: [15:?]
+; HASWELL-NEXT:    fxtract # sched: [15:4.25]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_fxtract:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    fxtract # sched: [100:0.25]
 ; BROADWELL-NEXT:    #NO_APP

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fxtract # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fxtract:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fxtract # sched: [100:?]
+; ZNVER1-NEXT:    fxtract # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fxtract", ""() nounwind
   ret void
 }
 
 define void @test_fyl2x() optsize {
 ; GENERIC-LABEL: test_fyl2x:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fyl2x # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fyl2x:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fyl2x # sched: [100:?]
+; ZNVER1-NEXT:    fyl2x # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fyl2x", ""() nounwind
   ret void
 }
 
 define void @test_fyl2xp1() optsize {
 ; GENERIC-LABEL: test_fyl2xp1:

 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fyl2xp1 # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fyl2xp1:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    fyl2xp1 # sched: [100:?]
+; ZNVER1-NEXT:    fyl2xp1 # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retl # sched: [1:0.50]
   tail call void asm sideeffect "fyl2xp1", ""() nounwind
   ret void
 }

llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s

 # ALL-NEXT: [1]: #uOps
 # ALL-NEXT: [2]: Latency
 # ALL-NEXT: [3]: RThroughput
 # ALL-NEXT: [4]: MayLoad
 # ALL-NEXT: [5]: MayStore
 # ALL-NEXT: [6]: HasSideEffects
 
 # ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# ALL-NEXT:  1      0      -                          b t
+
+# M1-NEXT:   1      0     0.25                        b t
+# M3-NEXT:   1      0     0.17                        b t
 
 # ALL:      Timeline view:
 # ALL-NEXT: Index     01
 
 # ALL:      [0,0]     DR   b  t
 # ALL-NEXT: [1,0]     DR   b  t
 # ALL-NEXT: [2,0]     DR   b  t
 
 # ALL:      Average Wait times (based on the timeline view):
 # ALL-NEXT: [0]: Executions
 # ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # ALL-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # ALL:            [0]    [1]    [2]    [3]
 # ALL-NEXT: 0.     3     0.0    0.0    0.0       b  t

llvm/trunk/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  1      1     0.25                  *     clc
 # CHECK-NEXT:  1      1     0.25                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s

 # CHECK-NEXT:  1      1     0.50                        vxorpd  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   vxorpd  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  2      1     1.00                        vxorpd  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  2      6     2.00    *                   vxorpd  (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.50                        vxorps  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   vxorps  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  2      1     1.00                        vxorps  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  2      6     2.00    *                   vxorps  (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  73     90     -      *      *      *     vzeroall
-# CHECK-NEXT:  37     46     -      *      *      *     vzeroupper
+# CHECK-NEXT:  73     90    36.50   *      *      *     vzeroall
+# CHECK-NEXT:  37     46    18.50   *      *      *     vzeroupper
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - JALU0
 # CHECK-NEXT: [1]   - JALU1
 # CHECK-NEXT: [2]   - JDiv
 # CHECK-NEXT: [3]   - JFPA
 # CHECK-NEXT: [4]   - JFPM
 # CHECK-NEXT: [5]   - JFPU0

llvm/trunk/test/tools/llvm-mca/X86/BtVer2/zero-idioms.s

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      0      -                          xorps %xmm0, %xmm0
-# CHECK-NEXT:  1      0      -                          xorpd %xmm1, %xmm1
-# CHECK-NEXT:  1      0      -                          vxorps  %xmm2, %xmm2, %xmm2
-# CHECK-NEXT:  1      0      -                          vxorpd  %xmm1, %xmm1, %xmm1
-# CHECK-NEXT:  1      0      -                          pxor  %xmm2, %xmm2
-# CHECK-NEXT:  1      0      -                          vpxor %xmm3, %xmm3, %xmm3
-# CHECK-NEXT:  1      0      -                          vxorps  %xmm4, %xmm4, %xmm5
-# CHECK-NEXT:  1      0      -                          vxorpd  %xmm1, %xmm1, %xmm3
-# CHECK-NEXT:  1      0      -                          vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT:  1      0     0.50                        xorps %xmm0, %xmm0
+# CHECK-NEXT:  1      0     0.50                        xorpd %xmm1, %xmm1
+# CHECK-NEXT:  1      0     0.50                        vxorps  %xmm2, %xmm2, %xmm2
+# CHECK-NEXT:  1      0     0.50                        vxorpd  %xmm1, %xmm1, %xmm1
+# CHECK-NEXT:  1      0     0.50                        pxor  %xmm2, %xmm2
+# CHECK-NEXT:  1      0     0.50                        vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT:  1      0     0.50                        vxorps  %xmm4, %xmm4, %xmm5
+# CHECK-NEXT:  1      0     0.50                        vxorpd  %xmm1, %xmm1, %xmm3
+# CHECK-NEXT:  1      0     0.50                        vpxor %xmm3, %xmm3, %xmm5
 
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    0
 # CHECK-NEXT: Max number of mappings used:         0
 
 # CHECK:      *  Register File #1 -- JFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     72
 # CHECK-NEXT:    Total number of mappings created: 0

llvm/trunk/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s

 # CHECK-NEXT:  3      7     1.00    *      *            andq  $7, (%rax)
 # CHECK-NEXT:  1      1     0.25                        andq  %rdi, %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            andq  %rdi, (%rax)
 # CHECK-NEXT:  2      6     0.50    *                   andq  (%rax), %rdi
 # CHECK-NEXT:  1      1     0.50                        btw %si, %di
 # CHECK-NEXT:  1      1     0.50                        btcw  %si, %di
 # CHECK-NEXT:  1      1     0.50                        btrw  %si, %di
 # CHECK-NEXT:  1      1     0.50                        btsw  %si, %di
-# CHECK-NEXT:  10     1      -      *                   btw %si, (%rax)
-# CHECK-NEXT:  11     1      -      *      *            btcw  %si, (%rax)
-# CHECK-NEXT:  11     1      -      *      *            btrw  %si, (%rax)
-# CHECK-NEXT:  11     1      -      *      *            btsw  %si, (%rax)
+# CHECK-NEXT:  10     1     2.50    *                   btw %si, (%rax)
+# CHECK-NEXT:  11     1     2.75    *      *            btcw  %si, (%rax)
+# CHECK-NEXT:  11     1     2.75    *      *            btrw  %si, (%rax)
+# CHECK-NEXT:  11     1     2.75    *      *            btsw  %si, (%rax)
 # CHECK-NEXT:  1      1     0.50                        btw $7, %di
 # CHECK-NEXT:  1      1     0.50                        btcw  $7, %di
 # CHECK-NEXT:  1      1     0.50                        btrw  $7, %di
 # CHECK-NEXT:  1      1     0.50                        btsw  $7, %di
 # CHECK-NEXT:  2      6     0.50    *                   btw $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btcw  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btrw  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btsw  $7, (%rax)
 # CHECK-NEXT:  1      1     0.50                        btl %esi, %edi
 # CHECK-NEXT:  1      1     0.50                        btcl  %esi, %edi
 # CHECK-NEXT:  1      1     0.50                        btrl  %esi, %edi
 # CHECK-NEXT:  1      1     0.50                        btsl  %esi, %edi
-# CHECK-NEXT:  10     1      -      *                   btl %esi, (%rax)
-# CHECK-NEXT:  11     1      -      *      *            btcl  %esi, (%rax)
-# CHECK-NEXT:  11     1      -      *      *            btrl  %esi, (%rax)
-# CHECK-NEXT:  11     1      -      *      *            btsl  %esi, (%rax)
+# CHECK-NEXT:  10     1     2.50    *                   btl %esi, (%rax)
+# CHECK-NEXT:  11     1     2.75    *      *            btcl  %esi, (%rax)
+# CHECK-NEXT:  11     1     2.75    *      *            btrl  %esi, (%rax)
+# CHECK-NEXT:  11     1     2.75    *      *            btsl  %esi, (%rax)
 # CHECK-NEXT:  1      1     0.50                        btl $7, %edi
 # CHECK-NEXT:  1      1     0.50                        btcl  $7, %edi
 # CHECK-NEXT:  1      1     0.50                        btrl  $7, %edi
 # CHECK-NEXT:  1      1     0.50                        btsl  $7, %edi
 # CHECK-NEXT:  2      6     0.50    *                   btl $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btcl  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btrl  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btsl  $7, (%rax)
 # CHECK-NEXT:  1      1     0.50                        btq %rsi, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  %rsi, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  %rsi, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  %rsi, %rdi
-# CHECK-NEXT:  10     1      -      *                   btq %rsi, (%rax)
-# CHECK-NEXT:  11     1      -      *      *            btcq  %rsi, (%rax)
-# CHECK-NEXT:  11     1      -      *      *            btrq  %rsi, (%rax)
-# CHECK-NEXT:  11     1      -      *      *            btsq  %rsi, (%rax)
+# CHECK-NEXT:  10     1     2.50    *                   btq %rsi, (%rax)
+# CHECK-NEXT:  11     1     2.75    *      *            btcq  %rsi, (%rax)
+# CHECK-NEXT:  11     1     2.75    *      *            btrq  %rsi, (%rax)
+# CHECK-NEXT:  11     1     2.75    *      *            btsq  %rsi, (%rax)
 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  1      1     0.25                  *     clc
 # CHECK-NEXT:  1      1     0.25                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

llvm/trunk/test/tools/llvm-mca/X86/Haswell/resources-x87.s

 # CHECK-NEXT:  1      3     1.00                  *     fadd  %st(0), %st(1)
 # CHECK-NEXT:  1      3     1.00                  *     fadd  %st(2)
 # CHECK-NEXT:  2      10    1.00    *             *     fadds (%ecx)
 # CHECK-NEXT:  2      10    1.00    *             *     faddl (%ecx)
 # CHECK-NEXT:  1      3     1.00                  *     faddp %st(1)
 # CHECK-NEXT:  1      3     1.00                  *     faddp %st(2)
 # CHECK-NEXT:  3      13    2.00    *             *     fiadds  (%ecx)
 # CHECK-NEXT:  3      13    2.00    *             *     fiaddl  (%ecx)
-# CHECK-NEXT:  43     47     -                    *     fbld  (%ecx)
+# CHECK-NEXT:  43     47    10.75                 *     fbld  (%ecx)
 # CHECK-NEXT:  2      1     1.00                  *     fbstp (%eax)
 # CHECK-NEXT:  1      1     1.00                  *     fchs
 # CHECK-NEXT:  4      4     1.00                  *     fnclex
 # CHECK-NEXT:  1      3     1.00                  *     fcmovb  %st(1), %st(0)
 # CHECK-NEXT:  1      3     1.00                  *     fcmovbe %st(1), %st(0)
 # CHECK-NEXT:  1      3     1.00                  *     fcmove  %st(1), %st(0)
 # CHECK-NEXT:  1      3     1.00                  *     fcmovnb %st(1), %st(0)
 # CHECK-NEXT:  1      3     1.00                  *     fcmovnbe  %st(1), %st(0)

 # CHECK-NEXT:  2      12    1.00    *             *     fmuls (%ecx)
 # CHECK-NEXT:  2      12    1.00    *             *     fmull (%eax)
 # CHECK-NEXT:  1      5     1.00                  *     fmulp %st(1)
 # CHECK-NEXT:  1      5     1.00                  *     fmulp %st(2)
 # CHECK-NEXT:  3      15    1.00    *             *     fimuls  (%ecx)
 # CHECK-NEXT:  3      15    1.00    *             *     fimull  (%eax)
 # CHECK-NEXT:  1      1     0.50                  *     fnop
 # CHECK-NEXT:  1      100   0.25                  *     fpatan
-# CHECK-NEXT:  28     19     -                    *     fprem
-# CHECK-NEXT:  41     27     -                    *     fprem1
+# CHECK-NEXT:  28     19    7.00                  *     fprem
+# CHECK-NEXT:  41     27    10.25                 *     fprem1
 # CHECK-NEXT:  1      100   0.25                  *     fptan
-# CHECK-NEXT:  17     11     -                    *     frndint
-# CHECK-NEXT:  90     1      -                    *     frstor  (%eax)
-# CHECK-NEXT:  147    1      -                    *     fnsave  (%eax)
-# CHECK-NEXT:  50     75     -                    *     fscale
+# CHECK-NEXT:  17     11    4.25                  *     frndint
+# CHECK-NEXT:  90     1     22.50                 *     frstor  (%eax)
+# CHECK-NEXT:  147    1     36.75                 *     fnsave  (%eax)
+# CHECK-NEXT:  50     75    12.50                 *     fscale
 # CHECK-NEXT:  1      100   0.25                  *     fsin
 # CHECK-NEXT:  1      100   0.25                  *     fsincos
 # CHECK-NEXT:  1      23    17.00                 *     fsqrt
 # CHECK-NEXT:  1      1     0.50                  *     fst %st(0)
 # CHECK-NEXT:  1      1     1.00           *      *     fsts  (%edx)
 # CHECK-NEXT:  1      1     1.00           *      *     fstl  (%ecx)
 # CHECK-NEXT:  1      1     0.50                  *     fstp  %st(0)
 # CHECK-NEXT:  2      1     1.00           *      *     fstpl (%edx)
 # CHECK-NEXT:  2      1     1.00           *      *     fstpl (%ecx)
 # CHECK-NEXT:  2      1     1.00           *      *     fstpt (%eax)
 # CHECK-NEXT:  3      2     1.00           *      *     fnstcw  (%eax)
 # CHECK-NEXT:  100    115   19.50                 *     fnstenv (%eax)
 # CHECK-NEXT:  3      4     1.00                  *     fnstsw  (%eax)
-# CHECK-NEXT:  90     1      -                    *     frstor  (%eax)
+# CHECK-NEXT:  90     1     22.50                 *     frstor  (%eax)
 # CHECK-NEXT:  2      2     0.50                  *     wait
-# CHECK-NEXT:  147    1      -                    *     fnsave  (%eax)
+# CHECK-NEXT:  147    1     36.75                 *     fnsave  (%eax)
 # CHECK-NEXT:  1      3     1.00                  *     fsub  %st(0), %st(1)
 # CHECK-NEXT:  1      3     1.00                  *     fsub  %st(2)
 # CHECK-NEXT:  2      10    1.00    *             *     fsubs (%ecx)
 # CHECK-NEXT:  2      10    1.00    *             *     fsubl (%eax)
 # CHECK-NEXT:  1      3     1.00                  *     fsubp %st(1)
 # CHECK-NEXT:  1      3     1.00                  *     fsubp %st(2)
 # CHECK-NEXT:  3      13    2.00    *             *     fisubs  (%ecx)
 # CHECK-NEXT:  3      13    2.00    *             *     fisubl  (%eax)

 # CHECK-NEXT:  3      1     0.50                  *     fucomi  %st(3)
 # CHECK-NEXT:  3      1     0.50                  *     fucompi %st(3)
 # CHECK-NEXT:  2      2     0.50                  *     wait
 # CHECK-NEXT:  2      1     2.00                  *     fxam
 # CHECK-NEXT:  15     17    4.00                  *     fxch  %st(1)
 # CHECK-NEXT:  15     17    4.00                  *     fxch  %st(3)
 # CHECK-NEXT:  90     64    16.50   *      *      *     fxrstor (%eax)
 # CHECK-NEXT:  1      100   0.25    *      *      *     fxsave  (%eax)
-# CHECK-NEXT:  17     15     -                    *     fxtract
+# CHECK-NEXT:  17     15    4.25                  *     fxtract
 # CHECK-NEXT:  1      100   0.25                  *     fyl2x
 # CHECK-NEXT:  1      100   0.25                  *     fyl2xp1
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - HWDivider
 # CHECK-NEXT: [1]   - HWFPDivider
 # CHECK-NEXT: [2]   - HWPort0
 # CHECK-NEXT: [3]   - HWPort1

llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        negb  %dil
 # CHECK-NEXT:  2      5     2.00    *      *            negb  (%r8)
 # CHECK-NEXT:  1      1     0.50                        negw  %si
 # CHECK-NEXT:  2      5     2.00    *      *            negw  (%r9)
 # CHECK-NEXT:  1      1     0.50                        negl  %edx
 # CHECK-NEXT:  2      5     2.00    *      *            negl  (%rax)
 # CHECK-NEXT:  1      1     0.50                        negq  %rcx
 # CHECK-NEXT:  2      5     2.00    *      *            negq  (%r10)
-# CHECK-NEXT:  1      1      -                          nop
-# CHECK-NEXT:  1      1      -                          nopw  %di
-# CHECK-NEXT:  1      1      -                          nopw  (%rcx)
-# CHECK-NEXT:  1      1      -                          nopl  %esi
-# CHECK-NEXT:  1      1      -                          nopl  (%r8)
-# CHECK-NEXT:  1      1      -                          nopq  %rdx
-# CHECK-NEXT:  1      1      -                          nopq  (%r9)
+# CHECK-NEXT:  1      1     0.50                        nop
+# CHECK-NEXT:  1      1     0.50                        nopw  %di
+# CHECK-NEXT:  1      1     0.50                        nopw  (%rcx)
+# CHECK-NEXT:  1      1     0.50                        nopl  %esi
+# CHECK-NEXT:  1      1     0.50                        nopl  (%r8)
+# CHECK-NEXT:  1      1     0.50                        nopq  %rdx
+# CHECK-NEXT:  1      1     0.50                        nopq  (%r9)
 # CHECK-NEXT:  1      1     0.50                        notb  %dil
 # CHECK-NEXT:  2      5     2.00    *      *            notb  (%r8)
 # CHECK-NEXT:  1      1     0.50                        notw  %si
 # CHECK-NEXT:  2      5     2.00    *      *            notw  (%r9)
 # CHECK-NEXT:  1      1     0.50                        notl  %edx
 # CHECK-NEXT:  2      5     2.00    *      *            notl  (%rax)
 # CHECK-NEXT:  1      1     0.50                        notq  %rcx
 # CHECK-NEXT:  2      5     2.00    *      *            notq  (%r10)

llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-x87.s

 # CHECK-NEXT:  1      5     2.00                  *     fmul  %st(0), %st(1)
 # CHECK-NEXT:  1      5     2.00                  *     fmul  %st(2)
 # CHECK-NEXT:  1      8     2.00    *             *     fmuls (%ecx)
 # CHECK-NEXT:  1      8     2.00    *             *     fmull (%eax)
 # CHECK-NEXT:  1      5     2.00                  *     fmulp %st(1)
 # CHECK-NEXT:  1      5     2.00                  *     fmulp %st(2)
 # CHECK-NEXT:  1      8     2.00    *             *     fimuls  (%ecx)
 # CHECK-NEXT:  1      8     2.00    *             *     fimull  (%eax)
-# CHECK-NEXT:  1      1      -                    *     fnop
+# CHECK-NEXT:  1      1     0.50                  *     fnop
 # CHECK-NEXT:  1      100   1.00                  *     fpatan
 # CHECK-NEXT:  1      100   1.00                  *     fprem
 # CHECK-NEXT:  1      100   1.00                  *     fprem1
 # CHECK-NEXT:  1      100   1.00                  *     fptan
 # CHECK-NEXT:  1      100   1.00                  *     frndint
 # CHECK-NEXT:  1      100   1.00                  *     frstor  (%eax)
 # CHECK-NEXT:  1      100   1.00                  *     fnsave  (%eax)
 # CHECK-NEXT:  1      100   1.00                  *     fscale

llvm/trunk/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  1      1     0.25                  *     clc
 # CHECK-NEXT:  1      1     0.33                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.33                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.33                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.33                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

 # CHECK-NEXT:  1      1     0.33                        negb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            negb  (%r8)
 # CHECK-NEXT:  1      1     0.33                        negw  %si
 # CHECK-NEXT:  3      7     1.00    *      *            negw  (%r9)
 # CHECK-NEXT:  1      1     0.33                        negl  %edx
 # CHECK-NEXT:  3      7     1.00    *      *            negl  (%rax)
 # CHECK-NEXT:  1      1     0.33                        negq  %rcx
 # CHECK-NEXT:  3      7     1.00    *      *            negq  (%r10)
-# CHECK-NEXT:  1      1      -                          nop
-# CHECK-NEXT:  1      1      -                          nopw  %di
-# CHECK-NEXT:  1      1      -                          nopw  (%rcx)
-# CHECK-NEXT:  1      1      -                          nopl  %esi
-# CHECK-NEXT:  1      1      -                          nopl  (%r8)
-# CHECK-NEXT:  1      1      -                          nopq  %rdx
-# CHECK-NEXT:  1      1      -                          nopq  (%r9)
+# CHECK-NEXT:  1      1     0.25                        nop
+# CHECK-NEXT:  1      1     0.25                        nopw  %di
+# CHECK-NEXT:  1      1     0.25                        nopw  (%rcx)
+# CHECK-NEXT:  1      1     0.25                        nopl  %esi
+# CHECK-NEXT:  1      1     0.25                        nopl  (%r8)
+# CHECK-NEXT:  1      1     0.25                        nopq  %rdx
+# CHECK-NEXT:  1      1     0.25                        nopq  (%r9)
 # CHECK-NEXT:  1      1     0.33                        notb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            notb  (%r8)
 # CHECK-NEXT:  1      1     0.33                        notw  %si
 # CHECK-NEXT:  3      7     1.00    *      *            notw  (%r9)
 # CHECK-NEXT:  1      1     0.33                        notl  %edx
 # CHECK-NEXT:  3      7     1.00    *      *            notl  (%rax)
 # CHECK-NEXT:  1      1     0.33                        notq  %rcx
 # CHECK-NEXT:  3      7     1.00    *      *            notq  (%r10)

llvm/trunk/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  1      1     0.17                  *     clc
 # CHECK-NEXT:  1      1     0.25                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

llvm/trunk/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  1      1     0.17                  *     clc
 # CHECK-NEXT:  1      1     0.25                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-avx1.s

 # CHECK-NEXT:  1      15    1.00                        vdivps  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      22    1.00    *                   vdivps  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      12    12.00                       vdivps  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  2      19    19.00   *                   vdivps  (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      15    1.00                        vdivsd  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      22    1.00    *                   vdivsd  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      15    1.00                        vdivss  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      22    1.00    *                   vdivss  (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vdppd $22, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vdppd $22, (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vdpps $22, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vdpps $22, (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vdpps $22, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vdpps $22, (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.33                        vextractf128  $1, %ymm0, %xmm2
 # CHECK-NEXT:  2      8     0.50           *            vextractf128  $1, %ymm0, (%rax)
 # CHECK-NEXT:  2      2     2.00                        vextractps  $1, %xmm0, %ecx
 # CHECK-NEXT:  2      5     2.50           *            vextractps  $1, %xmm0, (%rax)
-# CHECK-NEXT:  1      100    -                          vhaddpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vhaddpd (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vhaddpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vhaddpd (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -                          vhaddps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vhaddps (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vhaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vhaddps (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -                          vhsubpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vhsubpd (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vhsubpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vhsubpd (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -                          vhsubps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vhsubps (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vhsubps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vhsubps (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      2     0.67                        vinsertf128 $1, %xmm0, %ymm1, %ymm2
 # CHECK-NEXT:  2      9     0.67    *                   vinsertf128 $1, (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.50                        vinsertps $1, %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vinsertps $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vlddqu  (%rax), %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vlddqu  (%rax), %ymm2
-# CHECK-NEXT:  1      100    -      *      *      *     vldmxcsr  (%rax)
-# CHECK-NEXT:  1      100    -      *      *      *     vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT:  1      100   0.25    *      *      *     vldmxcsr  (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *      *     vmaskmovdqu %xmm0, %xmm1
 # CHECK-NEXT:  1      8     0.50    *                   vmaskmovpd  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  2      8     1.00    *                   vmaskmovpd  (%rax), %ymm0, %ymm2
 # CHECK-NEXT:  1      4     0.50    *      *            vmaskmovpd  %xmm0, %xmm1, (%rax)
 # CHECK-NEXT:  2      5     1.00    *      *            vmaskmovpd  %ymm0, %ymm1, (%rax)
 # CHECK-NEXT:  1      8     0.50    *                   vmaskmovps  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  2      8     1.00    *                   vmaskmovps  (%rax), %ymm0, %ymm2
 # CHECK-NEXT:  1      4     0.50    *      *            vmaskmovps  %xmm0, %xmm1, (%rax)
 # CHECK-NEXT:  2      5     1.00    *      *            vmaskmovps  %ymm0, %ymm1, (%rax)

 # CHECK-NEXT:  1      1     0.50           *            vmovupd %ymm0, (%rax)
 # CHECK-NEXT:  1      8     0.50    *                   vmovupd (%rax), %ymm2
 # CHECK-NEXT:  1      1     0.25                        vmovups %xmm0, %xmm2
 # CHECK-NEXT:  1      1     0.50           *            vmovups %xmm0, (%rax)
 # CHECK-NEXT:  1      8     0.50    *                   vmovups (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.25                        vmovups %ymm0, %ymm2
 # CHECK-NEXT:  1      1     0.50           *            vmovups %ymm0, (%rax)
 # CHECK-NEXT:  1      8     0.50    *                   vmovups (%rax), %ymm2
-# CHECK-NEXT:  1      100    -                          vmpsadbw  $1, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vmpsadbw  $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vmpsadbw  $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vmpsadbw  $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      3     0.50                        vmulpd  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  2      10    0.50    *                   vmulpd  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      4     0.50                        vmulpd  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  2      11    0.50    *                   vmulpd  (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      3     0.50                        vmulps  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  2      10    0.50    *                   vmulps  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      4     0.50                        vmulps  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  2      11    0.50    *                   vmulps  (%rax), %ymm1, %ymm2

 # CHECK-NEXT:  1      1     0.25                        vpavgb  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpavgb  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpavgw  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpavgw  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     1.00                        vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   vpblendvb %xmm3, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.33                        vpblendw  $11, %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  2      8     0.50    *                   vpblendw  $11, (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vpclmulqdq  $11, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vpclmulqdq  $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vpclmulqdq  $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vpclmulqdq  $11, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpcmpeqb  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpcmpeqb  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpcmpeqd  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpcmpeqd  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpcmpeqq  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpcmpeqq  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpcmpeqw  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpcmpeqw  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpcmpgtb  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpcmpgtb  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpcmpgtd  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpcmpgtd  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.50                        vpcmpgtq  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpcmpgtq  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpcmpgtw  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpcmpgtw  (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vperm2f128  $1, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vperm2f128  $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vperm2f128  $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vperm2f128  $1, (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.50                        vpermilpd $1, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpermilpd $1, (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        vpermilpd %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpermilpd (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.50                        vpermilpd $1, %ymm0, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpermilpd $1, (%rax), %ymm2
 # CHECK-NEXT:  1      1     0.50                        vpermilpd %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpermilpd (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.50                        vpermilps $1, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpermilps $1, (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        vpermilps %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpermilps (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.50                        vpermilps $1, %ymm0, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpermilps $1, (%rax), %ymm2
 # CHECK-NEXT:  1      1     0.50                        vpermilps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpermilps (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      2     2.00                        vpextrb $1, %xmm0, %ecx
 # CHECK-NEXT:  2      5     3.00           *            vpextrb $1, %xmm0, (%rax)
 # CHECK-NEXT:  1      2     2.00                        vpextrd $1, %xmm0, %ecx
 # CHECK-NEXT:  2      5     3.00           *            vpextrd $1, %xmm0, (%rax)
 # CHECK-NEXT:  1      2     2.00                        vpextrq $1, %xmm0, %rcx
 # CHECK-NEXT:  2      5     3.00           *            vpextrq $1, %xmm0, (%rax)
 # CHECK-NEXT:  1      2     2.00                        vpextrw $1, %xmm0, %ecx
 # CHECK-NEXT:  2      5     3.00           *            vpextrw $1, %xmm0, (%rax)
-# CHECK-NEXT:  1      100    -                          vphaddd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vphaddd (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vphaddsw  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vphaddsw  (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vphaddw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vphaddsw  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vphaddsw  (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vphaddw (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      4     1.00                        vphminposuw %xmm0, %xmm2
 # CHECK-NEXT:  1      11    1.00    *                   vphminposuw (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          vphsubd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vphsubd (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vphsubsw  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vphsubsw  (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -                          vphsubw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vphsubsw  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vphsubsw  (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25                        vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vphsubw (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpinsrb $1, %eax, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpinsrb $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpinsrd $1, %eax, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpinsrd $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpinsrq $1, %rax, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpinsrq $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vpinsrw $1, %eax, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vpinsrw $1, (%rax), %xmm1, %xmm2

 # CHECK-NEXT:  1      20    20.00                       vsqrtps %xmm0, %xmm2
 # CHECK-NEXT:  1      27    20.00   *                   vsqrtps (%rax), %xmm2
 # CHECK-NEXT:  1      28    28.00                       vsqrtps %ymm0, %ymm2
 # CHECK-NEXT:  2      35    28.00   *                   vsqrtps (%rax), %ymm2
 # CHECK-NEXT:  1      20    20.00                       vsqrtsd %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      27    20.00   *                   vsqrtsd (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      20    20.00                       vsqrtss %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      27    20.00   *                   vsqrtss (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      100    -      *      *      *     vstmxcsr  (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *      *     vstmxcsr  (%rax)
 # CHECK-NEXT:  1      3     1.00                        vsubpd  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   vsubpd  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      3     1.00                        vsubpd  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      10    1.00    *                   vsubpd  (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      3     1.00                        vsubps  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   vsubps  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      3     1.00                        vsubps  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      10    1.00    *                   vsubps  (%rax), %ymm1, %ymm2

 # CHECK-NEXT:  1      1     0.25                        vxorpd  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vxorpd  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vxorpd  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vxorpd  (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.25                        vxorps  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   vxorps  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.25                        vxorps  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vxorps  (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *      *      *     vzeroall
-# CHECK-NEXT:  1      100    -      *      *      *     vzeroupper
+# CHECK-NEXT:  1      100   0.25    *      *      *     vzeroall
+# CHECK-NEXT:  1      100   0.25    *      *      *     vzeroupper
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - ZnAGU0
 # CHECK-NEXT: [1]   - ZnAGU1
 # CHECK-NEXT: [2]   - ZnALU0
 # CHECK-NEXT: [3]   - ZnALU1
 # CHECK-NEXT: [4]   - ZnALU2
 # CHECK-NEXT: [5]   - ZnALU3

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-avx2.s

 # CHECK-NEXT: [6]: HasSideEffects
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      8     0.50    *                   vbroadcasti128  (%rax), %ymm0
 # CHECK-NEXT:  1      100   0.25                        vbroadcastsd  %xmm0, %ymm0
 # CHECK-NEXT:  1      100   0.25                        vbroadcastss  %xmm0, %ymm0
 # CHECK-NEXT:  1      2     0.25                        vextracti128  $1, %ymm0, %xmm2
 # CHECK-NEXT:  1      1     0.50           *            vextracti128  $1, %ymm0, (%rax)
-# CHECK-NEXT:  1      100    -      *                   vgatherdpd  %xmm0, (%rax,%xmm1,2), %xmm2
-# CHECK-NEXT:  1      100    -      *                   vgatherdpd  %ymm0, (%rax,%xmm1,2), %ymm2
-# CHECK-NEXT:  1      100    -      *                   vgatherdps  %xmm0, (%rax,%xmm1,2), %xmm2
-# CHECK-NEXT:  1      100    -      *                   vgatherdps  %ymm0, (%rax,%ymm1,2), %ymm2
-# CHECK-NEXT:  1      100    -      *                   vgatherqpd  %xmm0, (%rax,%xmm1,2), %xmm2
-# CHECK-NEXT:  1      100    -      *                   vgatherqpd  %ymm0, (%rax,%ymm1,2), %ymm2
-# CHECK-NEXT:  1      100    -      *                   vgatherqps  %xmm0, (%rax,%xmm1,2), %xmm2
-# CHECK-NEXT:  1      100    -      *                   vgatherqps  %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vgatherdpd  %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vgatherdpd  %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vgatherdps  %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vgatherdps  %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vgatherqpd  %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vgatherqpd  %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vgatherqps  %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vgatherqps  %xmm0, (%rax,%ymm1,2), %xmm2
 # CHECK-NEXT:  1      2     0.25                        vinserti128 $1, %xmm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      9     0.50    *                   vinserti128 $1, (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vmovntdqa (%rax), %ymm0
-# CHECK-NEXT:  1      100    -                          vmpsadbw  $1, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vmpsadbw  $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vmpsadbw  $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vmpsadbw  $1, (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.25                        vpabsb  %ymm0, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpabsb  (%rax), %ymm2
 # CHECK-NEXT:  1      1     0.25                        vpabsd  %ymm0, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpabsd  (%rax), %ymm2
 # CHECK-NEXT:  1      1     0.25                        vpabsw  %ymm0, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpabsw  (%rax), %ymm2
 # CHECK-NEXT:  1      1     0.25                        vpackssdw %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpackssdw (%rax), %ymm1, %ymm2

 # CHECK-NEXT:  1      2     0.25                        vpermd  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      9     0.50    *                   vpermd  (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      100   0.25                        vpermpd $1, %ymm0, %ymm2
 # CHECK-NEXT:  1      107   0.50    *                   vpermpd $1, (%rax), %ymm2
 # CHECK-NEXT:  1      100   0.25                        vpermps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      107   0.50    *                   vpermps (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      2     0.25                        vpermq  $1, %ymm0, %ymm2
 # CHECK-NEXT:  1      9     0.50    *                   vpermq  $1, (%rax), %ymm2
-# CHECK-NEXT:  1      100    -      *                   vpgatherdd  %xmm0, (%rax,%xmm1,2), %xmm2
-# CHECK-NEXT:  1      100    -      *                   vpgatherdd  %ymm0, (%rax,%ymm1,2), %ymm2
-# CHECK-NEXT:  1      100    -      *                   vpgatherdq  %xmm0, (%rax,%xmm1,2), %xmm2
-# CHECK-NEXT:  1      100    -      *                   vpgatherdq  %ymm0, (%rax,%xmm1,2), %ymm2
-# CHECK-NEXT:  1      100    -      *                   vpgatherqd  %xmm0, (%rax,%xmm1,2), %xmm2
-# CHECK-NEXT:  1      100    -      *                   vpgatherqq  %ymm0, (%rax,%ymm1,2), %ymm2
-# CHECK-NEXT:  1      100    -      *                   vpgatherqq  %xmm0, (%rax,%xmm1,2), %xmm2
-# CHECK-NEXT:  1      100    -      *                   vpgatherqq  %ymm0, (%rax,%ymm1,2), %ymm2
-# CHECK-NEXT:  1      100    -                          vphaddd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vphaddd (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -                          vphaddsw  %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vphaddsw  (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -                          vphaddw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vphaddw (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -                          vphsubd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vphsubd (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -                          vphsubsw  %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vphsubsw  (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -                          vphsubw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vpgatherdd  %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vpgatherdd  %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vpgatherdq  %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vpgatherdq  %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vpgatherqd  %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vpgatherqq  %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vpgatherqq  %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vpgatherqq  %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT:  1      100   0.25                        vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vphaddsw  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vphaddsw  (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vphsubsw  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vphsubsw  (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25                        vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vphsubw (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      4     1.00                        vpmaddubsw  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      11    1.00    *                   vpmaddubsw  (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      4     1.00                        vpmaddwd  %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      11    1.00    *                   vpmaddwd  (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vpmaskmovd  (%rax), %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vpmaskmovd  (%rax), %ymm0, %ymm2
-# CHECK-NEXT:  1      100    -      *      *            vpmaskmovd  %xmm0, %xmm1, (%rax)
-# CHECK-NEXT:  1      100    -      *      *            vpmaskmovd  %ymm0, %ymm1, (%rax)
+# CHECK-NEXT:  1      100   0.25    *                   vpmaskmovd  (%rax), %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vpmaskmovd  (%rax), %ymm0, %ymm2
+# CHECK-NEXT:  1      100   0.25    *      *            vpmaskmovd  %xmm0, %xmm1, (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *            vpmaskmovd  %ymm0, %ymm1, (%rax)
 # CHECK-NEXT:  2      8     1.00    *                   vpmaskmovq  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.50    *                   vpmaskmovq  (%rax), %ymm0, %ymm2
-# CHECK-NEXT:  1      100    -      *      *            vpmaskmovq  %xmm0, %xmm1, (%rax)
-# CHECK-NEXT:  1      100    -      *      *            vpmaskmovq  %ymm0, %ymm1, (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *            vpmaskmovq  %xmm0, %xmm1, (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *            vpmaskmovq  %ymm0, %ymm1, (%rax)
 # CHECK-NEXT:  1      1     0.25                        vpmaxsb %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpmaxsb (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.25                        vpmaxsd %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpmaxsd (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.25                        vpmaxsw %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpmaxsw (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.25                        vpmaxub %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  1      8     0.50    *                   vpmaxub (%rax), %ymm1, %ymm2

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-bmi2.s

 # CHECK-NEXT:  1      1     0.25                        bzhil %eax, %ebx, %ecx
 # CHECK-NEXT:  2      5     0.50    *                   bzhil %eax, (%rbx), %ecx
 # CHECK-NEXT:  1      1     0.25                        bzhiq %rax, %rbx, %rcx
 # CHECK-NEXT:  2      5     0.50    *                   bzhiq %rax, (%rbx), %rcx
 # CHECK-NEXT:  1      3     2.00                        mulxl %eax, %ebx, %ecx
 # CHECK-NEXT:  1      8     2.00    *                   mulxl (%rax), %ebx, %ecx
 # CHECK-NEXT:  1      3     1.00                        mulxq %rax, %rbx, %rcx
 # CHECK-NEXT:  1      8     1.00    *                   mulxq (%rax), %rbx, %rcx
-# CHECK-NEXT:  1      100    -                          pdepl %eax, %ebx, %ecx
-# CHECK-NEXT:  1      100    -      *                   pdepl (%rax), %ebx, %ecx
-# CHECK-NEXT:  1      100    -                          pdepq %rax, %rbx, %rcx
-# CHECK-NEXT:  1      100    -      *                   pdepq (%rax), %rbx, %rcx
-# CHECK-NEXT:  1      100    -                          pextl %eax, %ebx, %ecx
-# CHECK-NEXT:  1      100    -      *                   pextl (%rax), %ebx, %ecx
-# CHECK-NEXT:  1      100    -                          pextq %rax, %rbx, %rcx
-# CHECK-NEXT:  1      100    -      *                   pextq (%rax), %rbx, %rcx
+# CHECK-NEXT:  1      100   0.25                        pdepl %eax, %ebx, %ecx
+# CHECK-NEXT:  1      100   0.25    *                   pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT:  1      100   0.25                        pdepq %rax, %rbx, %rcx
+# CHECK-NEXT:  1      100   0.25    *                   pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT:  1      100   0.25                        pextl %eax, %ebx, %ecx
+# CHECK-NEXT:  1      100   0.25    *                   pextl (%rax), %ebx, %ecx
+# CHECK-NEXT:  1      100   0.25                        pextq %rax, %rbx, %rcx
+# CHECK-NEXT:  1      100   0.25    *                   pextq (%rax), %rbx, %rcx
 # CHECK-NEXT:  1      1     0.25                        rorxl $1, %eax, %ecx
 # CHECK-NEXT:  2      5     0.50    *                   rorxl $1, (%rax), %ecx
 # CHECK-NEXT:  1      1     0.25                        rorxq $1, %rax, %rcx
 # CHECK-NEXT:  2      5     0.50    *                   rorxq $1, (%rax), %rcx
 # CHECK-NEXT:  1      1     0.25                        sarxl %eax, %ebx, %ecx
 # CHECK-NEXT:  2      5     0.50    *                   sarxl %eax, (%rbx), %ecx
 # CHECK-NEXT:  1      1     0.25                        sarxq %rax, %rbx, %rcx
 # CHECK-NEXT:  2      5     0.50    *                   sarxq %rax, (%rbx), %rcx

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-f16c.s

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      100    -                          vcvtph2ps %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   vcvtph2ps (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          vcvtph2ps %xmm0, %ymm2
-# CHECK-NEXT:  1      100    -      *                   vcvtph2ps (%rax), %ymm2
-# CHECK-NEXT:  1      100    -                          vcvtps2ph $0, %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -             *            vcvtps2ph $0, %xmm0, (%rax)
-# CHECK-NEXT:  1      100    -                          vcvtps2ph $0, %ymm0, %xmm2
-# CHECK-NEXT:  1      100    -             *            vcvtps2ph $0, %ymm0, (%rax)
+# CHECK-NEXT:  1      100   0.25                        vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT:  1      100   0.25    *                   vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT:  1      100   0.25                        vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25           *            vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT:  1      100   0.25                        vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT:  1      100   0.25           *            vcvtps2ph $0, %ymm0, (%rax)
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - ZnAGU0
 # CHECK-NEXT: [1]   - ZnAGU1
 # CHECK-NEXT: [2]   - ZnALU0
 # CHECK-NEXT: [3]   - ZnALU1
 # CHECK-NEXT: [4]   - ZnALU2
 # CHECK-NEXT: [5]   - ZnALU3

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-sse1.s

 # CHECK-NEXT:  1      5     1.00                        cvttss2si %xmm0, %ecx
 # CHECK-NEXT:  1      5     1.00                        cvttss2si %xmm0, %rcx
 # CHECK-NEXT:  2      12    1.00    *                   cvttss2si (%rax), %ecx
 # CHECK-NEXT:  2      12    1.00    *                   cvttss2si (%rax), %rcx
 # CHECK-NEXT:  1      15    1.00                        divps %xmm0, %xmm2
 # CHECK-NEXT:  1      22    1.00    *                   divps (%rax), %xmm2
 # CHECK-NEXT:  1      15    1.00                        divss %xmm0, %xmm2
 # CHECK-NEXT:  1      22    1.00    *                   divss (%rax), %xmm2
-# CHECK-NEXT:  1      100    -      *      *      *     ldmxcsr (%rax)
-# CHECK-NEXT:  1      100    -      *      *      *     maskmovq  %mm0, %mm1
+# CHECK-NEXT:  1      100   0.25    *      *      *     ldmxcsr (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *      *     maskmovq  %mm0, %mm1
 # CHECK-NEXT:  1      3     1.00                        maxps %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   maxps (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        maxss %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   maxss (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        minps %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   minps (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        minss %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   minss (%rax), %xmm2

 # CHECK-NEXT:  2      12    1.00    *                   rsqrtss (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50    *      *      *     sfence
 # CHECK-NEXT:  1      1     0.50                        shufps  $1, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   shufps  $1, (%rax), %xmm2
 # CHECK-NEXT:  1      20    20.00                       sqrtps  %xmm0, %xmm2
 # CHECK-NEXT:  1      27    20.00   *                   sqrtps  (%rax), %xmm2
 # CHECK-NEXT:  1      20    20.00                       sqrtss  %xmm0, %xmm2
 # CHECK-NEXT:  1      27    20.00   *                   sqrtss  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -      *      *      *     stmxcsr (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *      *     stmxcsr (%rax)
 # CHECK-NEXT:  1      3     1.00                        subps %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   subps (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        subss %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   subss (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        ucomiss %xmm0, %xmm1
 # CHECK-NEXT:  1      10    1.00    *                   ucomiss (%rax), %xmm1
 # CHECK-NEXT:  1      1     0.50                        unpckhps  %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   unpckhps  (%rax), %xmm2

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-sse2.s

 # CHECK-NEXT:  1      5     1.00                        cvttsd2si %xmm0, %rcx
 # CHECK-NEXT:  1      12    1.00    *                   cvttsd2si (%rax), %ecx
 # CHECK-NEXT:  1      12    1.00    *                   cvttsd2si (%rax), %rcx
 # CHECK-NEXT:  1      15    1.00                        divpd %xmm0, %xmm2
 # CHECK-NEXT:  1      22    1.00    *                   divpd (%rax), %xmm2
 # CHECK-NEXT:  1      15    1.00                        divsd %xmm0, %xmm2
 # CHECK-NEXT:  1      22    1.00    *                   divsd (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50    *      *      *     lfence
-# CHECK-NEXT:  1      100    -      *      *      *     maskmovdqu  %xmm0, %xmm1
+# CHECK-NEXT:  1      100   0.25    *      *      *     maskmovdqu  %xmm0, %xmm1
 # CHECK-NEXT:  1      3     1.00                        maxpd %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   maxpd (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        maxsd %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   maxsd (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        minpd %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   minpd (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        minsd %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   minsd (%rax), %xmm2

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-sse3.s

 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      3     1.00                        addsubpd  %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   addsubpd  (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        addsubps  %xmm0, %xmm2
 # CHECK-NEXT:  1      10    1.00    *                   addsubps  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          haddpd  %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   haddpd  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          haddps  %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   haddps  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          hsubpd  %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   hsubpd  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          hsubps  %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   hsubps  (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        haddpd  %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   haddpd  (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        haddps  %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   haddps  (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        hsubpd  %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   hsubpd  (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        hsubps  %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   hsubps  (%rax), %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   lddqu (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        movddup %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   movddup (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        movshdup  %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   movshdup  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          movsldup  %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   movsldup  (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        movsldup  %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   movsldup  (%rax), %xmm2
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - ZnAGU0
 # CHECK-NEXT: [1]   - ZnAGU1
 # CHECK-NEXT: [2]   - ZnALU0
 # CHECK-NEXT: [3]   - ZnALU1
 # CHECK-NEXT: [4]   - ZnALU2
 # CHECK-NEXT: [5]   - ZnALU3

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-sse41.s

 # CHECK-NEXT:  1      1     0.50                        blendpd $11, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   blendpd $11, (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        blendps $11, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   blendps $11, (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        blendvpd  %xmm0, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   blendvpd  %xmm0, (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        blendvps  %xmm0, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   blendvps  %xmm0, (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          dppd  $22, %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   dppd  $22, (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          dpps  $22, %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   dpps  $22, (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        dppd  $22, %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   dppd  $22, (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        dpps  $22, %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   dpps  $22, (%rax), %xmm2
 # CHECK-NEXT:  2      2     2.00                        extractps $1, %xmm0, %ecx
 # CHECK-NEXT:  2      5     2.50           *            extractps $1, %xmm0, (%rax)
 # CHECK-NEXT:  1      1     0.50                        insertps  $1, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   insertps  $1, (%rax), %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   movntdqa  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          mpsadbw $1, %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   mpsadbw $1, (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.25                        packusdw  %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   packusdw  (%rax), %xmm2
 # CHECK-NEXT:  1      1     1.00                        pblendvb  %xmm0, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   pblendvb  %xmm0, (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.33                        pblendw $11, %xmm0, %xmm2
 # CHECK-NEXT:  2      8     0.50    *                   pblendw $11, (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.25                        pcmpeqq %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   pcmpeqq (%rax), %xmm2

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-sse42.s

 # CHECK-NEXT:  1      3     1.00                        crc32l  %eax, %ecx
 # CHECK-NEXT:  1      10    1.00    *                   crc32l  (%rax), %ecx
 # CHECK-NEXT:  1      3     1.00                        crc32w  %ax, %ecx
 # CHECK-NEXT:  1      10    1.00    *                   crc32w  (%rax), %ecx
 # CHECK-NEXT:  1      3     1.00                        crc32b  %al, %rcx
 # CHECK-NEXT:  1      10    1.00    *                   crc32b  (%rax), %rcx
 # CHECK-NEXT:  1      3     1.00                        crc32q  %rax, %rcx
 # CHECK-NEXT:  1      10    1.00    *                   crc32q  (%rax), %rcx
-# CHECK-NEXT:  1      100    -                          pcmpestri $1, %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   pcmpestri $1, (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          pcmpestrm $1, %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   pcmpestrm $1, (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          pcmpistri $1, %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   pcmpistri $1, (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          pcmpistrm $1, %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   pcmpistrm $1, (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        pcmpgtq %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   pcmpgtq (%rax), %xmm2
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - ZnAGU0
 # CHECK-NEXT: [1]   - ZnAGU1
 # CHECK-NEXT: [2]   - ZnALU0
 # CHECK-NEXT: [3]   - ZnALU1

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-ssse3.s

 # CHECK-NEXT:  1      1     0.25                        pabsw %mm0, %mm2
 # CHECK-NEXT:  1      8     0.50    *                   pabsw (%rax), %mm2
 # CHECK-NEXT:  1      1     0.25                        pabsw %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   pabsw (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.25                        palignr $1, %mm0, %mm2
 # CHECK-NEXT:  1      8     0.50    *                   palignr $1, (%rax), %mm2
 # CHECK-NEXT:  1      1     0.25                        palignr $1, %xmm0, %xmm2
 # CHECK-NEXT:  1      8     0.50    *                   palignr $1, (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          phaddd  %mm0, %mm2
-# CHECK-NEXT:  1      100    -      *                   phaddd  (%rax), %mm2
-# CHECK-NEXT:  1      100    -                          phaddd  %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   phaddd  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          phaddsw %mm0, %mm2
-# CHECK-NEXT:  1      100    -      *                   phaddsw (%rax), %mm2
-# CHECK-NEXT:  1      100    -                          phaddsw %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   phaddsw (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          phaddw  %mm0, %mm2
-# CHECK-NEXT:  1      100    -      *                   phaddw  (%rax), %mm2
-# CHECK-NEXT:  1      100    -                          phaddw  %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   phaddw  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          phsubd  %mm0, %mm2
-# CHECK-NEXT:  1      100    -      *                   phsubd  (%rax), %mm2
-# CHECK-NEXT:  1      100    -                          phsubd  %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   phsubd  (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          phsubsw %mm0, %mm2
-# CHECK-NEXT:  1      100    -      *                   phsubsw (%rax), %mm2
-# CHECK-NEXT:  1      100    -                          phsubsw %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   phsubsw (%rax), %xmm2
-# CHECK-NEXT:  1      100    -                          phsubw  %mm0, %mm2
-# CHECK-NEXT:  1      100    -      *                   phsubw  (%rax), %mm2
-# CHECK-NEXT:  1      100    -                          phsubw  %xmm0, %xmm2
-# CHECK-NEXT:  1      100    -      *                   phsubw  (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        phaddd  %mm0, %mm2
+# CHECK-NEXT:  1      100   0.25    *                   phaddd  (%rax), %mm2
+# CHECK-NEXT:  1      100   0.25                        phaddd  %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   phaddd  (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        phaddsw %mm0, %mm2
+# CHECK-NEXT:  1      100   0.25    *                   phaddsw (%rax), %mm2
+# CHECK-NEXT:  1      100   0.25                        phaddsw %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   phaddsw (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        phaddw  %mm0, %mm2
+# CHECK-NEXT:  1      100   0.25    *                   phaddw  (%rax), %mm2
+# CHECK-NEXT:  1      100   0.25                        phaddw  %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   phaddw  (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        phsubd  %mm0, %mm2
+# CHECK-NEXT:  1      100   0.25    *                   phsubd  (%rax), %mm2
+# CHECK-NEXT:  1      100   0.25                        phsubd  %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   phsubd  (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        phsubsw %mm0, %mm2
+# CHECK-NEXT:  1      100   0.25    *                   phsubsw (%rax), %mm2
+# CHECK-NEXT:  1      100   0.25                        phsubsw %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   phsubsw (%rax), %xmm2
+# CHECK-NEXT:  1      100   0.25                        phsubw  %mm0, %mm2
+# CHECK-NEXT:  1      100   0.25    *                   phsubw  (%rax), %mm2
+# CHECK-NEXT:  1      100   0.25                        phsubw  %xmm0, %xmm2
+# CHECK-NEXT:  1      100   0.25    *                   phsubw  (%rax), %xmm2
 # CHECK-NEXT:  1      4     1.00                        pmaddubsw %mm0, %mm2
 # CHECK-NEXT:  1      11    1.00    *                   pmaddubsw (%rax), %mm2
 # CHECK-NEXT:  1      4     1.00                        pmaddubsw %xmm0, %xmm2
 # CHECK-NEXT:  1      11    1.00    *                   pmaddubsw (%rax), %xmm2
 # CHECK-NEXT:  1      4     1.00                        pmulhrsw  %mm0, %mm2
 # CHECK-NEXT:  1      11    1.00    *                   pmulhrsw  (%rax), %mm2
 # CHECK-NEXT:  1      4     1.00                        pmulhrsw  %xmm0, %xmm2
 # CHECK-NEXT:  1      11    1.00    *                   pmulhrsw  (%rax), %xmm2

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.25                        negb  %dil
 # CHECK-NEXT:  2      5     0.50    *      *            negb  (%r8)
 # CHECK-NEXT:  1      1     0.25                        negw  %si
 # CHECK-NEXT:  2      5     0.50    *      *            negw  (%r9)
 # CHECK-NEXT:  1      1     0.25                        negl  %edx
 # CHECK-NEXT:  2      5     0.50    *      *            negl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        negq  %rcx
 # CHECK-NEXT:  2      5     0.50    *      *            negq  (%r10)
-# CHECK-NEXT:  1      1      -                          nop
-# CHECK-NEXT:  1      1      -                          nopw  %di
-# CHECK-NEXT:  1      1      -                          nopw  (%rcx)
-# CHECK-NEXT:  1      1      -                          nopl  %esi
-# CHECK-NEXT:  1      1      -                          nopl  (%r8)
-# CHECK-NEXT:  1      1      -                          nopq  %rdx
-# CHECK-NEXT:  1      1      -                          nopq  (%r9)
+# CHECK-NEXT:  1      1     0.25                        nop
+# CHECK-NEXT:  1      1     0.25                        nopw  %di
+# CHECK-NEXT:  1      1     0.25                        nopw  (%rcx)
+# CHECK-NEXT:  1      1     0.25                        nopl  %esi
+# CHECK-NEXT:  1      1     0.25                        nopl  (%r8)
+# CHECK-NEXT:  1      1     0.25                        nopq  %rdx
+# CHECK-NEXT:  1      1     0.25                        nopq  (%r9)
 # CHECK-NEXT:  1      1     0.25                        notb  %dil
 # CHECK-NEXT:  2      5     0.50    *      *            notb  (%r8)
 # CHECK-NEXT:  1      1     0.25                        notw  %si
 # CHECK-NEXT:  2      5     0.50    *      *            notw  (%r9)
 # CHECK-NEXT:  1      1     0.25                        notl  %edx
 # CHECK-NEXT:  2      5     0.50    *      *            notl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        notq  %rcx
 # CHECK-NEXT:  2      5     0.50    *      *            notq  (%r10)

 # CHECK-NEXT:  2      5     0.50    *      *            orq $665536, (%rax)
 # CHECK-NEXT:  1      1     0.25                        orq $7, %rdi
 # CHECK-NEXT:  2      5     0.50    *      *            orq $7, (%rax)
 # CHECK-NEXT:  1      1     0.25                        orq %rdi, %rdi
 # CHECK-NEXT:  2      5     0.50    *      *            orq %rdi, (%rax)
 # CHECK-NEXT:  2      5     0.50    *                   orq (%rax), %rdi
 # CHECK-NEXT:  1      1     0.25                        rclb  %dil
 # CHECK-NEXT:  1      1     0.25                        rcrb  %dil
-# CHECK-NEXT:  1      100    -             *            rclb  (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrb  (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rclb  (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        rclb  $7, %dil
 # CHECK-NEXT:  1      1     0.25                        rcrb  $7, %dil
-# CHECK-NEXT:  1      100    -             *            rclb  $7, (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrb  $7, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rclb  $7, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrb  $7, (%rax)
 # CHECK-NEXT:  1      1     0.25                        rclb  %cl, %dil
 # CHECK-NEXT:  1      1     0.25                        rcrb  %cl, %dil
-# CHECK-NEXT:  1      100    -             *            rclb  %cl, (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrb  %cl, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rclb  %cl, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrb  %cl, (%rax)
 # CHECK-NEXT:  1      1     0.25                        rclw  %di
 # CHECK-NEXT:  1      1     0.25                        rcrw  %di
-# CHECK-NEXT:  1      100    -             *            rclw  (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrw  (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rclw  (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrw  (%rax)
 # CHECK-NEXT:  1      1     0.25                        rclw  $7, %di
 # CHECK-NEXT:  1      1     0.25                        rcrw  $7, %di
-# CHECK-NEXT:  1      100    -             *            rclw  $7, (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrw  $7, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rclw  $7, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrw  $7, (%rax)
 # CHECK-NEXT:  1      1     0.25                        rclw  %cl, %di
 # CHECK-NEXT:  1      1     0.25                        rcrw  %cl, %di
-# CHECK-NEXT:  1      100    -             *            rclw  %cl, (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrw  %cl, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rclw  %cl, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrw  %cl, (%rax)
 # CHECK-NEXT:  1      1     0.25                        rcll  %edi
 # CHECK-NEXT:  1      1     0.25                        rcrl  %edi
-# CHECK-NEXT:  1      100    -             *            rcll  (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrl  (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcll  (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        rcll  $7, %edi
 # CHECK-NEXT:  1      1     0.25                        rcrl  $7, %edi
-# CHECK-NEXT:  1      100    -             *            rcll  $7, (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrl  $7, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcll  $7, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrl  $7, (%rax)
 # CHECK-NEXT:  1      1     0.25                        rcll  %cl, %edi
 # CHECK-NEXT:  1      1     0.25                        rcrl  %cl, %edi
-# CHECK-NEXT:  1      100    -             *            rcll  %cl, (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrl  %cl, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcll  %cl, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrl  %cl, (%rax)
 # CHECK-NEXT:  1      1     0.25                        rclq  %rdi
 # CHECK-NEXT:  1      1     0.25                        rcrq  %rdi
-# CHECK-NEXT:  1      100    -             *            rclq  (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrq  (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rclq  (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrq  (%rax)
 # CHECK-NEXT:  1      1     0.25                        rclq  $7, %rdi
 # CHECK-NEXT:  1      1     0.25                        rcrq  $7, %rdi
-# CHECK-NEXT:  1      100    -             *            rclq  $7, (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrq  $7, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rclq  $7, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrq  $7, (%rax)
 # CHECK-NEXT:  1      1     0.25                        rclq  %cl, %rdi
 # CHECK-NEXT:  1      1     0.25                        rcrq  %cl, %rdi
-# CHECK-NEXT:  1      100    -             *            rclq  %cl, (%rax)
-# CHECK-NEXT:  1      100    -             *            rcrq  %cl, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rclq  %cl, (%rax)
+# CHECK-NEXT:  1      100   0.25           *            rcrq  %cl, (%rax)
 # CHECK-NEXT:  1      1     0.25                        rolb  %dil
 # CHECK-NEXT:  1      1     0.25                        rorb  %dil
 # CHECK-NEXT:  3      5     1.00    *      *            rolb  (%rax)
 # CHECK-NEXT:  3      5     1.00    *      *            rorb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        rolb  $7, %dil
 # CHECK-NEXT:  1      1     0.25                        rorb  $7, %dil
 # CHECK-NEXT:  3      5     1.00    *      *            rolb  $7, (%rax)
 # CHECK-NEXT:  3      5     1.00    *      *            rorb  $7, (%rax)

 # CHECK-NEXT:  1      1     0.25                        sbbq  $665536, %rax
 # CHECK-NEXT:  1      1     0.25                        sbbq  $665536, %rdi
 # CHECK-NEXT:  2      5     0.50    *      *            sbbq  $665536, (%rax)
 # CHECK-NEXT:  1      1     0.25                        sbbq  $7, %rdi
 # CHECK-NEXT:  2      5     0.50    *      *            sbbq  $7, (%rax)
 # CHECK-NEXT:  1      1     0.25                        sbbq  %rdi, %rdi
 # CHECK-NEXT:  2      5     0.50    *      *            sbbq  %rdi, (%rax)
 # CHECK-NEXT:  2      5     0.50    *                   sbbq  (%rax), %rdi
-# CHECK-NEXT:  1      100    -                          shldw %cl, %si, %di
-# CHECK-NEXT:  1      100    -                          shrdw %cl, %si, %di
-# CHECK-NEXT:  1      100    -      *      *            shldw %cl, %si, (%rax)
-# CHECK-NEXT:  1      100    -      *      *            shrdw %cl, %si, (%rax)
+# CHECK-NEXT:  1      100   0.25                        shldw %cl, %si, %di
+# CHECK-NEXT:  1      100   0.25                        shrdw %cl, %si, %di
+# CHECK-NEXT:  1      100   0.25    *      *            shldw %cl, %si, (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *            shrdw %cl, %si, (%rax)
 # CHECK-NEXT:  1      1     0.25                        shldw $7, %si, %di
 # CHECK-NEXT:  1      1     0.25                        shrdw $7, %si, %di
 # CHECK-NEXT:  2      5     0.50    *      *            shldw $7, %si, (%rax)
 # CHECK-NEXT:  2      5     0.50    *      *            shrdw $7, %si, (%rax)
-# CHECK-NEXT:  1      100    -                          shldl %cl, %esi, %edi
-# CHECK-NEXT:  1      100    -                          shrdl %cl, %esi, %edi
-# CHECK-NEXT:  1      100    -      *      *            shldl %cl, %esi, (%rax)
-# CHECK-NEXT:  1      100    -      *      *            shrdl %cl, %esi, (%rax)
+# CHECK-NEXT:  1      100   0.25                        shldl %cl, %esi, %edi
+# CHECK-NEXT:  1      100   0.25                        shrdl %cl, %esi, %edi
+# CHECK-NEXT:  1      100   0.25    *      *            shldl %cl, %esi, (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *            shrdl %cl, %esi, (%rax)
 # CHECK-NEXT:  1      1     0.25                        shldl $7, %esi, %edi
 # CHECK-NEXT:  1      1     0.25                        shrdl $7, %esi, %edi
 # CHECK-NEXT:  2      5     0.50    *      *            shldl $7, %esi, (%rax)
 # CHECK-NEXT:  2      5     0.50    *      *            shrdl $7, %esi, (%rax)
-# CHECK-NEXT:  1      100    -                          shldq %cl, %rsi, %rdi
-# CHECK-NEXT:  1      100    -                          shrdq %cl, %rsi, %rdi
-# CHECK-NEXT:  1      100    -      *      *            shldq %cl, %rsi, (%rax)
-# CHECK-NEXT:  1      100    -      *      *            shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT:  1      100   0.25                        shldq %cl, %rsi, %rdi
+# CHECK-NEXT:  1      100   0.25                        shrdq %cl, %rsi, %rdi
+# CHECK-NEXT:  1      100   0.25    *      *            shldq %cl, %rsi, (%rax)
+# CHECK-NEXT:  1      100   0.25    *      *            shrdq %cl, %rsi, (%rax)
 # CHECK-NEXT:  1      1     0.25                        shldq $7, %rsi, %rdi
 # CHECK-NEXT:  1      1     0.25                        shrdq $7, %rsi, %rdi
 # CHECK-NEXT:  2      5     0.50    *      *            shldq $7, %rsi, (%rax)
 # CHECK-NEXT:  2      5     0.50    *      *            shrdq $7, %rsi, (%rax)
 # CHECK-NEXT:  1      1     0.25                        subb  $7, %al
 # CHECK-NEXT:  1      1     0.25                        subb  $7, %dil
 # CHECK-NEXT:  2      5     0.50    *      *            subb  $7, (%rax)
 # CHECK-NEXT:  1      1     0.25                        subb  %dil, %dil

llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-x87.s

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      100    -                    *     f2xm1
+# CHECK-NEXT:  1      100   0.25                  *     f2xm1
 # CHECK-NEXT:  1      2     1.00                  *     fabs
 # CHECK-NEXT:  1      3     1.00                  *     fadd  %st(0), %st(1)
 # CHECK-NEXT:  1      3     1.00                  *     fadd  %st(2)
 # CHECK-NEXT:  1      10    1.00    *             *     fadds (%ecx)
 # CHECK-NEXT:  1      10    1.00    *             *     faddl (%ecx)
 # CHECK-NEXT:  1      3     1.00                  *     faddp %st(1)
 # CHECK-NEXT:  1      3     1.00                  *     faddp %st(2)
 # CHECK-NEXT:  1      10    1.00    *             *     fiadds  (%ecx)
 # CHECK-NEXT:  1      10    1.00    *             *     fiaddl  (%ecx)
-# CHECK-NEXT:  1      100    -                    *     fbld  (%ecx)
-# CHECK-NEXT:  1      100    -                    *     fbstp (%eax)
+# CHECK-NEXT:  1      100   0.25                  *     fbld  (%ecx)
+# CHECK-NEXT:  1      100   0.25                  *     fbstp (%eax)
 # CHECK-NEXT:  1      1     1.00                  *     fchs
-# CHECK-NEXT:  1      100    -                    *     fnclex
-# CHECK-NEXT:  1      100    -                    *     fcmovb  %st(1), %st(0)
-# CHECK-NEXT:  1      100    -                    *     fcmovbe %st(1), %st(0)
-# CHECK-NEXT:  1      100    -                    *     fcmove  %st(1), %st(0)
-# CHECK-NEXT:  1      100    -                    *     fcmovnb %st(1), %st(0)
-# CHECK-NEXT:  1      100    -                    *     fcmovnbe  %st(1), %st(0)
-# CHECK-NEXT:  1      100    -                    *     fcmovne %st(1), %st(0)
-# CHECK-NEXT:  1      100    -                    *     fcmovnu %st(1), %st(0)
-# CHECK-NEXT:  1      100    -                    *     fcmovu  %st(1), %st(0)
+# CHECK-NEXT:  1      100   0.25                  *     fnclex
+# CHECK-NEXT:  1      100   0.25                  *     fcmovb  %st(1), %st(0)
+# CHECK-NEXT:  1      100   0.25                  *     fcmovbe %st(1), %st(0)
+# CHECK-NEXT:  1      100   0.25                  *     fcmove  %st(1), %st(0)
+# CHECK-NEXT:  1      100   0.25                  *     fcmovnb %st(1), %st(0)
+# CHECK-NEXT:  1      100   0.25                  *     fcmovnbe  %st(1), %st(0)
+# CHECK-NEXT:  1      100   0.25                  *     fcmovne %st(1), %st(0)
+# CHECK-NEXT:  1      100   0.25                  *     fcmovnu %st(1), %st(0)
+# CHECK-NEXT:  1      100   0.25                  *     fcmovu  %st(1), %st(0)
 # CHECK-NEXT:  1      1     1.00                  *     fcom  %st(1)
 # CHECK-NEXT:  1      1     1.00                  *     fcom  %st(3)
 # CHECK-NEXT:  1      8     1.00                  *     fcoms (%ecx)
 # CHECK-NEXT:  1      8     1.00                  *     fcoml (%eax)
 # CHECK-NEXT:  1      1     1.00                  *     fcomp %st(1)
 # CHECK-NEXT:  1      1     1.00                  *     fcomp %st(3)
 # CHECK-NEXT:  1      8     1.00                  *     fcomps  (%ecx)
 # CHECK-NEXT:  1      8     1.00                  *     fcompl  (%eax)
 # CHECK-NEXT:  1      1     1.00                  *     fcompp
 # CHECK-NEXT:  1      9     0.50                  *     fcomi %st(3)
 # CHECK-NEXT:  1      9     0.50                  *     fcompi  %st(3)
-# CHECK-NEXT:  1      100    -                    *     fcos
+# CHECK-NEXT:  1      100   0.25                  *     fcos
 # CHECK-NEXT:  1      11    1.00                  *     fdecstp
 # CHECK-NEXT:  1      15    1.00                  *     fdiv  %st(0), %st(1)
 # CHECK-NEXT:  1      15    1.00                  *     fdiv  %st(2)
 # CHECK-NEXT:  1      22    1.00    *             *     fdivs (%ecx)
 # CHECK-NEXT:  1      22    1.00    *             *     fdivl (%eax)
 # CHECK-NEXT:  1      15    1.00                  *     fdivp %st(1)
 # CHECK-NEXT:  1      15    1.00                  *     fdivp %st(2)
 # CHECK-NEXT:  1      22    1.00    *             *     fidivs  (%ecx)

 # CHECK-NEXT:  2      12    1.50                  *     ficoms  (%ecx)
 # CHECK-NEXT:  2      12    1.50                  *     ficoml  (%eax)
 # CHECK-NEXT:  2      12    1.50                  *     ficomps (%ecx)
 # CHECK-NEXT:  2      12    1.50                  *     ficompl (%eax)
 # CHECK-NEXT:  2      11    1.00    *             *     filds (%edx)
 # CHECK-NEXT:  2      11    1.00    *             *     fildl (%ecx)
 # CHECK-NEXT:  2      11    1.00    *             *     fildll  (%eax)
 # CHECK-NEXT:  1      11    1.00                  *     fincstp
-# CHECK-NEXT:  1      100    -                    *     fninit
+# CHECK-NEXT:  1      100   0.25                  *     fninit
 # CHECK-NEXT:  1      12    0.50           *      *     fists (%edx)
 # CHECK-NEXT:  1      12    0.50           *      *     fistl (%ecx)
 # CHECK-NEXT:  1      12    0.50           *      *     fistps  (%edx)
 # CHECK-NEXT:  1      12    0.50           *      *     fistpl  (%ecx)
 # CHECK-NEXT:  1      12    0.50           *      *     fistpll (%eax)
 # CHECK-NEXT:  1      12    0.50           *      *     fisttps (%edx)
 # CHECK-NEXT:  1      12    0.50           *      *     fisttpl (%ecx)
 # CHECK-NEXT:  1      12    0.50           *      *     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     0.50                  *     fld %st(0)
 # CHECK-NEXT:  1      8     0.50    *             *     flds  (%edx)
 # CHECK-NEXT:  1      8     0.50    *             *     fldl  (%ecx)
 # CHECK-NEXT:  2      1     0.50    *             *     fldt  (%eax)
-# CHECK-NEXT:  1      100    -      *             *     fldcw (%eax)
-# CHECK-NEXT:  1      100    -                    *     fldenv  (%eax)
+# CHECK-NEXT:  1      100   0.25    *             *     fldcw (%eax)
+# CHECK-NEXT:  1      100   0.25                  *     fldenv  (%eax)
 # CHECK-NEXT:  1      11    1.00                  *     fld1
 # CHECK-NEXT:  1      11    1.00                  *     fldl2e
 # CHECK-NEXT:  1      11    1.00                  *     fldl2t
 # CHECK-NEXT:  1      11    1.00                  *     fldlg2
 # CHECK-NEXT:  1      11    1.00                  *     fldln2
 # CHECK-NEXT:  1      11    1.00                  *     fldpi
 # CHECK-NEXT:  1      8     0.50                  *     fldz
 # CHECK-NEXT:  1      3     0.50                  *     fmul  %st(0), %st(1)
 # CHECK-NEXT:  1      3     0.50                  *     fmul  %st(2)
 # CHECK-NEXT:  2      10    0.50    *             *     fmuls (%ecx)
 # CHECK-NEXT:  2      10    0.50    *             *     fmull (%eax)
 # CHECK-NEXT:  1      3     0.50                  *     fmulp %st(1)
 # CHECK-NEXT:  1      3     0.50                  *     fmulp %st(2)
 # CHECK-NEXT:  2      10    0.50    *             *     fimuls  (%ecx)
 # CHECK-NEXT:  2      10    0.50    *             *     fimull  (%eax)
 # CHECK-NEXT:  1      1     1.00                  *     fnop
-# CHECK-NEXT:  1      100    -                    *     fpatan
-# CHECK-NEXT:  1      100    -                    *     fprem
-# CHECK-NEXT:  1      100    -                    *     fprem1
-# CHECK-NEXT:  1      100    -                    *     fptan
-# CHECK-NEXT:  1      100    -                    *     frndint
-# CHECK-NEXT:  1      100    -                    *     frstor  (%eax)
-# CHECK-NEXT:  1      100    -                    *     fnsave  (%eax)
-# CHECK-NEXT:  1      100    -                    *     fscale
-# CHECK-NEXT:  1      100    -                    *     fsin
-# CHECK-NEXT:  1      100    -                    *     fsincos
+# CHECK-NEXT:  1      100   0.25                  *     fpatan
+# CHECK-NEXT:  1      100   0.25                  *     fprem
+# CHECK-NEXT:  1      100   0.25                  *     fprem1
+# CHECK-NEXT:  1      100   0.25                  *     fptan
+# CHECK-NEXT:  1      100   0.25                  *     frndint
+# CHECK-NEXT:  1      100   0.25                  *     frstor  (%eax)
+# CHECK-NEXT:  1      100   0.25                  *     fnsave  (%eax)
+# CHECK-NEXT:  1      100   0.25                  *     fscale
+# CHECK-NEXT:  1      100   0.25                  *     fsin
+# CHECK-NEXT:  1      100   0.25                  *     fsincos
 # CHECK-NEXT:  1      20    20.00                 *     fsqrt
 # CHECK-NEXT:  2      5     0.50                  *     fst %st(0)
 # CHECK-NEXT:  1      1     0.50           *      *     fsts  (%edx)
 # CHECK-NEXT:  1      1     0.50           *      *     fstl  (%ecx)
 # CHECK-NEXT:  2      5     0.50                  *     fstp  %st(0)
 # CHECK-NEXT:  1      1     0.50           *      *     fstpl (%edx)
 # CHECK-NEXT:  1      1     0.50           *      *     fstpl (%ecx)
 # CHECK-NEXT:  1      5     0.50           *      *     fstpt (%eax)
-# CHECK-NEXT:  1      100    -             *      *     fnstcw  (%eax)
-# CHECK-NEXT:  1      100    -                    *     fnstenv (%eax)
-# CHECK-NEXT:  1      100    -                    *     fnstsw  (%eax)
-# CHECK-NEXT:  1      100    -                    *     frstor  (%eax)
+# CHECK-NEXT:  1      100   0.25           *      *     fnstcw  (%eax)
+# CHECK-NEXT:  1      100   0.25                  *     fnstenv (%eax)
+# CHECK-NEXT:  1      100   0.25                  *     fnstsw  (%eax)
+# CHECK-NEXT:  1      100   0.25                  *     frstor  (%eax)
 # CHECK-NEXT:  1      1     1.00                  *     wait
-# CHECK-NEXT:  1      100    -                    *     fnsave  (%eax)
+# CHECK-NEXT:  1      100   0.25                  *     fnsave  (%eax)
 # CHECK-NEXT:  1      3     1.00                  *     fsub  %st(0), %st(1)
 # CHECK-NEXT:  1      3     1.00                  *     fsub  %st(2)
 # CHECK-NEXT:  1      10    1.00    *             *     fsubs (%ecx)
 # CHECK-NEXT:  1      10    1.00    *             *     fsubl (%eax)
 # CHECK-NEXT:  1      3     1.00                  *     fsubp %st(1)
 # CHECK-NEXT:  1      3     1.00                  *     fsubp %st(2)
 # CHECK-NEXT:  1      10    1.00    *             *     fisubs  (%ecx)
 # CHECK-NEXT:  1      10    1.00    *             *     fisubl  (%eax)

 # CHECK-NEXT:  1      1     1.00                  *     fucomp  %st(3)
 # CHECK-NEXT:  1      1     1.00                  *     fucompp
 # CHECK-NEXT:  1      9     0.50                  *     fucomi  %st(3)
 # CHECK-NEXT:  1      9     0.50                  *     fucompi %st(3)
 # CHECK-NEXT:  1      1     1.00                  *     wait
 # CHECK-NEXT:  1      1     1.00                  *     fxam
 # CHECK-NEXT:  1      1     0.25                  *     fxch  %st(1)
 # CHECK-NEXT:  1      1     0.25                  *     fxch  %st(3)
-# CHECK-NEXT:  1      100    -      *      *      *     fxrstor (%eax)
-# CHECK-NEXT:  1      100    -      *      *      *     fxsave  (%eax)
-# CHECK-NEXT:  1      100    -                    *     fxtract
-# CHECK-NEXT:  1      100    -                    *     fyl2x
-# CHECK-NEXT:  1      100    -                    *     fyl2xp1
+# CHECK-NEXT:  1      100   0.25    *      *      *     fxrstor (%eax)
+# CHECK-NEXT:  1      100   0.25    *      *      *     fxsave  (%eax)
+# CHECK-NEXT:  1      100   0.25                  *     fxtract
+# CHECK-NEXT:  1      100   0.25                  *     fyl2x
+# CHECK-NEXT:  1      100   0.25                  *     fyl2xp1
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - ZnAGU0
 # CHECK-NEXT: [1]   - ZnAGU1
 # CHECK-NEXT: [2]   - ZnALU0
 # CHECK-NEXT: [3]   - ZnALU1
 # CHECK-NEXT: [4]   - ZnALU2
 # CHECK-NEXT: [5]   - ZnALU3