[ARM] Enable SETCCCARRY lowering for Thumb1.

[efriedma]

Summary

We've had Thumb1 support for ARMISD::SUBE for a while now, so this just works. Reduces codesize a bit for 64-bit integer comparisons.

[efriedma]

Fix testcase.

[rogfer01]

Thanks @efriedma looks good to me.

test/CodeGen/ARM/wide-compares.ll

13

I wonder if we could predicate more aggressively here and spare us that r12 (not sure if that'd be a win though)

movwlt r0, #1 
movwge r0, #2

[efriedma]

test/CodeGen/ARM/wide-compares.ll

13

This is a scheduling problem: the first mov is scheduled before the subs, so it can't clobber r0. (This should be a bit more clear if you pass -post-RA-scheduler=false to llc.)

-enable-misched=true actually "fixes" this. I think this is by chance; as far as I know, there aren't any relevant heuristics.

lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
   if (Subtarget->hasFullFP16()) {
     setOperationAction(ISD::SETCC,     MVT::f16, Expand);
     setOperationAction(ISD::SELECT,    MVT::f16, Custom);
     setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
   }
 
-  // Thumb-1 cannot currently select ARMISD::SUBE.
-  if (!Subtarget->isThumb1Only())
-    setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
 
   setOperationAction(ISD::BRCOND,    MVT::Other, Custom);
   setOperationAction(ISD::BR_CC,     MVT::i32,   Custom);
   if (Subtarget->hasFullFP16())
       setOperationAction(ISD::BR_CC, MVT::f16,   Custom);
   setOperationAction(ISD::BR_CC,     MVT::f32,   Custom);
   setOperationAction(ISD::BR_CC,     MVT::f64,   Custom);
   setOperationAction(ISD::BR_JT,     MVT::Other, Custom);

test/CodeGen/ARM/smml.ll

 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V4
 ; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
 ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
 ; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMB
-; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6
+; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMB
 ; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
 ; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
 ; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V4
 ; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6T2
 
 define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: Test0
 ; CHECK-NOT: smmls
   %conv4 = zext i32 %a to i64
   %conv1 = sext i32 %b to i64
   %conv2 = sext i32 %c to i64
   %mul = mul nsw i64 %conv2, %conv1
   %shr5 = lshr i64 %mul, 32
   %sub = sub nsw i64 %conv4, %shr5
   %conv3 = trunc i64 %sub to i32
   ret i32 %conv3
 }
 
 define i32 @Test1(i32 %a, i32 %b, i32 %c) {
 ;CHECK-LABEL: Test1
 ;CHECK-V4-NOT: smmls
 ;CHECK-THUMB-NOT: smmls
-;CHECK-THUMBV6-NOT: smmls
 ;CHECK-V6: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
 ;CHECK-THUMBV6T2: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
 entry:
   %conv = sext i32 %b to i64
   %conv1 = sext i32 %c to i64
   %mul = mul nsw i64 %conv1, %conv
   %conv26 = zext i32 %a to i64
   %shl = shl nuw i64 %conv26, 32
   %sub = sub nsw i64 %shl, %mul
   %shr7 = lshr i64 %sub, 32
   %conv3 = trunc i64 %shr7 to i32
   ret i32 %conv3
 }
 
 declare void @opaque(i32)
 define void @test_used_flags(i32 %in1, i32 %in2) {
 ; CHECK-LABEL: test_used_flags:
-; CHECK-THUMB: cmp  r1, #0
-; CHECK-THUMB: push {r2}
-; CHECK-THUMB: pop  {r3}
-; CHECK-THUMB: ble
-; CHECK-THUMBV6: cmp r1, #0
-; CHECK-THUMBV6: mov r3, r2
-; CHECK-THUMBV6: ble
+; CHECK-THUMB: movs    r2, #0
+; CHECK-THUMB: subs    r0, r2, r0
+; CHECK-THUMB: sbcs    r2, r1
+; CHECK-THUMB: bge
 ; CHECK-V6: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
 ; CHECK-V6: rsbs {{.*}}, [[PROD_LO]], #0
 ; CHECK-V6: rscs {{.*}}, [[PROD_HI]], #0
 ; CHECK-THUMBV6T2: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
 ; CHECK-THUMBV6T2: movs [[ZERO:r[0-9]+]], #0
 ; CHECK-THUMBV6T2: rsbs {{.*}}, [[PROD_LO]], #0
 ; CHECK-THUMBV6T2: sbcs.w {{.*}}, [[ZERO]], [[PROD_HI]]
   %in1.64 = sext i32 %in1 to i64

test/CodeGen/ARM/wide-compares.ll

-; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s
-; RUN: llc -mtriple=thumbv6-unknown-linux < %s | FileCheck --check-prefix=CHECK-THUMB1 %s
-; RUN: llc -mtriple=thumbv7-unknown-linux < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-THUMB2 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=CHECK,CHECK-ARM %s
+; RUN: llc -mtriple=thumbv6-unknown-linux < %s | FileCheck --check-prefix=CHECK,CHECK-THUMB1 %s
+; RUN: llc -mtriple=thumbv7-unknown-linux < %s | FileCheck --check-prefix=CHECK,CHECK-THUMB2 %s
 
-; CHECK-THUMB1-NOT: sbc
-
-; CHECK-LABEL: test_slt1:
 define i32 @test_slt1(i64 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_slt1:
+; CHECK-ARM:       @ %bb.0: @ %entry
+; CHECK-ARM-NEXT:    subs r0, r0, r2
+; CHECK-ARM-NEXT:    mov r12, #2
+; CHECK-ARM-NEXT:    sbcs r0, r1, r3
+; CHECK-ARM-NEXT:    movwlt r12, #1
+; CHECK-ARM-NEXT:    mov r0, r12
+; CHECK-ARM-NEXT:    bx lr
+;
+; CHECK-THUMB1-LABEL: test_slt1:
+; CHECK-THUMB1:       @ %bb.0: @ %entry
+; CHECK-THUMB1-NEXT:    subs r0, r0, r2
+; CHECK-THUMB1-NEXT:    sbcs r1, r3
+; CHECK-THUMB1-NEXT:    bge .LBB0_2
+; CHECK-THUMB1-NEXT:  @ %bb.1: @ %bb1
+; CHECK-THUMB1-NEXT:    movs r0, #1
+; CHECK-THUMB1-NEXT:    bx lr
+; CHECK-THUMB1-NEXT:  .LBB0_2: @ %bb2
+; CHECK-THUMB1-NEXT:    movs r0, #2
+; CHECK-THUMB1-NEXT:    bx lr
+;
+; CHECK-THUMB2-LABEL: test_slt1:
+; CHECK-THUMB2:       @ %bb.0: @ %entry
+; CHECK-THUMB2-NEXT:    subs r0, r0, r2
+; CHECK-THUMB2-NEXT:    mov.w r12, #2
+; CHECK-THUMB2-NEXT:    sbcs.w r0, r1, r3
+; CHECK-THUMB2-NEXT:    it lt
+; CHECK-THUMB2-NEXT:    movlt.w r12, #1
+; CHECK-THUMB2-NEXT:    mov r0, r12
+; CHECK-THUMB2-NEXT:    bx lr
 entry:
-  ; CHECK-ARM: subs {{[^,]+}}, r0, r2
-  ; CHECK-ARM: mov [[TMP:[0-9a-z]+]], #2
-  ; CHECK-ARM: sbcs {{[^,]+}}, r1, r3
-  ; CHECK-ARM: movwlt [[TMP]], #1
-  ; CHECK-ARM: mov r0, [[TMP]]
-  ; CHECK-ARM: bx lr
-  ; CHECK-THUMB2: subs {{[^,]+}}, r0, r2
-  ; CHECK-THUMB2: mov.w [[TMP:[0-9a-z]+]], #2
-  ; CHECK-THUMB2: sbcs.w {{[^,]+}}, r1, r3
-  ; CHECK-THUMB2: it lt
-  ; CHECK-THUMB2: movlt.w [[TMP]], #1
-  ; CHECK-THUMB2: mov r0, [[TMP]]
-  ; CHECK-THUMB2: bx lr
   %cmp = icmp slt i64 %a, %b
   br i1 %cmp, label %bb1, label %bb2
 bb1:
   ret i32 1
 bb2:
   ret i32 2
 }
 
-; CHECK-LABEL: test_slt2:
 define void @test_slt2(i64 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_slt2:
+; CHECK-ARM:       @ %bb.0: @ %entry
+; CHECK-ARM-NEXT:    push {r11, lr}
+; CHECK-ARM-NEXT:    subs r0, r0, r2
+; CHECK-ARM-NEXT:    sbcs r0, r1, r3
+; CHECK-ARM-NEXT:    bge .LBB1_2
+; CHECK-ARM-NEXT:  @ %bb.1: @ %bb1
+; CHECK-ARM-NEXT:    bl f
+; CHECK-ARM-NEXT:    pop {r11, pc}
+; CHECK-ARM-NEXT:  .LBB1_2: @ %bb2
+; CHECK-ARM-NEXT:    bl g
+; CHECK-ARM-NEXT:    pop {r11, pc}
+;
+; CHECK-THUMB1-LABEL: test_slt2:
+; CHECK-THUMB1:       @ %bb.0: @ %entry
+; CHECK-THUMB1-NEXT:    push {r7, lr}
+; CHECK-THUMB1-NEXT:    subs r0, r0, r2
+; CHECK-THUMB1-NEXT:    sbcs r1, r3
+; CHECK-THUMB1-NEXT:    bge .LBB1_2
+; CHECK-THUMB1-NEXT:  @ %bb.1: @ %bb1
+; CHECK-THUMB1-NEXT:    bl f
+; CHECK-THUMB1-NEXT:    pop {r7, pc}
+; CHECK-THUMB1-NEXT:  .LBB1_2: @ %bb2
+; CHECK-THUMB1-NEXT:    bl g
+; CHECK-THUMB1-NEXT:    pop {r7, pc}
+;
+; CHECK-THUMB2-LABEL: test_slt2:
+; CHECK-THUMB2:       @ %bb.0: @ %entry
+; CHECK-THUMB2-NEXT:    push {r7, lr}
+; CHECK-THUMB2-NEXT:    subs r0, r0, r2
+; CHECK-THUMB2-NEXT:    sbcs.w r0, r1, r3
+; CHECK-THUMB2-NEXT:    bge .LBB1_2
+; CHECK-THUMB2-NEXT:  @ %bb.1: @ %bb1
+; CHECK-THUMB2-NEXT:    bl f
+; CHECK-THUMB2-NEXT:    pop {r7, pc}
+; CHECK-THUMB2-NEXT:  .LBB1_2: @ %bb2
+; CHECK-THUMB2-NEXT:    bl g
+; CHECK-THUMB2-NEXT:    pop {r7, pc}
 entry:
   %cmp = icmp slt i64 %a, %b
-  ; CHECK-ARM: subs {{[^,]+}}, r0, r2
-  ; CHECK-ARM: sbcs {{[^,]+}}, r1, r3
-  ; CHECK-THUMB2: subs {{[^,]+}}, r0, r2
-  ; CHECK-THUMB2: sbcs.w {{[^,]+}}, r1, r3
-  ; CHECK: bge [[BB2:\.[0-9A-Za-z_]+]]
   br i1 %cmp, label %bb1, label %bb2
 bb1:
   call void @f()
   ret void
 bb2:
-  ; CHECK: [[BB2]]:
-  ; CHECK-NEXT: bl g
   call void @g()
   ret void
 }
 
 declare void @f()
 declare void @g()