[llvm-mca] Register listeners with the Stage instances.

[mattd]

Summary

This is an intermediate patch for moving the notification/eventing from the backend into the individual stages.
For now, the simplest approach, to put us on the right path, is to use the Backend::addEventListener to register
listeners for all stages. In the future a listener will be able to listen for events from a particular stage.

For now, we still need to maintain a list of listeners in the backend to handle events from MCA components that are not
yet stages, and to handle the cycleBegin and cycleEnd events. With this in place we can start to remove the Owner
pointers from stages that use the Owner for event dispatch. Stages should start to handle that now.

[mattd]

tools/llvm-mca/Backend.h

62

When we get stages for all of the components in MCA, this will become a unique_ptr<Stage> and we can remove the explicit references to Fetch, Dispatch above. A pipeline should operates as a composable sequence of stages.

[andreadb]

Hi Matt,

This patch looks good. However, the code will have to change again once the RetireStage and the ExecuteStage are available.

So, if you don't mind, I think it is better if we keep this patch on hold for now.
Today, I have reviewed (and accepted) the patch that introduces the RetireStage.
Once we have the ExecuteStage, then we can revisit this patch. What do you think?

Thanks,
-Andrea

[mattd]

In D47306#1112268, @andreadb wrote:

Hi Matt,

This patch looks good. However, the code will have to change again once the RetireStage and the ExecuteStage are available.

So, if you don't mind, I think it is better if we keep this patch on hold for now.
Today, I have reviewed (and accepted) the patch that introduces the RetireStage.
Once we have the ExecuteStage, then we can revisit this patch. What do you think?

I completely agree.

[mattd]

Abandoning in favor of https://reviews.llvm.org/D48576

tools/llvm-mca/Backend.h

 
 #ifndef LLVM_TOOLS_LLVM_MCA_BACKEND_H
 #define LLVM_TOOLS_LLVM_MCA_BACKEND_H
 
 #include "DispatchStage.h"
 #include "FetchStage.h"
 #include "InstrBuilder.h"
 #include "Scheduler.h"
+#include "llvm/ADT/SmallVector.h"
 
 namespace mca {
 
 class HWEventListener;
 class HWInstructionEvent;
 class HWStallEvent;
 
 /// An out of order backend for a specific subtarget.

 class Backend {
   /// This is the initial stage of the pipeline.
   /// TODO: Eventually this will become a list of unique Stage* that this
   /// backend pipeline executes.
   std::unique_ptr<FetchStage> Fetch;
   std::unique_ptr<Scheduler> HWS;
   std::unique_ptr<DispatchStage> Dispatch;
   std::set<HWEventListener *> Listeners;
+  llvm::SmallVector<Stage *, 4> Stages;
   unsigned Cycles;
 
   void runCycle(unsigned Cycle);
 
 public:
   Backend(const llvm::MCSubtargetInfo &Subtarget,
           const llvm::MCRegisterInfo &MRI,
           std::unique_ptr<FetchStage> InitialStage, unsigned DispatchWidth = 0,
           unsigned RegisterFileSize = 0, unsigned LoadQueueSize = 0,
           unsigned StoreQueueSize = 0, bool AssumeNoAlias = false)
       : Fetch(std::move(InitialStage)),
         HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(),
                                          LoadQueueSize, StoreQueueSize,
                                          AssumeNoAlias)),
         Dispatch(llvm::make_unique<DispatchStage>(
-            this, Subtarget, MRI, RegisterFileSize, DispatchWidth, HWS.get())),
+            Subtarget, MRI, RegisterFileSize, DispatchWidth, HWS.get())),
         Cycles(0) {
     HWS->setDispatchStage(Dispatch.get());
+
+    // Build a list of all stages that this backend recognizes.
+    Stages.push_back(Fetch.get());
+    Stages.push_back(Dispatch.get());
   }
 
   void run();
   void addEventListener(HWEventListener *Listener);
   void notifyCycleBegin(unsigned Cycle);
   void notifyInstructionEvent(const HWInstructionEvent &Event);
   void notifyStallEvent(const HWStallEvent &Event);
   void notifyResourceAvailable(const ResourceRef &RR);
   void notifyReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyCycleEnd(unsigned Cycle);
 };
 } // namespace mca
 
 #endif

tools/llvm-mca/Backend.cpp

 
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 
 using namespace llvm;
 
 void Backend::addEventListener(HWEventListener *Listener) {
-  if (Listener)
+  if (Listener) {
     Listeners.insert(Listener);
+    for (Stage *S : Stages)
+      S->addListener(Listener);
+  }
 }
 
 void Backend::run() {
   while (Fetch->isReady() || !Dispatch->isReady())
     runCycle(Cycles++);
 }
 
 void Backend::runCycle(unsigned Cycle) {
for (HWEventListener *Listener : Listeners)
     Listener->onCycleBegin();
 }
 
 void Backend::notifyInstructionEvent(const HWInstructionEvent &Event) {
   for (HWEventListener *Listener : Listeners)
     Listener->onInstructionEvent(Event);
 }
 
-void Backend::notifyStallEvent(const HWStallEvent &Event) {
-  for (HWEventListener *Listener : Listeners)
-    Listener->onStallEvent(Event);
-}
-
 void Backend::notifyResourceAvailable(const ResourceRef &RR) {
   LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.'
                     << RR.second << "]\n");
   for (HWEventListener *Listener : Listeners)
     Listener->onResourceAvailable(RR);
 }
 
 void Backend::notifyReservedBuffers(ArrayRef<unsigned> Buffers) {

tools/llvm-mca/DispatchStage.h

 // other instructions.
 class DispatchStage : public Stage {
   unsigned DispatchWidth;
   unsigned AvailableEntries;
   unsigned CarryOver;
   Scheduler *SC;
   std::unique_ptr<RegisterFile> RAT;
   std::unique_ptr<RetireControlUnit> RCU;
-  Backend *Owner;
   const llvm::MCSubtargetInfo &STI;
 
   bool checkRAT(const InstRef &IR);
   bool checkRCU(const InstRef &IR);
   bool checkScheduler(const InstRef &IR);
   void dispatch(InstRef IR);
   bool isRCUEmpty() const { return RCU->isEmpty(); }
   void updateRAWDependencies(ReadState &RS, const llvm::MCSubtargetInfo &STI);
class DispatchStage : public Stage {
   }
 
   void collectWrites(llvm::SmallVectorImpl<WriteState *> &Vec,
                      unsigned RegID) const {
     return RAT->collectWrites(Vec, RegID);
   }
 
 public:
-  DispatchStage(Backend *B, const llvm::MCSubtargetInfo &Subtarget,
+  DispatchStage(const llvm::MCSubtargetInfo &Subtarget,
                 const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
                 unsigned MaxDispatchWidth, Scheduler *Sched)
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
         CarryOver(0U), SC(Sched),
         RAT(llvm::make_unique<RegisterFile>(Subtarget.getSchedModel(), MRI,
                                             RegisterFileSize)),
         RCU(llvm::make_unique<RetireControlUnit>(Subtarget.getSchedModel(),
                                                  this)),
-        Owner(B), STI(Subtarget) {}
+        STI(Subtarget) {}
 
   virtual bool isReady() const override final { return isRCUEmpty(); }
   virtual void preExecute(const InstRef &IR) override final;
   virtual bool execute(InstRef &IR) override final;
   void notifyInstructionRetired(const InstRef &IR);
   void notifyDispatchStall(const InstRef &IR, unsigned EventType);
 
   void onInstructionExecuted(unsigned TokenID) {

tools/llvm-mca/DispatchStage.cpp

 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
 void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
                                                 ArrayRef<unsigned> UsedRegs) {
   LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: " << IR << '\n');
-  Owner->notifyInstructionEvent(HWInstructionDispatchedEvent(IR, UsedRegs));
+  notifyInstructionEvent(HWInstructionDispatchedEvent(IR, UsedRegs));
 }
 
 void DispatchStage::notifyInstructionRetired(const InstRef &IR) {
   LLVM_DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
   SmallVector<unsigned, 4> FreedRegs(RAT->getNumRegisterFiles());
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
 
   for (const std::unique_ptr<WriteState> &WS : IR.getInstruction()->getDefs())
     RAT->removeRegisterWrite(*WS.get(), FreedRegs, !Desc.isZeroLatency());
-  Owner->notifyInstructionEvent(HWInstructionRetiredEvent(IR, FreedRegs));
+  notifyInstructionEvent(HWInstructionRetiredEvent(IR, FreedRegs));
 }
 
 bool DispatchStage::checkRAT(const InstRef &IR) {
   SmallVector<unsigned, 4> RegDefs;
   for (const std::unique_ptr<WriteState> &RegDef :
        IR.getInstruction()->getDefs())
     RegDefs.emplace_back(RegDef->getRegisterID());
 
   unsigned RegisterMask = RAT->isAvailable(RegDefs);
   // A mask with all zeroes means: register files are available.
   if (RegisterMask) {
-    Owner->notifyStallEvent(HWStallEvent(HWStallEvent::RegisterFileStall, IR));
+    notifyStallEvent(HWStallEvent(HWStallEvent::RegisterFileStall, IR));
     return false;
   }
 
   return true;
 }
 
 bool DispatchStage::checkRCU(const InstRef &IR) {
   const unsigned NumMicroOps = IR.getInstruction()->getDesc().NumMicroOps;
   if (RCU->isAvailable(NumMicroOps))
     return true;
-  Owner->notifyStallEvent(
-      HWStallEvent(HWStallEvent::RetireControlUnitStall, IR));
+  notifyStallEvent(HWStallEvent(HWStallEvent::RetireControlUnitStall, IR));
   return false;
 }
 
 bool DispatchStage::checkScheduler(const InstRef &IR) {
   return SC->canBeDispatched(IR);
 }
 
 void DispatchStage::updateRAWDependencies(ReadState &RS,

tools/llvm-mca/Scheduler.cpp

else {
     case ResourceStateEvent::RS_BUFFER_UNAVAILABLE:
       Type = HWStallEvent::SchedulerQueueFull;
       break;
     case ResourceStateEvent::RS_RESERVED:
       Type = HWStallEvent::DispatchGroupStall;
     }
   }
 
-  Owner->notifyStallEvent(HWStallEvent(Type, IR));
+  DS->notifyStallEvent(HWStallEvent(Type, IR));
   return false;
 }
 
 void Scheduler::issueInstructionImpl(
     InstRef &IR,
     SmallVectorImpl<std::pair<ResourceRef, double>> &UsedResources) {
   Instruction *IS = IR.getInstruction();
   const InstrDesc &D = IS->getDesc();

tools/llvm-mca/Stage.h

 /// This file defines a stage.
 /// A chain of stages compose an instruction pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_STAGE_H
 
+#include "HWEventListener.h"
 #include <set>
 
 namespace mca {
 
-class HWEventListener;
 class InstRef;
 
 class Stage {
   std::set<HWEventListener *> Listeners;
   Stage(const Stage &Other) = delete;
   Stage &operator=(const Stage &Other) = delete;
 
 public:
public:
   virtual void preExecute(const InstRef &IR) {}
 
   /// Called as a cleanup and finalization phase after main stage execution.
   virtual void postExecute(const InstRef &IR) {}
 
   /// The primary action that this stage performs.
   virtual bool execute(InstRef &IR) = 0;
 
-  /// Add a listener to receive callbaks during the execution of this stage.
+  /// Add a listener to receive callbacks during the execution of this stage.
   void addListener(HWEventListener *Listener);
+
+  /// Notify listeners that an instruction event has occurred.
+  void notifyInstructionEvent(const HWInstructionEvent &Event);
+
+  /// Notify listeners that a hardware stall event has occurred.
+  void notifyStallEvent(const HWStallEvent &Event);
 };
 
 } // namespace mca
 #endif // LLVM_TOOLS_LLVM_MCA_STAGE_H

tools/llvm-mca/Stage.cpp

 #include "llvm/Support/ErrorHandling.h"
 
 namespace mca {
 
 // Pin the vtable here in the implementation file.
 Stage::Stage() {}
 
 void Stage::addListener(HWEventListener *Listener) {
-  llvm_unreachable("Stage-based eventing is not implemented.");
+  Listeners.insert(Listener);
+}
+
+void Stage::notifyInstructionEvent(const HWInstructionEvent &Event) {
+  for (HWEventListener *Listener : Listeners)
+    Listener->onInstructionEvent(Event);
+}
+
+void Stage::notifyStallEvent(const HWStallEvent &Event) {
+  for (HWEventListener *Listener : Listeners)
+    Listener->onStallEvent(Event);
 }
 
 } // namespace mca