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Differential D47178

[PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX
ClosedPublic

Authored by steven.zhang on May 21 2018, 10:13 PM.

Details

Reviewers
nemanjai
hfinkel
Commits
rGf4ec67822fb6: [PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX
rL333150: [PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX
Summary

The match pattern in the definition of LXSDX is xoaddr, which make the Pseudo instruction XFLOADf64 never selected. And XFLOADf64 will be expanded to LXSDX/LFDX post RA basing on the register pressure. To avoid the ambiguous, we need to remove the select pattern for LXSDX, just the same as what we did for LXSD. The same issue also happen for STXSDX.

This is the example to show this change:

cat a.ll
define double @_Z3foov() {
ret double 4.220000e+00
}
llc a.ll -mcpu=pwr8
cat a.s
_Z3foov: # @_Z3foov
.Lfunc_begin0:
.cfi_startproc
.Lfunc_gep0:
addis 2, 12, .TOC.-.Lfunc_gep0@ha
addi 2, 2, .TOC.-.Lfunc_gep0@l
.Lfunc_lep0:
.localentry _Z3foov, .Lfunc_lep0-.Lfunc_gep0
; %bb.0:
addis 3, 2, .LCPI0_0@toc@ha
addi 3, 3, .LCPI0_0@toc@l
lxsdx 1, 0, 3 <----- LXSDX is selected in instruction selection phase.
blr
The right process should be, XFLOADf64--> LXSDX/LFDX --> LFDX

Diff Detail

Repository
rL LLVM

Event Timeline

steven.zhang created this revision.May 21 2018, 10:13 PM
Herald added subscribers: kbarton, hiraditya. · View Herald TranscriptMay 21 2018, 10:13 PM
steven.zhang edited the summary of this revision. (Show Details)May 22 2018, 12:12 AM
hfinkel accepted this revision.May 22 2018, 6:59 AM

LGTM

This revision is now accepted and ready to land.May 22 2018, 6:59 AM
steven.zhang added a comment.May 23 2018, 7:07 PM

I need someone to commit the change for me as I didn't have the permission to commit the code. Thank you.

lei added a subscriber: lei.May 23 2018, 8:02 PM

I will commit the change for you.

Closed by commit rL333150: [PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX (authored by lei). · Explain WhyMay 23 2018, 8:24 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 148330

llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
let Uses = [RM] in { let Uses = [RM] in {
// Load indexed instructions // Load indexed instructions
let mayLoad = 1, mayStore = 0 in { let mayLoad = 1, mayStore = 0 in {
let CodeSize = 3 in let CodeSize = 3 in
def LXSDX : XX1Form_memOp<31, 588, def LXSDX : XX1Form_memOp<31, 588,
(outs vsfrc:$XT), (ins memrr:$src), (outs vsfrc:$XT), (ins memrr:$src),
"lxsdx $XT, $src", IIC_LdStLFD, "lxsdx $XT, $src", IIC_LdStLFD,
[(set f64:$XT, (load xoaddr:$src))]>; []>;
// Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later
let isPseudo = 1, CodeSize = 3 in let isPseudo = 1, CodeSize = 3 in
def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
"#XFLOADf64", "#XFLOADf64",
[(set f64:$XT, (load xoaddr:$src))]>; [(set f64:$XT, (load xoaddr:$src))]>;
let Predicates = [HasVSX, HasOnlySwappingMemOps] in let Predicates = [HasVSX, HasOnlySwappingMemOps] in
Show All 14 Lineslet Uses = [RM] in {
} // mayLoad } // mayLoad
// Store indexed instructions // Store indexed instructions
let mayStore = 1, mayLoad = 0 in { let mayStore = 1, mayLoad = 0 in {
let CodeSize = 3 in let CodeSize = 3 in
def STXSDX : XX1Form_memOp<31, 716, def STXSDX : XX1Form_memOp<31, 716,
(outs), (ins vsfrc:$XT, memrr:$dst), (outs), (ins vsfrc:$XT, memrr:$dst),
"stxsdx $XT, $dst", IIC_LdStSTFD, "stxsdx $XT, $dst", IIC_LdStSTFD,
[(store f64:$XT, xoaddr:$dst)]>; []>;
// Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later
let isPseudo = 1, CodeSize = 3 in let isPseudo = 1, CodeSize = 3 in
def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
"#XFSTOREf64", "#XFSTOREf64",
[(store f64:$XT, xoaddr:$dst)]>; [(store f64:$XT, xoaddr:$dst)]>;
let Predicates = [HasVSX, HasOnlySwappingMemOps] in { let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
▲ Show 20 Lines • Show All 3,518 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/bitcasts-direct-move.ll

Show All 12 Lines
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
; CHECK: mfvsrwz 3, [[SHIFTREG]] ; CHECK: mfvsrwz 3, [[SHIFTREG]]
} }
define i64 @f64toi64(double %a) { define i64 @f64toi64(double %a) {
entry: entry:
%0 = bitcast double %a to i64 %0 = bitcast double %a to i64
ret i64 %0 ret i64 %0
; CHECK-P7: stxsdx 1, ; CHECK-P7: stfdx 1,
; CHECK-P7: ld 3, ; CHECK-P7: ld 3,
; CHECK: mffprd 3, 1 ; CHECK: mffprd 3, 1
} }
define float @i32tof32(i32 signext %a) { define float @i32tof32(i32 signext %a) {
entry: entry:
%0 = bitcast i32 %a to float %0 = bitcast i32 %a to float
ret float %0 ret float %0
; CHECK-P7: stw 3, ; CHECK-P7: stw 3,
; CHECK-P7: lfs 1, ; CHECK-P7: lfs 1,
; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3 ; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
; CHECK: xscvspdpn 1, [[SHIFTREG]] ; CHECK: xscvspdpn 1, [[SHIFTREG]]
} }
define double @i64tof64(i64 %a) { define double @i64tof64(i64 %a) {
entry: entry:
%0 = bitcast i64 %a to double %0 = bitcast i64 %a to double
ret double %0 ret double %0
; CHECK-P7: std 3, ; CHECK-P7: std 3,
; CHECK-P7: lxsdx 1, ; CHECK-P7: lfdx 1,
; CHECK: mtvsrd 1, 3 ; CHECK: mtvsrd 1, 3
} }
define zeroext i32 @f32toi32u(float %a) { define zeroext i32 @f32toi32u(float %a) {
entry: entry:
%0 = bitcast float %a to i32 %0 = bitcast float %a to i32
ret i32 %0 ret i32 %0
; CHECK-P7: stfs 1, ; CHECK-P7: stfs 1,
; CHECK-P7: lwz 3, ; CHECK-P7: lwz 3,
; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
; CHECK: mfvsrwz 3, [[SHIFTREG]] ; CHECK: mfvsrwz 3, [[SHIFTREG]]
} }
define i64 @f64toi64u(double %a) { define i64 @f64toi64u(double %a) {
entry: entry:
%0 = bitcast double %a to i64 %0 = bitcast double %a to i64
ret i64 %0 ret i64 %0
; CHECK-P7: stxsdx 1, ; CHECK-P7: stfdx 1,
; CHECK-P7: ld 3, ; CHECK-P7: ld 3,
; CHECK: mffprd 3, 1 ; CHECK: mffprd 3, 1
} }
define float @i32utof32(i32 zeroext %a) { define float @i32utof32(i32 zeroext %a) {
entry: entry:
%0 = bitcast i32 %a to float %0 = bitcast i32 %a to float
ret float %0 ret float %0
; CHECK-P7: stw 3, ; CHECK-P7: stw 3,
; CHECK-P7: lfs 1, ; CHECK-P7: lfs 1,
; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3 ; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
; CHECK: xscvspdpn 1, [[SHIFTREG]] ; CHECK: xscvspdpn 1, [[SHIFTREG]]
} }
define double @i64utof64(i64 %a) { define double @i64utof64(i64 %a) {
entry: entry:
%0 = bitcast i64 %a to double %0 = bitcast i64 %a to double
ret double %0 ret double %0
; CHECK-P7: std 3, ; CHECK-P7: std 3,
; CHECK-P7: lxsdx 1, ; CHECK-P7: lfdx 1,
; CHECK: mtvsrd 1, 3 ; CHECK: mtvsrd 1, 3
} }

llvm/trunk/test/CodeGen/PowerPC/branch_coalesce.ll

Show All 9 Lines
; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0 ; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]] ; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]]
; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha ; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha
; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha ; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha
; CHECK-DAG: xxlxor 2, 2, 2 ; CHECK-DAG: xxlxor 2, 2, 2
; CHECK-NOT: beq ; CHECK-NOT: beq
; CHECK-DAG: addi [[LD1BASE:[0-9]+]], [[LD1REG]] ; CHECK-DAG: addi [[LD1BASE:[0-9]+]], [[LD1REG]]
; CHECK-DAG: addi [[LD2BASE:[0-9]+]], [[LD2REG]] ; CHECK-DAG: addi [[LD2BASE:[0-9]+]], [[LD2REG]]
; CHECK-DAG: lxsdx 1, 0, [[LD1BASE]] ; CHECK-DAG: lfdx 1, 0, [[LD1BASE]]
; CHECK-DAG: lxsdx 3, 0, [[LD2BASE]] ; CHECK-DAG: lfdx 3, 0, [[LD2BASE]]
; CHECK: .LBB[[LAB1]] ; CHECK: .LBB[[LAB1]]
; CHECK: xsadddp 0, 1, 2 ; CHECK: xsadddp 0, 1, 2
; CHECK: xsadddp 1, 0, 3 ; CHECK: xsadddp 1, 0, 3
; CHECK: blr ; CHECK: blr
; CHECK-NOCOALESCE-LABEL: testBranchCoal: ; CHECK-NOCOALESCE-LABEL: testBranchCoal:
; CHECK-NOCOALESCE: # %bb.0: # %entry ; CHECK-NOCOALESCE: # %bb.0: # %entry
; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0 ; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5 ; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5
; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry ; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6 ; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6
; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry ; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry
; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4 ; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4
; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry ; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry
; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_1@toc@l ; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_1@toc@l
; CHECK-NOCOALESCE-NEXT: lxsdx 3, 0, 3 ; CHECK-NOCOALESCE-NEXT: lfdx 3, 0, 3
; CHECK-NOCOALESCE-NEXT: .LBB0_4: # %entry ; CHECK-NOCOALESCE-NEXT: .LBB0_4: # %entry
; CHECK-NOCOALESCE-NEXT: xsadddp 0, 1, 2 ; CHECK-NOCOALESCE-NEXT: xsadddp 0, 1, 2
; CHECK-NOCOALESCE-NEXT: xsadddp 1, 0, 3 ; CHECK-NOCOALESCE-NEXT: xsadddp 1, 0, 3
; CHECK-NOCOALESCE-NEXT: blr ; CHECK-NOCOALESCE-NEXT: blr
; CHECK-NOCOALESCE-NEXT: .LBB0_5: # %entry ; CHECK-NOCOALESCE-NEXT: .LBB0_5: # %entry
; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_0@toc@l ; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK-NOCOALESCE-NEXT: lxsdx 1, 0, 3 ; CHECK-NOCOALESCE-NEXT: lfdx 1, 0, 3
; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_2 ; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_2
; CHECK-NOCOALESCE-NEXT: .LBB0_6: # %entry ; CHECK-NOCOALESCE-NEXT: .LBB0_6: # %entry
; CHECK-NOCOALESCE-NEXT: xxlxor 2, 2, 2 ; CHECK-NOCOALESCE-NEXT: xxlxor 2, 2, 2
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_3 ; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_3
; CHECK-NOCOALESCE-NEXT: b .LBB0_4 ; CHECK-NOCOALESCE-NEXT: b .LBB0_4
entry: entry:
%test = icmp eq i32 %x, 0 %test = icmp eq i32 %x, 0
%tmp1 = select i1 %test, double %a, double 2.000000e-03 %tmp1 = select i1 %test, double %a, double 2.000000e-03
%tmp2 = select i1 %test, double %b, double 0.000000e+00 %tmp2 = select i1 %test, double %b, double 0.000000e+00
%tmp3 = select i1 %test, double %c, double 5.000000e-03 %tmp3 = select i1 %test, double %c, double 5.000000e-03
%res1 = fadd double %tmp1, %tmp2 %res1 = fadd double %tmp1, %tmp2
%result = fadd double %res1, %tmp3 %result = fadd double %res1, %tmp3
ret double %result ret double %result
} }

llvm/trunk/test/CodeGen/PowerPC/build-vector-tests.ll

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; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xvcvdpsp ; P9LE: xvcvdpsp
; P9LE: xvcvdpsp ; P9LE: xvcvdpsp
; P9LE: vmrgew ; P9LE: vmrgew
; P9LE: xvcvspsxws v2 ; P9LE: xvcvspsxws v2
; P8BE: lxsdx ; P8BE: lfdx
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xvcvdpsp ; P8BE: xvcvdpsp
; P8BE: xvcvdpsp ; P8BE: xvcvdpsp
; P8BE: vmrgew ; P8BE: vmrgew
; P8BE: xvcvspsxws v2 ; P8BE: xvcvspsxws v2
; P8LE: lxsdx ; P8LE: lfdx
; P8LE: lxsdx ; P8LE: lfd
; P8LE: lxsdx ; P8LE: lfd
; P8LE: lxsdx ; P8LE: lfd
; P8LE: xxmrghd ; P8LE: xxmrghd
; P8LE: xxmrghd ; P8LE: xxmrghd
; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: vmrgew ; P8LE: vmrgew
; P8LE: xvcvspsxws v2 ; P8LE: xvcvspsxws v2
} }
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; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xvcvdpsp ; P9LE: xvcvdpsp
; P9LE: xvcvdpsp ; P9LE: xvcvdpsp
; P9LE: vmrgew ; P9LE: vmrgew
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; P8BE: lfdux ; P8BE: lfdux
; P8BE: lxsdx ; P8BE: lfd
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; P8LE: lfdux ; P8LE: lfdux
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; P8LE: lxsdx ; P8LE: lfd
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; P8LE: xxmrghd ; P8LE: xxmrghd
; P8LE: xxmrghd ; P8LE: xxmrghd
; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: vmrgew ; P8LE: vmrgew
; P8LE: xvcvspsxws v2 ; P8LE: xvcvspsxws v2
} }
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; P9LE: lfd ; P9LE: lfd
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; P9LE: xvcvdpsp ; P9LE: xvcvdpsp
; P9LE: vmrgew ; P9LE: vmrgew
; P9LE: xvcvspsxws v2 ; P9LE: xvcvspsxws v2
; P8BE: lfdux ; P8BE: lfdux
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
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; P8LE: lfdux ; P8LE: lfdux
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; P8LE: lxsdx ; P8LE: lfd
; P8LE: lxsdx ; P8LE: lfd
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; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: vmrgew ; P8LE: vmrgew
; P8LE: xvcvspsxws v2 ; P8LE: xvcvspsxws v2
} }
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; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
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; P9LE: xvcvdpsp ; P9LE: xvcvdpsp
; P9LE: xvcvdpsp ; P9LE: xvcvdpsp
; P9LE: vmrgew ; P9LE: vmrgew
; P9LE: xvcvspuxws v2 ; P9LE: xvcvspuxws v2
; P8BE: lxsdx ; P8BE: lfdx
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
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; P8BE: xvcvdpsp ; P8BE: xvcvdpsp
; P8BE: vmrgew ; P8BE: vmrgew
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; P8LE: lxsdx ; P8LE: lfdx
; P8LE: lxsdx ; P8LE: lfd
; P8LE: lxsdx ; P8LE: lfd
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; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: vmrgew ; P8LE: vmrgew
; P8LE: xvcvspuxws v2 ; P8LE: xvcvspuxws v2
} }
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; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
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; P9LE: vmrgew ; P9LE: vmrgew
; P9LE: xvcvspuxws v2 ; P9LE: xvcvspuxws v2
; P8BE: lfdux ; P8BE: lfdux
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xvcvdpsp ; P8BE: xvcvdpsp
; P8BE: xvcvdpsp ; P8BE: xvcvdpsp
; P8BE: vmrgew ; P8BE: vmrgew
; P8BE: xvcvspuxws v2 ; P8BE: xvcvspuxws v2
; P8LE: lfdux ; P8LE: lfdux
; P8LE: lxsdx ; P8LE: lfd
; P8LE: lxsdx ; P8LE: lfd
; P8LE: lxsdx ; P8LE: lfd
; P8LE: xxmrghd ; P8LE: xxmrghd
; P8LE: xxmrghd ; P8LE: xxmrghd
; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: vmrgew ; P8LE: vmrgew
; P8LE: xvcvspuxws v2 ; P8LE: xvcvspuxws v2
} }
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; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xxmrghd ; P9LE: xxmrghd
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; P9LE: xvcvdpsp ; P9LE: xvcvdpsp
; P9LE: vmrgew ; P9LE: vmrgew
; P9LE: xvcvspuxws v2 ; P9LE: xvcvspuxws v2
; P8BE: lfdux ; P8BE: lfdux
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
; P8BE: lxsdx ; P8BE: lfd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xvcvdpsp ; P8BE: xvcvdpsp
; P8BE: xvcvdpsp ; P8BE: xvcvdpsp
; P8BE: vmrgew ; P8BE: vmrgew
; P8BE: xvcvspuxws v2 ; P8BE: xvcvspuxws v2
; P8LE: lfdux ; P8LE: lfdux
; P8LE: lxsdx ; P8LE: lfd
; P8LE: lxsdx ; P8LE: lfd
; P8LE: lxsdx ; P8LE: lfd
; P8LE: xxmrghd ; P8LE: xxmrghd
; P8LE: xxmrghd ; P8LE: xxmrghd
; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: xvcvdpsp ; P8LE: xvcvdpsp
; P8LE: vmrgew ; P8LE: vmrgew
; P8LE: xvcvspuxws v2 ; P8LE: xvcvspuxws v2
} }
▲ Show 20 Lines • Show All 1,861 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll

Show All 11 Lines
%SomeStruct = type { double } %SomeStruct = type { double }
; ELF64VSX-LABEL: SomeStructCtor ; ELF64VSX-LABEL: SomeStructCtor
define linkonce_odr void @SomeStructCtor(%SomeStruct* %this, double %V) unnamed_addr align 2 { define linkonce_odr void @SomeStructCtor(%SomeStruct* %this, double %V) unnamed_addr align 2 {
entry: entry:
%this.addr = alloca %SomeStruct*, align 8 %this.addr = alloca %SomeStruct*, align 8
%V.addr = alloca double, align 8 %V.addr = alloca double, align 8
store %SomeStruct* %this, %SomeStruct** %this.addr, align 8 store %SomeStruct* %this, %SomeStruct** %this.addr, align 8
; ELF64VSX: stxsdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}} ; ELF64VSX: stfdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}}
store double %V, double* %V.addr, align 8 store double %V, double* %V.addr, align 8
%this1 = load %SomeStruct*, %SomeStruct** %this.addr %this1 = load %SomeStruct*, %SomeStruct** %this.addr
%Val = getelementptr inbounds %SomeStruct, %SomeStruct* %this1, i32 0, i32 0 %Val = getelementptr inbounds %SomeStruct, %SomeStruct* %this1, i32 0, i32 0
; ELF64VSX: stxsdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}} ; ELF64VSX: stxsdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}}
%0 = load double, double* %V.addr, align 8 %0 = load double, double* %V.addr, align 8
store double %0, double* %Val, align 8 store double %0, double* %Val, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/float-to-int.ll

Show All 15 Lines
; CHECK: @foo ; CHECK: @foo
; CHECK: fctidz [[REG:[0-9]+]], 1 ; CHECK: fctidz [[REG:[0-9]+]], 1
; CHECK: stfd [[REG]], ; CHECK: stfd [[REG]],
; CHECK: ld 3, ; CHECK: ld 3,
; CHECK: blr ; CHECK: blr
; CHECK-VSX: @foo ; CHECK-VSX: @foo
; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
; CHECK-VSX: stxsdx [[REG]], ; CHECK-VSX: stfdx [[REG]],
; CHECK-VSX: ld 3, ; CHECK-VSX: ld 3,
; CHECK-VSX: blr ; CHECK-VSX: blr
; CHECK-LABEL-P9: @foo ; CHECK-LABEL-P9: @foo
; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1 ; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
; CHECK-P9: stfd [[REG]], ; CHECK-P9: stfd [[REG]],
; CHECK-P9: ld 3, ; CHECK-P9: ld 3,
; CHECK-P9: blr ; CHECK-P9: blr
} }
define i64 @foo2(double %a) nounwind { define i64 @foo2(double %a) nounwind {
%x = fptosi double %a to i64 %x = fptosi double %a to i64
ret i64 %x ret i64 %x
; CHECK: @foo2 ; CHECK: @foo2
; CHECK: fctidz [[REG:[0-9]+]], 1 ; CHECK: fctidz [[REG:[0-9]+]], 1
; CHECK: stfd [[REG]], ; CHECK: stfd [[REG]],
; CHECK: ld 3, ; CHECK: ld 3,
; CHECK: blr ; CHECK: blr
; CHECK-VSX: @foo2 ; CHECK-VSX: @foo2
; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
; CHECK-VSX: stxsdx [[REG]], ; CHECK-VSX: stfdx [[REG]],
; CHECK-VSX: ld 3, ; CHECK-VSX: ld 3,
; CHECK-VSX: blr ; CHECK-VSX: blr
; CHECK-LABEL-P9: @foo2 ; CHECK-LABEL-P9: @foo2
; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1 ; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
; CHECK-P9: stfd [[REG]], ; CHECK-P9: stfd [[REG]],
; CHECK-P9: ld 3, ; CHECK-P9: ld 3,
; CHECK-P9: blr ; CHECK-P9: blr
} }
define i64 @foo3(float %a) nounwind { define i64 @foo3(float %a) nounwind {
%x = fptoui float %a to i64 %x = fptoui float %a to i64
ret i64 %x ret i64 %x
; CHECK: @foo3 ; CHECK: @foo3
; CHECK: fctiduz [[REG:[0-9]+]], 1 ; CHECK: fctiduz [[REG:[0-9]+]], 1
; CHECK: stfd [[REG]], ; CHECK: stfd [[REG]],
; CHECK: ld 3, ; CHECK: ld 3,
; CHECK: blr ; CHECK: blr
; CHECK-VSX: @foo3 ; CHECK-VSX: @foo3
; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1 ; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
; CHECK-VSX: stxsdx [[REG]], ; CHECK-VSX: stfdx [[REG]],
; CHECK-VSX: ld 3, ; CHECK-VSX: ld 3,
; CHECK-VSX: blr ; CHECK-VSX: blr
; CHECK-LABEL-P9: @foo3 ; CHECK-LABEL-P9: @foo3
; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1 ; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
; CHECK-P9: stfd [[REG]], ; CHECK-P9: stfd [[REG]],
; CHECK-P9: ld 3, ; CHECK-P9: ld 3,
; CHECK-P9: blr ; CHECK-P9: blr
} }
define i64 @foo4(double %a) nounwind { define i64 @foo4(double %a) nounwind {
%x = fptoui double %a to i64 %x = fptoui double %a to i64
ret i64 %x ret i64 %x
; CHECK: @foo4 ; CHECK: @foo4
; CHECK: fctiduz [[REG:[0-9]+]], 1 ; CHECK: fctiduz [[REG:[0-9]+]], 1
; CHECK: stfd [[REG]], ; CHECK: stfd [[REG]],
; CHECK: ld 3, ; CHECK: ld 3,
; CHECK: blr ; CHECK: blr
; CHECK-VSX: @foo4 ; CHECK-VSX: @foo4
; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1 ; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
; CHECK-VSX: stxsdx [[REG]], ; CHECK-VSX: stfdx [[REG]],
; CHECK-VSX: ld 3, ; CHECK-VSX: ld 3,
; CHECK-VSX: blr ; CHECK-VSX: blr
; CHECK-LABEL-P9: @foo4 ; CHECK-LABEL-P9: @foo4
; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1 ; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
; CHECK-P9: stfd [[REG]], ; CHECK-P9: stfd [[REG]],
; CHECK-P9: ld 3, ; CHECK-P9: ld 3,
; CHECK-P9: blr ; CHECK-P9: blr
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32
define i128 @test_abs(ppc_fp128 %x) nounwind { define i128 @test_abs(ppc_fp128 %x) nounwind {
entry: entry:
; PPC64-LABEL: test_abs: ; PPC64-LABEL: test_abs:
; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]] ; PPC64-DAG: stfdx 2, 0, [[ADDR_HI:[0-9]+]]
; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]] ; PPC64-DAG: stfdx 1, 0, [[ADDR_LO:[0-9]+]]
; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]] ; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]] ; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]]) ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]]) ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
; PPC64-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0 ; PPC64-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]] ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]] ; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
; PPC64: blr ; PPC64: blr
Show All 20 Lines; PPC32: blr
%0 = tail call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 %x) %0 = tail call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 %x)
%1 = bitcast ppc_fp128 %0 to i128 %1 = bitcast ppc_fp128 %0 to i128
ret i128 %1 ret i128 %1
} }
define i128 @test_neg(ppc_fp128 %x) nounwind { define i128 @test_neg(ppc_fp128 %x) nounwind {
entry: entry:
; PPC64-LABEL: test_neg: ; PPC64-LABEL: test_neg:
; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]] ; PPC64-DAG: stfdx 2, 0, [[ADDR_HI:[0-9]+]]
; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]] ; PPC64-DAG: stfdx 1, 0, [[ADDR_LO:[0-9]+]]
; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]] ; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]] ; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1 ; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1
; PPC64-DAG: sldi [[FLIP_BIT]], [[FLIP_BIT]], 63 ; PPC64-DAG: sldi [[FLIP_BIT]], [[FLIP_BIT]], 63
; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]]) ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]]) ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
; PPC64-NOT: BARRIER ; PPC64-NOT: BARRIER
; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]] ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
Show All 24 Lines; PPC32: blr
%0 = fsub ppc_fp128 0xM80000000000000000000000000000000, %x %0 = fsub ppc_fp128 0xM80000000000000000000000000000000, %x
%1 = bitcast ppc_fp128 %0 to i128 %1 = bitcast ppc_fp128 %0 to i128
ret i128 %1 ret i128 %1
} }
define i128 @test_copysign(ppc_fp128 %x) nounwind { define i128 @test_copysign(ppc_fp128 %x) nounwind {
entry: entry:
; PPC64-LABEL: test_copysign: ; PPC64-LABEL: test_copysign:
; PPC64-DAG: stxsdx 1, 0, [[ADDR_REG:[0-9]+]] ; PPC64-DAG: stfdx 1, 0, [[ADDR_REG:[0-9]+]]
; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]] ; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]]
; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399 ; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48 ; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019 ; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52 ; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
; PPC64-NOT: BARRIER ; PPC64-NOT: BARRIER
; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1) ; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0 ; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
Show All 31 Lines

llvm/trunk/test/CodeGen/PowerPC/i64-to-float.ll

Show All 14 Lines
; CHECK: @foo ; CHECK: @foo
; CHECK: std 3, ; CHECK: std 3,
; CHECK: lfd [[REG:[0-9]+]], ; CHECK: lfd [[REG:[0-9]+]],
; CHECK: fcfids 1, [[REG]] ; CHECK: fcfids 1, [[REG]]
; CHECK: blr ; CHECK: blr
; CHECK-VSX: @foo ; CHECK-VSX: @foo
; CHECK-VSX: std 3, ; CHECK-VSX: std 3,
; CHECK-VSX: lxsdx [[REG:[0-9]+]], ; CHECK-VSX: lfdx [[REG:[0-9]+]],
; CHECK-VSX: fcfids 1, [[REG]] ; CHECK-VSX: fcfids 1, [[REG]]
; CHECK-VSX: blr ; CHECK-VSX: blr
; CHECK-P9: @foo ; CHECK-P9: @foo
; CHECK-P9: std 3, ; CHECK-P9: std 3,
; CHECK-P9: lfd [[REG:[0-9]+]], ; CHECK-P9: lfd [[REG:[0-9]+]],
; CHECK-P9: xscvsxdsp 1, [[REG]] ; CHECK-P9: xscvsxdsp 1, [[REG]]
; CHECK-P9: blr ; CHECK-P9: blr
} }
define double @goo(i64 %a) nounwind { define double @goo(i64 %a) nounwind {
entry: entry:
%x = sitofp i64 %a to double %x = sitofp i64 %a to double
ret double %x ret double %x
; CHECK: @goo ; CHECK: @goo
; CHECK: std 3, ; CHECK: std 3,
; CHECK: lfd [[REG:[0-9]+]], ; CHECK: lfd [[REG:[0-9]+]],
; CHECK: fcfid 1, [[REG]] ; CHECK: fcfid 1, [[REG]]
; CHECK: blr ; CHECK: blr
; CHECK-VSX: @goo ; CHECK-VSX: @goo
; CHECK-VSX: std 3, ; CHECK-VSX: std 3,
; CHECK-VSX: lxsdx [[REG:[0-9]+]], ; CHECK-VSX: lfdx [[REG:[0-9]+]],
; CHECK-VSX: xscvsxddp 1, [[REG]] ; CHECK-VSX: xscvsxddp 1, [[REG]]
; CHECK-VSX: blr ; CHECK-VSX: blr
; CHECK-P9: @goo ; CHECK-P9: @goo
; CHECK-P9: std 3, ; CHECK-P9: std 3,
; CHECK-P9: lfd [[REG:[0-9]+]], ; CHECK-P9: lfd [[REG:[0-9]+]],
; CHECK-P9: xscvsxddp 1, [[REG]] ; CHECK-P9: xscvsxddp 1, [[REG]]
; CHECK-P9: blr ; CHECK-P9: blr
} }
define float @foou(i64 %a) nounwind { define float @foou(i64 %a) nounwind {
entry: entry:
%x = uitofp i64 %a to float %x = uitofp i64 %a to float
ret float %x ret float %x
; CHECK: @foou ; CHECK: @foou
; CHECK: std 3, ; CHECK: std 3,
; CHECK: lfd [[REG:[0-9]+]], ; CHECK: lfd [[REG:[0-9]+]],
; CHECK: fcfidus 1, [[REG]] ; CHECK: fcfidus 1, [[REG]]
; CHECK: blr ; CHECK: blr
; CHECK-VSX: @foou ; CHECK-VSX: @foou
; CHECK-VSX: std 3, ; CHECK-VSX: std 3,
; CHECK-VSX: lxsdx [[REG:[0-9]+]], ; CHECK-VSX: lfdx [[REG:[0-9]+]],
; CHECK-VSX: fcfidus 1, [[REG]] ; CHECK-VSX: fcfidus 1, [[REG]]
; CHECK-VSX: blr ; CHECK-VSX: blr
; CHECK-P9: @foou ; CHECK-P9: @foou
; CHECK-P9: std 3, ; CHECK-P9: std 3,
; CHECK-P9: lfd [[REG:[0-9]+]], ; CHECK-P9: lfd [[REG:[0-9]+]],
; CHECK-P9: xscvuxdsp 1, [[REG]] ; CHECK-P9: xscvuxdsp 1, [[REG]]
; CHECK-P9: blr ; CHECK-P9: blr
} }
define double @goou(i64 %a) nounwind { define double @goou(i64 %a) nounwind {
entry: entry:
%x = uitofp i64 %a to double %x = uitofp i64 %a to double
ret double %x ret double %x
; CHECK: @goou ; CHECK: @goou
; CHECK: std 3, ; CHECK: std 3,
; CHECK: lfd [[REG:[0-9]+]], ; CHECK: lfd [[REG:[0-9]+]],
; CHECK: fcfidu 1, [[REG]] ; CHECK: fcfidu 1, [[REG]]
; CHECK: blr ; CHECK: blr
; CHECK-VSX: @goou ; CHECK-VSX: @goou
; CHECK-VSX: std 3, ; CHECK-VSX: std 3,
; CHECK-VSX: lxsdx [[REG:[0-9]+]], ; CHECK-VSX: lfdx [[REG:[0-9]+]],
; CHECK-VSX: xscvuxddp 1, [[REG]] ; CHECK-VSX: xscvuxddp 1, [[REG]]
; CHECK-VSX: blr ; CHECK-VSX: blr
; CHECK-P9: @goou ; CHECK-P9: @goou
; CHECK-P9: std 3, ; CHECK-P9: std 3,
; CHECK-P9: lfd [[REG:[0-9]+]], ; CHECK-P9: lfd [[REG:[0-9]+]],
; CHECK-P9: xscvuxddp 1, [[REG]] ; CHECK-P9: xscvuxddp 1, [[REG]]
; CHECK-P9: blr ; CHECK-P9: blr
} }

llvm/trunk/test/CodeGen/PowerPC/mcm-12.ll

Show All 21 Lines
; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
; CHECK-VSX: [[VAR:[a-z0-9A-Z_.]+]]: ; CHECK-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
; CHECK-VSX: .quad 4562098671269285104 ; CHECK-VSX: .quad 4562098671269285104
; CHECK-VSX-LABEL: test_double_const: ; CHECK-VSX-LABEL: test_double_const:
; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; CHECK-VSX: addi [[REG1]], {{[0-9]+}}, [[VAR]]@toc@l ; CHECK-VSX: addi [[REG1]], {{[0-9]+}}, [[VAR]]@toc@l
; CHECK-VSX: lxsdx {{[0-9]+}}, 0, [[REG1]] ; CHECK-VSX: lfdx {{[0-9]+}}, 0, [[REG1]]
; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]: ; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]:
; CHECK-P9: .quad 4562098671269285104 ; CHECK-P9: .quad 4562098671269285104
; CHECK-P9-LABEL: test_double_const: ; CHECK-P9-LABEL: test_double_const:
; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; CHECK-P9: addi [[REG1]], {{[0-9]+}}, [[VAR]]@toc@l ; CHECK-P9: addi [[REG1]], {{[0-9]+}}, [[VAR]]@toc@l
; CHECK-P9: lfd {{[0-9]+}}, 0([[REG1]]) ; CHECK-P9: lfd {{[0-9]+}}, 0([[REG1]])

llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll

Show All 28 Lines
; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]]) ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]: ; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
; MEDIUM-VSX: .quad 4562098671269285104 ; MEDIUM-VSX: .quad 4562098671269285104
; MEDIUM-VSX-LABEL: test_double_const: ; MEDIUM-VSX-LABEL: test_double_const:
; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
; MEDIUM-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]] ; MEDIUM-VSX: lfdx {{[0-9]+}}, 0, [[REG2]]
; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
; LARGE: .quad 4562098671269285104 ; LARGE: .quad 4562098671269285104
; LARGE-LABEL: test_double_const: ; LARGE-LABEL: test_double_const:
; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
; LARGE: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
; LARGE-VSX: .quad 4562098671269285104 ; LARGE-VSX: .quad 4562098671269285104
; LARGE-VSX-LABEL: test_double_const: ; LARGE-VSX-LABEL: test_double_const:
; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
; LARGE-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]] ; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]]
; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]: ; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]:
; MEDIUM-P9: .quad 4562098671269285104 ; MEDIUM-P9: .quad 4562098671269285104
; MEDIUM-P9-LABEL: test_double_const: ; MEDIUM-P9-LABEL: test_double_const:
; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]]) ; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]])
; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]:
; LARGE-P9: .quad 4562098671269285104 ; LARGE-P9: .quad 4562098671269285104
; LARGE-P9-LABEL: test_double_const: ; LARGE-P9-LABEL: test_double_const:
; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]])

llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll

Show All 40 Lines
; CHECK-VSX-DAG: std 6, 72(1) ; CHECK-VSX-DAG: std 6, 72(1)
; CHECK-VSX-DAG: std 5, 64(1) ; CHECK-VSX-DAG: std 5, 64(1)
; CHECK-VSX-DAG: std 4, 56(1) ; CHECK-VSX-DAG: std 4, 56(1)
; CHECK-VSX-DAG: std 3, 48(1) ; CHECK-VSX-DAG: std 3, 48(1)
; CHECK-VSX-DAG: std 5, -16(1) ; CHECK-VSX-DAG: std 5, -16(1)
; CHECK-VSX-DAG: std 6, -8(1) ; CHECK-VSX-DAG: std 6, -8(1)
; CHECK-VSX-DAG: addi [[REG1:[0-9]+]], 1, -16 ; CHECK-VSX-DAG: addi [[REG1:[0-9]+]], 1, -16
; CHECK-VSX-DAG: addi 3, 1, -8 ; CHECK-VSX-DAG: addi 3, 1, -8
; CHECK-VSX: lxsdx 1, 0, [[REG1]] ; CHECK-VSX: lfdx 1, 0, [[REG1]]
; CHECK-VSX: lxsdx 2, 0, 3 ; CHECK-VSX: lfdx 2, 0, 3
; FIXME-VSX: addi 4, 1, 48 ; FIXME-VSX: addi 4, 1, 48
; FIXME-VSX: lxsdx 1, 4, 3 ; FIXME-VSX: lxsdx 1, 4, 3
; FIXME-VSX: li 3, 24 ; FIXME-VSX: li 3, 24
; FIXME-VSX: lxsdx 2, 4, 3 ; FIXME-VSX: lxsdx 2, 4, 3
; CHECK-P9-DAG: std 6, 72(1) ; CHECK-P9-DAG: std 6, 72(1)
; CHECK-P9-DAG: std 5, 64(1) ; CHECK-P9-DAG: std 5, 64(1)
; CHECK-P9-DAG: std 4, 56(1) ; CHECK-P9-DAG: std 4, 56(1)
; CHECK-P9-DAG: std 3, 48(1) ; CHECK-P9-DAG: std 3, 48(1)
; CHECK-P9-DAG: mtvsrd 1, 5 ; CHECK-P9-DAG: mtvsrd 1, 5
; CHECK-P9-DAG: mtvsrd 2, 6 ; CHECK-P9-DAG: mtvsrd 2, 6

llvm/trunk/test/CodeGen/PowerPC/pr30715.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%11 = load float, float* %arrayidx.i, align 4 %11 = load float, float* %arrayidx.i, align 4
%conv = fpext float %11 to ppc_fp128 %conv = fpext float %11 to ppc_fp128
%add = fadd ppc_fp128 %conv, %conv %add = fadd ppc_fp128 %conv, %conv
%conv4 = fptrunc ppc_fp128 %add to float %conv4 = fptrunc ppc_fp128 %add to float
store float %conv4, float* %arrayidx.i, align 4 store float %conv4, float* %arrayidx.i, align 4
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
; CHECK: stxsdx ; CHECK: stfdx
; CHECK: lxvd2x ; CHECK: lxvd2x
} }
declare signext i32 @fn1(%class.FullMatrix*) local_unnamed_addr #1 declare signext i32 @fn1(%class.FullMatrix*) local_unnamed_addr #1

llvm/trunk/test/CodeGen/PowerPC/select_const.ll

Show First 20 Lines • Show All 646 Lines • ▼ Show 20 Lines
; ISEL-LABEL: sel_constants_fadd_constant: ; ISEL-LABEL: sel_constants_fadd_constant:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI34_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI34_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI34_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI34_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI34_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI34_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI34_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI34_1@toc@l
; ISEL-NEXT: isel 3, 3, 4, 1 ; ISEL-NEXT: isel 3, 3, 4, 1
; ISEL-NEXT: lxsdx 1, 0, 3 ; ISEL-NEXT: lfdx 1, 0, 3
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: sel_constants_fadd_constant: ; NO_ISEL-LABEL: sel_constants_fadd_constant:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI34_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI34_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI34_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI34_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI34_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI34_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI34_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI34_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB34_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB34_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB34_2 ; NO_ISEL-NEXT: b .LBB34_2
; NO_ISEL-NEXT: .LBB34_2: ; NO_ISEL-NEXT: .LBB34_2:
; NO_ISEL-NEXT: lxsdx 1, 0, 3 ; NO_ISEL-NEXT: lfdx 1, 0, 3
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fadd double %sel, 5.1 %bo = fadd double %sel, 5.1
ret double %bo ret double %bo
} }
define double @sel_constants_fsub_constant(i1 %cond) { define double @sel_constants_fsub_constant(i1 %cond) {
; ISEL-LABEL: sel_constants_fsub_constant: ; ISEL-LABEL: sel_constants_fsub_constant:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI35_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI35_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI35_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI35_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI35_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI35_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI35_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI35_1@toc@l
; ISEL-NEXT: isel 3, 3, 4, 1 ; ISEL-NEXT: isel 3, 3, 4, 1
; ISEL-NEXT: lxsdx 1, 0, 3 ; ISEL-NEXT: lfdx 1, 0, 3
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: sel_constants_fsub_constant: ; NO_ISEL-LABEL: sel_constants_fsub_constant:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI35_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI35_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI35_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI35_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI35_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI35_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI35_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI35_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB35_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB35_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB35_2 ; NO_ISEL-NEXT: b .LBB35_2
; NO_ISEL-NEXT: .LBB35_2: ; NO_ISEL-NEXT: .LBB35_2:
; NO_ISEL-NEXT: lxsdx 1, 0, 3 ; NO_ISEL-NEXT: lfdx 1, 0, 3
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fsub double %sel, 5.1 %bo = fsub double %sel, 5.1
ret double %bo ret double %bo
} }
define double @sel_constants_fmul_constant(i1 %cond) { define double @sel_constants_fmul_constant(i1 %cond) {
; ISEL-LABEL: sel_constants_fmul_constant: ; ISEL-LABEL: sel_constants_fmul_constant:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI36_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI36_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI36_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI36_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI36_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI36_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI36_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI36_1@toc@l
; ISEL-NEXT: isel 3, 3, 4, 1 ; ISEL-NEXT: isel 3, 3, 4, 1
; ISEL-NEXT: lxsdx 1, 0, 3 ; ISEL-NEXT: lfdx 1, 0, 3
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: sel_constants_fmul_constant: ; NO_ISEL-LABEL: sel_constants_fmul_constant:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI36_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI36_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI36_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI36_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI36_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI36_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI36_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI36_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB36_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB36_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB36_2 ; NO_ISEL-NEXT: b .LBB36_2
; NO_ISEL-NEXT: .LBB36_2: ; NO_ISEL-NEXT: .LBB36_2:
; NO_ISEL-NEXT: lxsdx 1, 0, 3 ; NO_ISEL-NEXT: lfdx 1, 0, 3
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fmul double %sel, 5.1 %bo = fmul double %sel, 5.1
ret double %bo ret double %bo
} }
define double @sel_constants_fdiv_constant(i1 %cond) { define double @sel_constants_fdiv_constant(i1 %cond) {
; ISEL-LABEL: sel_constants_fdiv_constant: ; ISEL-LABEL: sel_constants_fdiv_constant:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI37_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI37_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI37_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI37_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI37_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI37_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI37_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI37_1@toc@l
; ISEL-NEXT: isel 3, 3, 4, 1 ; ISEL-NEXT: isel 3, 3, 4, 1
; ISEL-NEXT: lxsdx 1, 0, 3 ; ISEL-NEXT: lfdx 1, 0, 3
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: sel_constants_fdiv_constant: ; NO_ISEL-LABEL: sel_constants_fdiv_constant:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI37_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI37_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI37_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI37_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI37_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI37_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI37_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI37_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB37_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB37_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB37_2 ; NO_ISEL-NEXT: b .LBB37_2
; NO_ISEL-NEXT: .LBB37_2: ; NO_ISEL-NEXT: .LBB37_2:
; NO_ISEL-NEXT: lxsdx 1, 0, 3 ; NO_ISEL-NEXT: lfdx 1, 0, 3
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fdiv double %sel, 5.1 %bo = fdiv double %sel, 5.1
ret double %bo ret double %bo
} }
define double @sel_constants_frem_constant(i1 %cond) { define double @sel_constants_frem_constant(i1 %cond) {
; ALL-LABEL: sel_constants_frem_constant: ; ALL-LABEL: sel_constants_frem_constant:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: andi. 3, 3, 1 ; ALL-NEXT: andi. 3, 3, 1
; ALL-NEXT: bc 12, 1, .LBB38_2 ; ALL-NEXT: bc 12, 1, .LBB38_2
; ALL-NEXT: # %bb.1: ; ALL-NEXT: # %bb.1:
; ALL-NEXT: addis 3, 2, .LCPI38_0@toc@ha ; ALL-NEXT: addis 3, 2, .LCPI38_0@toc@ha
; ALL-NEXT: addi 3, 3, .LCPI38_0@toc@l ; ALL-NEXT: addi 3, 3, .LCPI38_0@toc@l
; ALL-NEXT: lxsdx 1, 0, 3 ; ALL-NEXT: lfdx 1, 0, 3
; ALL-NEXT: blr ; ALL-NEXT: blr
; ALL-NEXT: .LBB38_2: ; ALL-NEXT: .LBB38_2:
; ALL-NEXT: addis 3, 2, .LCPI38_1@toc@ha ; ALL-NEXT: addis 3, 2, .LCPI38_1@toc@ha
; ALL-NEXT: addi 3, 3, .LCPI38_1@toc@l ; ALL-NEXT: addi 3, 3, .LCPI38_1@toc@l
; ALL-NEXT: lfsx 1, 0, 3 ; ALL-NEXT: lfsx 1, 0, 3
; ALL-NEXT: blr ; ALL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = frem double %sel, 5.1 %bo = frem double %sel, 5.1
ret double %bo ret double %bo
} }

llvm/trunk/test/CodeGen/PowerPC/store_fptoi.ll

Show All 16 Lines
; CHECK-LABEL: dpConv2sdw ; CHECK-LABEL: dpConv2sdw
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK: xscvdpsxds [[CONV:[0-9]+]], [[LD]] ; CHECK: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsd [[CONV]], 0(4) ; CHECK-NEXT: stxsd [[CONV]], 0(4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2sdw ; CHECK-PWR8-LABEL: dpConv2sdw
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4 ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2sw(double* nocapture readonly %a, i32* nocapture %b) { define void @dpConv2sw(double* nocapture readonly %a, i32* nocapture %b) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i32 %conv = fptosi double %0 to i32
store i32 %conv, i32* %b, align 4 store i32 %conv, i32* %b, align 4
ret void ret void
; CHECK-LABEL: dpConv2sw ; CHECK-LABEL: dpConv2sw
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stfiwx [[CONV]], 0, 4 ; CHECK-NEXT: stfiwx [[CONV]], 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2sw ; CHECK-PWR8-LABEL: dpConv2sw
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4 ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2shw(double* nocapture readonly %a, i16* nocapture %b) { define void @dpConv2shw(double* nocapture readonly %a, i16* nocapture %b) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i16 %conv = fptosi double %0 to i16
store i16 %conv, i16* %b, align 2 store i16 %conv, i16* %b, align 2
ret void ret void
; CHECK-LABEL: dpConv2shw ; CHECK-LABEL: dpConv2shw
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsihx [[CONV]], 0, 4 ; CHECK-NEXT: stxsihx [[CONV]], 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2shw ; CHECK-PWR8-LABEL: dpConv2shw
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
; CHECK-PWR8-NEXT: sth [[REG]], 0(4) ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2sb(double* nocapture readonly %a, i8* nocapture %b) { define void @dpConv2sb(double* nocapture readonly %a, i8* nocapture %b) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i8 %conv = fptosi double %0 to i8
store i8 %conv, i8* %b, align 1 store i8 %conv, i8* %b, align 1
ret void ret void
; CHECK-LABEL: dpConv2sb ; CHECK-LABEL: dpConv2sb
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsibx [[CONV]], 0, 4 ; CHECK-NEXT: stxsibx [[CONV]], 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2sb ; CHECK-PWR8-LABEL: dpConv2sb
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
; CHECK-PWR8-NEXT: stb [[REG]], 0(4) ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2sdw(float* nocapture readonly %a, i64* nocapture %b) { define void @spConv2sdw(float* nocapture readonly %a, i64* nocapture %b) {
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; CHECK-LABEL: dpConv2sdw_x ; CHECK-LABEL: dpConv2sdw_x
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3
; CHECK-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2sdw_x ; CHECK-PWR8-LABEL: dpConv2sdw_x
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3 ; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3
; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]] ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2sw_x(double* nocapture readonly %a, i32* nocapture %b, define void @dpConv2sw_x(double* nocapture readonly %a, i32* nocapture %b,
Show All 9 Lines
; CHECK-LABEL: dpConv2sw_x ; CHECK-LABEL: dpConv2sw_x
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2
; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2sw_x ; CHECK-PWR8-LABEL: dpConv2sw_x
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]] ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2shw_x(double* nocapture readonly %a, i16* nocapture %b, define void @dpConv2shw_x(double* nocapture readonly %a, i16* nocapture %b,
Show All 9 Lines
; CHECK-LABEL: dpConv2shw_x ; CHECK-LABEL: dpConv2shw_x
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 1 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 1
; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2shw_x ; CHECK-PWR8-LABEL: dpConv2shw_x
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5 ; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
Show All 9 Lines
; CHECK-LABEL: dpConv2sb_x ; CHECK-LABEL: dpConv2sb_x
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsibx [[CONV]], 4, 5 ; CHECK-NEXT: stxsibx [[CONV]], 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2sb_x ; CHECK-PWR8-LABEL: dpConv2sb_x
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2sdw_x(float* nocapture readonly %a, i64* nocapture %b, define void @spConv2sdw_x(float* nocapture readonly %a, i64* nocapture %b,
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; CHECK-LABEL: dpConv2udw ; CHECK-LABEL: dpConv2udw
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK: xscvdpuxds [[CONV:[0-9]+]], [[LD]] ; CHECK: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsd [[CONV]], 0(4) ; CHECK-NEXT: stxsd [[CONV]], 0(4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2udw ; CHECK-PWR8-LABEL: dpConv2udw
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4 ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2uw(double* nocapture readonly %a, i32* nocapture %b) { define void @dpConv2uw(double* nocapture readonly %a, i32* nocapture %b) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i32 %conv = fptoui double %0 to i32
store i32 %conv, i32* %b, align 4 store i32 %conv, i32* %b, align 4
ret void ret void
; CHECK-LABEL: dpConv2uw ; CHECK-LABEL: dpConv2uw
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stfiwx [[CONV]], 0, 4 ; CHECK-NEXT: stfiwx [[CONV]], 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2uw ; CHECK-PWR8-LABEL: dpConv2uw
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4 ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2uhw(double* nocapture readonly %a, i16* nocapture %b) { define void @dpConv2uhw(double* nocapture readonly %a, i16* nocapture %b) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i16 %conv = fptoui double %0 to i16
store i16 %conv, i16* %b, align 2 store i16 %conv, i16* %b, align 2
ret void ret void
; CHECK-LABEL: dpConv2uhw ; CHECK-LABEL: dpConv2uhw
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsihx [[CONV]], 0, 4 ; CHECK-NEXT: stxsihx [[CONV]], 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2uhw ; CHECK-PWR8-LABEL: dpConv2uhw
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
; CHECK-PWR8-NEXT: sth [[REG]], 0(4) ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2ub(double* nocapture readonly %a, i8* nocapture %b) { define void @dpConv2ub(double* nocapture readonly %a, i8* nocapture %b) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i8 %conv = fptoui double %0 to i8
store i8 %conv, i8* %b, align 1 store i8 %conv, i8* %b, align 1
ret void ret void
; CHECK-LABEL: dpConv2ub ; CHECK-LABEL: dpConv2ub
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsibx [[CONV]], 0, 4 ; CHECK-NEXT: stxsibx [[CONV]], 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2ub ; CHECK-PWR8-LABEL: dpConv2ub
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
; CHECK-PWR8-NEXT: stb [[REG]], 0(4) ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2udw(float* nocapture readonly %a, i64* nocapture %b) { define void @spConv2udw(float* nocapture readonly %a, i64* nocapture %b) {
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; CHECK-LABEL: dpConv2udw_x ; CHECK-LABEL: dpConv2udw_x
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3
; CHECK-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2udw_x ; CHECK-PWR8-LABEL: dpConv2udw_x
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3 ; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3
; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]] ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2uw_x(double* nocapture readonly %a, i32* nocapture %b, define void @dpConv2uw_x(double* nocapture readonly %a, i32* nocapture %b,
Show All 9 Lines
; CHECK-LABEL: dpConv2uw_x ; CHECK-LABEL: dpConv2uw_x
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2
; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2uw_x ; CHECK-PWR8-LABEL: dpConv2uw_x
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]] ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2uhw_x(double* nocapture readonly %a, i16* nocapture %b, define void @dpConv2uhw_x(double* nocapture readonly %a, i16* nocapture %b,
Show All 9 Lines
; CHECK-LABEL: dpConv2uhw_x ; CHECK-LABEL: dpConv2uhw_x
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 1 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 1
; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2uhw_x ; CHECK-PWR8-LABEL: dpConv2uhw_x
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5 ; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
Show All 9 Lines
; CHECK-LABEL: dpConv2ub_x ; CHECK-LABEL: dpConv2ub_x
; CHECK: lfd [[LD:[0-9]+]], 0(3) ; CHECK: lfd [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsibx [[CONV]], 4, 5 ; CHECK-NEXT: stxsibx [[CONV]], 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: dpConv2ub_x ; CHECK-PWR8-LABEL: dpConv2ub_x
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2udw_x(float* nocapture readonly %a, i64* nocapture %b, define void @spConv2udw_x(float* nocapture readonly %a, i64* nocapture %b,
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/swaps-le-6.ll

Show All 21 Linesentry:
%1 = load double, double* @y, align 8 %1 = load double, double* @y, align 8
%vecins = insertelement <2 x double> %0, double %1, i32 0 %vecins = insertelement <2 x double> %0, double %1, i32 0
store <2 x double> %vecins, <2 x double>* @z, align 16 store <2 x double> %vecins, <2 x double>* @z, align 16
ret void ret void
} }
; CHECK-LABEL: @bar0 ; CHECK-LABEL: @bar0
; CHECK-DAG: lxvd2x [[REG1:[0-9]+]] ; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
; CHECK-DAG: lxsdx [[REG2:[0-9]+]] ; CHECK-DAG: lfdx [[REG2:[0-9]+]]
; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0 ; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
; CHECK: xxpermdi [[REG5:[0-9]+]], [[REG4]], [[REG1]], 1 ; CHECK: xxpermdi [[REG5:[0-9]+]], [[REG4]], [[REG1]], 1
; CHECK: stxvd2x [[REG5]] ; CHECK: stxvd2x [[REG5]]
; CHECK-P9-LABEL: @bar0 ; CHECK-P9-LABEL: @bar0
; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]] ; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]]
; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3) ; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3)
; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0 ; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
; CHECK-P9: xxpermdi [[REG5:[0-9]+]], [[REG1]], [[REG4]], 1 ; CHECK-P9: xxpermdi [[REG5:[0-9]+]], [[REG1]], [[REG4]], 1
; CHECK-P9: stxvx [[REG5]] ; CHECK-P9: stxvx [[REG5]]
define void @bar1() { define void @bar1() {
entry: entry:
%0 = load <2 x double>, <2 x double>* @x, align 16 %0 = load <2 x double>, <2 x double>* @x, align 16
%1 = load double, double* @y, align 8 %1 = load double, double* @y, align 8
%vecins = insertelement <2 x double> %0, double %1, i32 1 %vecins = insertelement <2 x double> %0, double %1, i32 1
store <2 x double> %vecins, <2 x double>* @z, align 16 store <2 x double> %vecins, <2 x double>* @z, align 16
ret void ret void
} }
; CHECK-LABEL: @bar1 ; CHECK-LABEL: @bar1
; CHECK-DAG: lxvd2x [[REG1:[0-9]+]] ; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
; CHECK-DAG: lxsdx [[REG2:[0-9]+]] ; CHECK-DAG: lfdx [[REG2:[0-9]+]]
; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0 ; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
; CHECK: xxmrghd [[REG5:[0-9]+]], [[REG1]], [[REG4]] ; CHECK: xxmrghd [[REG5:[0-9]+]], [[REG1]], [[REG4]]
; CHECK: stxvd2x [[REG5]] ; CHECK: stxvd2x [[REG5]]
; CHECK-P9-LABEL: @bar1 ; CHECK-P9-LABEL: @bar1
; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]] ; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]]
; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3) ; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3)
; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0 ; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
; CHECK-P9: xxmrgld [[REG5:[0-9]+]], [[REG4]], [[REG1]] ; CHECK-P9: xxmrgld [[REG5:[0-9]+]], [[REG4]], [[REG1]]
; CHECK-P9: stxvx [[REG5]] ; CHECK-P9: stxvx [[REG5]]

llvm/trunk/test/CodeGen/PowerPC/unaligned.ll

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Linesentry:
store double %v, double* %r, align 1 store double %v, double* %r, align 1
ret void ret void
; CHECK: @foo5 ; CHECK: @foo5
; CHECK: lfd ; CHECK: lfd
; CHECK: stfd ; CHECK: stfd
; CHECK-VSX: @foo5 ; CHECK-VSX: @foo5
; CHECK-VSX: lxsdx ; CHECK-VSX: lfdx
; CHECK-VSX: stxsdx ; CHECK-VSX: stfdx
} }
define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind { define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind {
entry: entry:
%v = load <4 x float>, <4 x float>* %p, align 1 %v = load <4 x float>, <4 x float>* %p, align 1
store <4 x float> %v, <4 x float>* %r, align 1 store <4 x float> %v, <4 x float>* %r, align 1
ret void ret void
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llvm/trunk/test/CodeGen/PowerPC/vsx_insert_extract_le.ll

Show All 10 Lines
define <2 x double> @testi0(<2 x double>* %p1, double* %p2) { define <2 x double> @testi0(<2 x double>* %p1, double* %p2) {
%v = load <2 x double>, <2 x double>* %p1 %v = load <2 x double>, <2 x double>* %p1
%s = load double, double* %p2 %s = load double, double* %p2
%r = insertelement <2 x double> %v, double %s, i32 0 %r = insertelement <2 x double> %v, double %s, i32 0
ret <2 x double> %r ret <2 x double> %r
; CHECK-LABEL: testi0 ; CHECK-LABEL: testi0
; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 0, 0, 3
; CHECK: lxsdx 1, 0, 4 ; CHECK: lfdx 1, 0, 4
; CHECK-DAG: xxspltd 1, 1, 0 ; CHECK-DAG: xxspltd 1, 1, 0
; CHECK-DAG: xxswapd 0, 0 ; CHECK-DAG: xxswapd 0, 0
; CHECK: xxpermdi 34, 0, 1, 1 ; CHECK: xxpermdi 34, 0, 1, 1
; CHECK-P9-LABEL: testi0 ; CHECK-P9-LABEL: testi0
; CHECK-P9: lfd [[REG1:[0-9]+]], 0(4) ; CHECK-P9: lfd [[REG1:[0-9]+]], 0(4)
; CHECK-P9: lxv [[REG2:[0-9]+]], 0(3) ; CHECK-P9: lxv [[REG2:[0-9]+]], 0(3)
; CHECK-P9: xxspltd [[REG3:[0-9]+]], [[REG1]], 0 ; CHECK-P9: xxspltd [[REG3:[0-9]+]], [[REG1]], 0
; CHECK-P9: xxpermdi 34, [[REG2]], [[REG3]], 1 ; CHECK-P9: xxpermdi 34, [[REG2]], [[REG3]], 1
} }
define <2 x double> @testi1(<2 x double>* %p1, double* %p2) { define <2 x double> @testi1(<2 x double>* %p1, double* %p2) {
%v = load <2 x double>, <2 x double>* %p1 %v = load <2 x double>, <2 x double>* %p1
%s = load double, double* %p2 %s = load double, double* %p2
%r = insertelement <2 x double> %v, double %s, i32 1 %r = insertelement <2 x double> %v, double %s, i32 1
ret <2 x double> %r ret <2 x double> %r
; CHECK-LABEL: testi1 ; CHECK-LABEL: testi1
; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 0, 0, 3
; CHECK: lxsdx 1, 0, 4 ; CHECK: lfdx 1, 0, 4
; CHECK-DAG: xxspltd 1, 1, 0 ; CHECK-DAG: xxspltd 1, 1, 0
; CHECK-DAG: xxswapd 0, 0 ; CHECK-DAG: xxswapd 0, 0
; CHECK: xxmrgld 34, 1, 0 ; CHECK: xxmrgld 34, 1, 0
; CHECK-P9-LABEL: testi1 ; CHECK-P9-LABEL: testi1
; CHECK-P9: lfd [[REG1:[0-9]+]], 0(4) ; CHECK-P9: lfd [[REG1:[0-9]+]], 0(4)
; CHECK-P9: lxv [[REG2:[0-9]+]], 0(3) ; CHECK-P9: lxv [[REG2:[0-9]+]], 0(3)
; CHECK-P9: xxspltd [[REG3:[0-9]+]], [[REG1]], 0 ; CHECK-P9: xxspltd [[REG3:[0-9]+]], [[REG1]], 0
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llvm/trunk/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
define void @dblToFloat() #0 { define void @dblToFloat() #0 {
entry: entry:
%ff = alloca float, align 4 %ff = alloca float, align 4
%0 = load double, double* @d, align 8 %0 = load double, double* @d, align 8
%conv = fptrunc double %0 to float %conv = fptrunc double %0 to float
store volatile float %conv, float* %ff, align 4 store volatile float %conv, float* %ff, align 4
ret void ret void
; CHECK-LABEL: @dblToFloat ; CHECK-LABEL: @dblToFloat
; CHECK: lxsdx [[REGLD5:[0-9]+]], ; CHECK: lfdx [[REGLD5:[0-9]+]],
; CHECK: stfsx [[REGLD5]], ; CHECK: stfsx [[REGLD5]],
; CHECK-P9-LABEL: @dblToFloat ; CHECK-P9-LABEL: @dblToFloat
; CHECK-P9: lfd [[REGLD5:[0-9]+]], ; CHECK-P9: lfd [[REGLD5:[0-9]+]],
; CHECK-P9: stfs [[REGLD5]], ; CHECK-P9: stfs [[REGLD5]],
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @floatToDbl() #0 { define void @floatToDbl() #0 {
entry: entry:
%dd = alloca double, align 8 %dd = alloca double, align 8
%0 = load float, float* @f, align 4 %0 = load float, float* @f, align 4
%conv = fpext float %0 to double %conv = fpext float %0 to double
store volatile double %conv, double* %dd, align 8 store volatile double %conv, double* %dd, align 8
ret void ret void
; CHECK-LABEL: @floatToDbl ; CHECK-LABEL: @floatToDbl
; CHECK: lfsx [[REGLD5:[0-9]+]], ; CHECK: lfsx [[REGLD5:[0-9]+]],
; CHECK: stxsdx [[REGLD5]], ; CHECK: stfdx [[REGLD5]],
; CHECK-P9-LABEL: @floatToDbl ; CHECK-P9-LABEL: @floatToDbl
; CHECK-P9: lfs [[REGLD5:[0-9]+]], ; CHECK-P9: lfs [[REGLD5:[0-9]+]],
; CHECK-P9: stfd [[REGLD5]], ; CHECK-P9: stfd [[REGLD5]],
} }